mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/stm32f207xx.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/stm32f207xx.h@144:ef7eb2e8f9f7
Child:
167:e84263d55307
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f207xx.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V2.1.2
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS STM32F207xx Device Peripheral Access Layer Header File.
<> 144:ef7eb2e8f9f7 8 * This file contains :
<> 144:ef7eb2e8f9f7 9 * - Data structures and the address mapping for all peripherals
<> 144:ef7eb2e8f9f7 10 * - Peripherals registers declarations and bits definition
<> 144:ef7eb2e8f9f7 11 * - Macros to access peripheral’s registers hardware
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 ******************************************************************************
<> 144:ef7eb2e8f9f7 14 * @attention
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 44 * @{
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup stm32f207xx
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #ifndef __STM32F207xx_H
<> 144:ef7eb2e8f9f7 52 #define __STM32F207xx_H
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 55 extern "C" {
<> 144:ef7eb2e8f9f7 56 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @addtogroup Configuration_section_for_CMSIS
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 #define __CM3_REV 0x0200U /*!< Core revision r0p1 */
<> 144:ef7eb2e8f9f7 67 #define __MPU_PRESENT 1U /*!< STM32F2XX provides an MPU */
<> 144:ef7eb2e8f9f7 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F2XX uses 4 Bits for the Priority Levels */
<> 144:ef7eb2e8f9f7 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /**
<> 144:ef7eb2e8f9f7 72 * @}
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /** @addtogroup Peripheral_interrupt_number_definition
<> 144:ef7eb2e8f9f7 76 * @{
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @brief STM32F2XX Interrupt Number Definition, according to the selected device
<> 144:ef7eb2e8f9f7 81 * in @ref Library_configuration_section
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 typedef enum {
<> 144:ef7eb2e8f9f7 84 /****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/
<> 144:ef7eb2e8f9f7 85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 87 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 88 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 89 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 91 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 92 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 93 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 144:ef7eb2e8f9f7 94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 144:ef7eb2e8f9f7 95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 144:ef7eb2e8f9f7 96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 144:ef7eb2e8f9f7 97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 144:ef7eb2e8f9f7 98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 144:ef7eb2e8f9f7 99 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 144:ef7eb2e8f9f7 100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 144:ef7eb2e8f9f7 101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 144:ef7eb2e8f9f7 102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 144:ef7eb2e8f9f7 103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 144:ef7eb2e8f9f7 104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 144:ef7eb2e8f9f7 105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
<> 144:ef7eb2e8f9f7 111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
<> 144:ef7eb2e8f9f7 112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
<> 144:ef7eb2e8f9f7 113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
<> 144:ef7eb2e8f9f7 114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
<> 144:ef7eb2e8f9f7 115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
<> 144:ef7eb2e8f9f7 116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
<> 144:ef7eb2e8f9f7 117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 144:ef7eb2e8f9f7 118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
<> 144:ef7eb2e8f9f7 119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
<> 144:ef7eb2e8f9f7 120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
<> 144:ef7eb2e8f9f7 121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 144:ef7eb2e8f9f7 122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 144:ef7eb2e8f9f7 123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 144:ef7eb2e8f9f7 124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 144:ef7eb2e8f9f7 125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 144:ef7eb2e8f9f7 126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 144:ef7eb2e8f9f7 127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 144:ef7eb2e8f9f7 128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 144:ef7eb2e8f9f7 129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 144:ef7eb2e8f9f7 130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 144:ef7eb2e8f9f7 131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 144:ef7eb2e8f9f7 132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 144:ef7eb2e8f9f7 133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
<> 144:ef7eb2e8f9f7 134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 144:ef7eb2e8f9f7 135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
<> 144:ef7eb2e8f9f7 136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
<> 144:ef7eb2e8f9f7 137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
<> 144:ef7eb2e8f9f7 138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
<> 144:ef7eb2e8f9f7 139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
<> 144:ef7eb2e8f9f7 140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
<> 144:ef7eb2e8f9f7 141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
<> 144:ef7eb2e8f9f7 142 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
<> 144:ef7eb2e8f9f7 143 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
<> 144:ef7eb2e8f9f7 144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 144:ef7eb2e8f9f7 145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 144:ef7eb2e8f9f7 146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
<> 144:ef7eb2e8f9f7 147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
<> 144:ef7eb2e8f9f7 148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
<> 144:ef7eb2e8f9f7 149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
<> 144:ef7eb2e8f9f7 150 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 151 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 152 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 153 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 154 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 155 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
<> 144:ef7eb2e8f9f7 156 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
<> 144:ef7eb2e8f9f7 157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
<> 144:ef7eb2e8f9f7 158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
<> 144:ef7eb2e8f9f7 159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
<> 144:ef7eb2e8f9f7 160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
<> 144:ef7eb2e8f9f7 161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 144:ef7eb2e8f9f7 162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
<> 144:ef7eb2e8f9f7 163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
<> 144:ef7eb2e8f9f7 164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
<> 144:ef7eb2e8f9f7 165 USART6_IRQn = 71, /*!< USART6 global interrupt */
<> 144:ef7eb2e8f9f7 166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 144:ef7eb2e8f9f7 167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
<> 144:ef7eb2e8f9f7 168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
<> 144:ef7eb2e8f9f7 169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
<> 144:ef7eb2e8f9f7 170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
<> 144:ef7eb2e8f9f7 171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
<> 144:ef7eb2e8f9f7 172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
<> 144:ef7eb2e8f9f7 173 HASH_RNG_IRQn = 80 /*!< Hash and RNG global interrupt */
<> 144:ef7eb2e8f9f7 174 } IRQn_Type;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #include "core_cm3.h"
<> 144:ef7eb2e8f9f7 181 #include "system_stm32f2xx.h"
<> 144:ef7eb2e8f9f7 182 #include <stdint.h>
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /** @addtogroup Peripheral_registers_structures
<> 144:ef7eb2e8f9f7 185 * @{
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @brief Analog to Digital Converter
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 typedef struct {
<> 144:ef7eb2e8f9f7 193 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 194 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 195 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 196 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 197 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 198 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 199 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 200 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 201 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 202 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 203 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 204 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 205 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 206 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 207 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
<> 144:ef7eb2e8f9f7 208 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 209 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 210 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 212 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 213 } ADC_TypeDef;
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 typedef struct {
<> 144:ef7eb2e8f9f7 216 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
<> 144:ef7eb2e8f9f7 217 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 144:ef7eb2e8f9f7 218 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 144:ef7eb2e8f9f7 219 AND triple modes, Address offset: ADC1 base address + 0x308 */
<> 144:ef7eb2e8f9f7 220 } ADC_Common_TypeDef;
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Controller Area Network TxMailBox
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 typedef struct {
<> 144:ef7eb2e8f9f7 228 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
<> 144:ef7eb2e8f9f7 229 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 230 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
<> 144:ef7eb2e8f9f7 232 } CAN_TxMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief Controller Area Network FIFOMailBox
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 typedef struct {
<> 144:ef7eb2e8f9f7 239 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
<> 144:ef7eb2e8f9f7 240 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 241 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
<> 144:ef7eb2e8f9f7 242 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
<> 144:ef7eb2e8f9f7 243 } CAN_FIFOMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @brief Controller Area Network FilterRegister
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 typedef struct {
<> 144:ef7eb2e8f9f7 250 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 251 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 252 } CAN_FilterRegister_TypeDef;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @brief Controller Area Network
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 typedef struct {
<> 144:ef7eb2e8f9f7 259 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 260 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 261 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 262 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 263 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 264 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 265 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 266 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 267 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
<> 144:ef7eb2e8f9f7 268 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
<> 144:ef7eb2e8f9f7 269 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
<> 144:ef7eb2e8f9f7 270 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
<> 144:ef7eb2e8f9f7 271 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
<> 144:ef7eb2e8f9f7 272 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
<> 144:ef7eb2e8f9f7 273 uint32_t RESERVED2; /*!< Reserved, 0x208 */
<> 144:ef7eb2e8f9f7 274 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
<> 144:ef7eb2e8f9f7 275 uint32_t RESERVED3; /*!< Reserved, 0x210 */
<> 144:ef7eb2e8f9f7 276 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
<> 144:ef7eb2e8f9f7 277 uint32_t RESERVED4; /*!< Reserved, 0x218 */
<> 144:ef7eb2e8f9f7 278 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
<> 144:ef7eb2e8f9f7 279 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
<> 144:ef7eb2e8f9f7 280 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
<> 144:ef7eb2e8f9f7 281 } CAN_TypeDef;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @brief CRC calculation unit
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 typedef struct {
<> 144:ef7eb2e8f9f7 288 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 289 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 290 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 144:ef7eb2e8f9f7 291 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 144:ef7eb2e8f9f7 292 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 293 } CRC_TypeDef;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @brief Digital to Analog Converter
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 typedef struct {
<> 144:ef7eb2e8f9f7 300 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 301 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 302 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 303 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 304 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 305 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 306 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 307 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 308 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 309 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 310 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 311 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 312 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 313 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 314 } DAC_TypeDef;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief Debug MCU
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 typedef struct {
<> 144:ef7eb2e8f9f7 321 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 322 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 324 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 325 } DBGMCU_TypeDef;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @brief DCMI
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 typedef struct {
<> 144:ef7eb2e8f9f7 332 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 333 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 334 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 335 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 336 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 337 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 338 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 339 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 340 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 341 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 342 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 343 } DCMI_TypeDef;
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @brief DMA Controller
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 typedef struct {
<> 144:ef7eb2e8f9f7 350 __IO uint32_t CR; /*!< DMA stream x configuration register */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
<> 144:ef7eb2e8f9f7 352 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
<> 144:ef7eb2e8f9f7 353 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
<> 144:ef7eb2e8f9f7 354 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
<> 144:ef7eb2e8f9f7 355 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
<> 144:ef7eb2e8f9f7 356 } DMA_Stream_TypeDef;
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 typedef struct {
<> 144:ef7eb2e8f9f7 359 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 360 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 363 } DMA_TypeDef;
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @brief Ethernet MAC
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 typedef struct {
<> 144:ef7eb2e8f9f7 371 __IO uint32_t MACCR;
<> 144:ef7eb2e8f9f7 372 __IO uint32_t MACFFR;
<> 144:ef7eb2e8f9f7 373 __IO uint32_t MACHTHR;
<> 144:ef7eb2e8f9f7 374 __IO uint32_t MACHTLR;
<> 144:ef7eb2e8f9f7 375 __IO uint32_t MACMIIAR;
<> 144:ef7eb2e8f9f7 376 __IO uint32_t MACMIIDR;
<> 144:ef7eb2e8f9f7 377 __IO uint32_t MACFCR;
<> 144:ef7eb2e8f9f7 378 __IO uint32_t MACVLANTR; /* 8 */
<> 144:ef7eb2e8f9f7 379 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 380 __IO uint32_t MACRWUFFR; /* 11 */
<> 144:ef7eb2e8f9f7 381 __IO uint32_t MACPMTCSR;
<> 144:ef7eb2e8f9f7 382 uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 383 __IO uint32_t MACSR; /* 15 */
<> 144:ef7eb2e8f9f7 384 __IO uint32_t MACIMR;
<> 144:ef7eb2e8f9f7 385 __IO uint32_t MACA0HR;
<> 144:ef7eb2e8f9f7 386 __IO uint32_t MACA0LR;
<> 144:ef7eb2e8f9f7 387 __IO uint32_t MACA1HR;
<> 144:ef7eb2e8f9f7 388 __IO uint32_t MACA1LR;
<> 144:ef7eb2e8f9f7 389 __IO uint32_t MACA2HR;
<> 144:ef7eb2e8f9f7 390 __IO uint32_t MACA2LR;
<> 144:ef7eb2e8f9f7 391 __IO uint32_t MACA3HR;
<> 144:ef7eb2e8f9f7 392 __IO uint32_t MACA3LR; /* 24 */
<> 144:ef7eb2e8f9f7 393 uint32_t RESERVED2[40];
<> 144:ef7eb2e8f9f7 394 __IO uint32_t MMCCR; /* 65 */
<> 144:ef7eb2e8f9f7 395 __IO uint32_t MMCRIR;
<> 144:ef7eb2e8f9f7 396 __IO uint32_t MMCTIR;
<> 144:ef7eb2e8f9f7 397 __IO uint32_t MMCRIMR;
<> 144:ef7eb2e8f9f7 398 __IO uint32_t MMCTIMR; /* 69 */
<> 144:ef7eb2e8f9f7 399 uint32_t RESERVED3[14];
<> 144:ef7eb2e8f9f7 400 __IO uint32_t MMCTGFSCCR; /* 84 */
<> 144:ef7eb2e8f9f7 401 __IO uint32_t MMCTGFMSCCR;
<> 144:ef7eb2e8f9f7 402 uint32_t RESERVED4[5];
<> 144:ef7eb2e8f9f7 403 __IO uint32_t MMCTGFCR;
<> 144:ef7eb2e8f9f7 404 uint32_t RESERVED5[10];
<> 144:ef7eb2e8f9f7 405 __IO uint32_t MMCRFCECR;
<> 144:ef7eb2e8f9f7 406 __IO uint32_t MMCRFAECR;
<> 144:ef7eb2e8f9f7 407 uint32_t RESERVED6[10];
<> 144:ef7eb2e8f9f7 408 __IO uint32_t MMCRGUFCR;
<> 144:ef7eb2e8f9f7 409 uint32_t RESERVED7[334];
<> 144:ef7eb2e8f9f7 410 __IO uint32_t PTPTSCR;
<> 144:ef7eb2e8f9f7 411 __IO uint32_t PTPSSIR;
<> 144:ef7eb2e8f9f7 412 __IO uint32_t PTPTSHR;
<> 144:ef7eb2e8f9f7 413 __IO uint32_t PTPTSLR;
<> 144:ef7eb2e8f9f7 414 __IO uint32_t PTPTSHUR;
<> 144:ef7eb2e8f9f7 415 __IO uint32_t PTPTSLUR;
<> 144:ef7eb2e8f9f7 416 __IO uint32_t PTPTSAR;
<> 144:ef7eb2e8f9f7 417 __IO uint32_t PTPTTHR;
<> 144:ef7eb2e8f9f7 418 __IO uint32_t PTPTTLR;
<> 144:ef7eb2e8f9f7 419 __IO uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 420 __IO uint32_t PTPTSSR;
<> 144:ef7eb2e8f9f7 421 uint32_t RESERVED9[565];
<> 144:ef7eb2e8f9f7 422 __IO uint32_t DMABMR;
<> 144:ef7eb2e8f9f7 423 __IO uint32_t DMATPDR;
<> 144:ef7eb2e8f9f7 424 __IO uint32_t DMARPDR;
<> 144:ef7eb2e8f9f7 425 __IO uint32_t DMARDLAR;
<> 144:ef7eb2e8f9f7 426 __IO uint32_t DMATDLAR;
<> 144:ef7eb2e8f9f7 427 __IO uint32_t DMASR;
<> 144:ef7eb2e8f9f7 428 __IO uint32_t DMAOMR;
<> 144:ef7eb2e8f9f7 429 __IO uint32_t DMAIER;
<> 144:ef7eb2e8f9f7 430 __IO uint32_t DMAMFBOCR;
<> 144:ef7eb2e8f9f7 431 __IO uint32_t DMARSWTR;
<> 144:ef7eb2e8f9f7 432 uint32_t RESERVED10[8];
<> 144:ef7eb2e8f9f7 433 __IO uint32_t DMACHTDR;
<> 144:ef7eb2e8f9f7 434 __IO uint32_t DMACHRDR;
<> 144:ef7eb2e8f9f7 435 __IO uint32_t DMACHTBAR;
<> 144:ef7eb2e8f9f7 436 __IO uint32_t DMACHRBAR;
<> 144:ef7eb2e8f9f7 437 } ETH_TypeDef;
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * @brief External Interrupt/Event Controller
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 typedef struct {
<> 144:ef7eb2e8f9f7 444 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 445 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 446 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 447 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 448 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 449 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 450 } EXTI_TypeDef;
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @brief FLASH Registers
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 typedef struct {
<> 144:ef7eb2e8f9f7 457 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 458 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 459 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 460 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 461 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 462 __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 463 } FLASH_TypeDef;
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @brief Flexible Static Memory Controller
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 typedef struct {
<> 144:ef7eb2e8f9f7 471 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
<> 144:ef7eb2e8f9f7 472 } FSMC_Bank1_TypeDef;
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /**
<> 144:ef7eb2e8f9f7 475 * @brief Flexible Static Memory Controller Bank1E
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 typedef struct {
<> 144:ef7eb2e8f9f7 479 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
<> 144:ef7eb2e8f9f7 480 } FSMC_Bank1E_TypeDef;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @brief Flexible Static Memory Controller Bank2
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 typedef struct {
<> 144:ef7eb2e8f9f7 487 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 488 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 489 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
<> 144:ef7eb2e8f9f7 490 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
<> 144:ef7eb2e8f9f7 491 uint32_t RESERVED0; /*!< Reserved, 0x70 */
<> 144:ef7eb2e8f9f7 492 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 493 uint32_t RESERVED1; /*!< Reserved, 0x78 */
<> 144:ef7eb2e8f9f7 494 uint32_t RESERVED2; /*!< Reserved, 0x7C */
<> 144:ef7eb2e8f9f7 495 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 496 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 497 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 498 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 499 uint32_t RESERVED3; /*!< Reserved, 0x90 */
<> 144:ef7eb2e8f9f7 500 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 501 } FSMC_Bank2_3_TypeDef;
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief Flexible Static Memory Controller Bank4
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 typedef struct {
<> 144:ef7eb2e8f9f7 508 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
<> 144:ef7eb2e8f9f7 509 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
<> 144:ef7eb2e8f9f7 510 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
<> 144:ef7eb2e8f9f7 511 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
<> 144:ef7eb2e8f9f7 512 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
<> 144:ef7eb2e8f9f7 513 } FSMC_Bank4_TypeDef;
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @brief General Purpose I/O
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 typedef struct {
<> 144:ef7eb2e8f9f7 521 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 522 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 523 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 524 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 525 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 526 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 527 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 528 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 529 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 144:ef7eb2e8f9f7 530 } GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /**
<> 144:ef7eb2e8f9f7 533 * @brief System configuration controller
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 typedef struct {
<> 144:ef7eb2e8f9f7 537 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 538 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 539 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 144:ef7eb2e8f9f7 540 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
<> 144:ef7eb2e8f9f7 541 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 542 } SYSCFG_TypeDef;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @brief Inter-integrated Circuit Interface
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 typedef struct {
<> 144:ef7eb2e8f9f7 549 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 550 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 551 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 552 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 553 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 554 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 555 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 556 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 557 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 558 } I2C_TypeDef;
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @brief Independent WATCHDOG
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 typedef struct {
<> 144:ef7eb2e8f9f7 565 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 566 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 567 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 568 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 569 } IWDG_TypeDef;
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @brief Power Control
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 typedef struct {
<> 144:ef7eb2e8f9f7 576 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 577 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 578 } PWR_TypeDef;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @brief Reset and Clock Control
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 typedef struct {
<> 144:ef7eb2e8f9f7 585 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 586 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 587 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 588 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 589 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 590 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 591 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 592 uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 144:ef7eb2e8f9f7 593 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 594 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 595 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
<> 144:ef7eb2e8f9f7 596 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 597 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 598 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 599 uint32_t RESERVED2; /*!< Reserved, 0x3C */
<> 144:ef7eb2e8f9f7 600 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 601 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 602 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
<> 144:ef7eb2e8f9f7 603 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 604 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 605 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 606 uint32_t RESERVED4; /*!< Reserved, 0x5C */
<> 144:ef7eb2e8f9f7 607 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 608 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 609 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
<> 144:ef7eb2e8f9f7 610 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 611 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 612 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
<> 144:ef7eb2e8f9f7 613 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 614 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 } RCC_TypeDef;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @brief Real-Time Clock
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 typedef struct {
<> 144:ef7eb2e8f9f7 623 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 624 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 625 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 626 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 627 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 628 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 629 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 630 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 631 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 632 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 633 uint32_t RESERVED1; /*!< Reserved, 0x28 */
<> 144:ef7eb2e8f9f7 634 uint32_t RESERVED2; /*!< Reserved, 0x2C */
<> 144:ef7eb2e8f9f7 635 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 636 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 637 uint32_t RESERVED3; /*!< Reserved, 0x38 */
<> 144:ef7eb2e8f9f7 638 uint32_t RESERVED4; /*!< Reserved, 0x3C */
<> 144:ef7eb2e8f9f7 639 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 640 uint32_t RESERVED5; /*!< Reserved, 0x44 */
<> 144:ef7eb2e8f9f7 641 uint32_t RESERVED6; /*!< Reserved, 0x48 */
<> 144:ef7eb2e8f9f7 642 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 144:ef7eb2e8f9f7 643 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 644 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 645 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 646 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 144:ef7eb2e8f9f7 647 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 648 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 649 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 144:ef7eb2e8f9f7 650 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 144:ef7eb2e8f9f7 651 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 652 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 653 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 144:ef7eb2e8f9f7 654 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 144:ef7eb2e8f9f7 655 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 656 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 657 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 658 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 659 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 144:ef7eb2e8f9f7 660 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 661 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 144:ef7eb2e8f9f7 662 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 144:ef7eb2e8f9f7 663 } RTC_TypeDef;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @brief SD host Interface
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 typedef struct {
<> 144:ef7eb2e8f9f7 671 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 672 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 673 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 674 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 675 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 676 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 677 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 678 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 679 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 680 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 681 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 682 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 683 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 684 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 685 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 686 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 687 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
<> 144:ef7eb2e8f9f7 688 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 689 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
<> 144:ef7eb2e8f9f7 690 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 691 } SDIO_TypeDef;
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /**
<> 144:ef7eb2e8f9f7 694 * @brief Serial Peripheral Interface
<> 144:ef7eb2e8f9f7 695 */
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 typedef struct {
<> 144:ef7eb2e8f9f7 698 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 699 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 700 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 701 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 702 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 703 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 704 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 705 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 706 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 707 } SPI_TypeDef;
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /**
<> 144:ef7eb2e8f9f7 710 * @brief TIM
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 typedef struct {
<> 144:ef7eb2e8f9f7 714 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 715 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 716 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 717 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 718 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 719 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 720 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 721 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 722 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 723 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 724 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 725 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 726 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 727 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 728 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 729 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 730 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 731 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 732 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 733 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 734 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 735 } TIM_TypeDef;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /**
<> 144:ef7eb2e8f9f7 738 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 typedef struct {
<> 144:ef7eb2e8f9f7 742 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 743 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 744 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 745 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 746 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 747 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 748 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 749 } USART_TypeDef;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /**
<> 144:ef7eb2e8f9f7 752 * @brief Window WATCHDOG
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 typedef struct {
<> 144:ef7eb2e8f9f7 756 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 757 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 758 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 759 } WWDG_TypeDef;
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /**
<> 144:ef7eb2e8f9f7 763 * @brief RNG
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 typedef struct {
<> 144:ef7eb2e8f9f7 767 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 768 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 769 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 770 } RNG_TypeDef;
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /**
<> 144:ef7eb2e8f9f7 775 * @brief __USB_OTG_Core_register
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777 typedef struct {
<> 144:ef7eb2e8f9f7 778 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
<> 144:ef7eb2e8f9f7 779 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
<> 144:ef7eb2e8f9f7 780 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
<> 144:ef7eb2e8f9f7 781 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
<> 144:ef7eb2e8f9f7 782 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
<> 144:ef7eb2e8f9f7 783 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
<> 144:ef7eb2e8f9f7 784 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
<> 144:ef7eb2e8f9f7 785 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
<> 144:ef7eb2e8f9f7 786 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
<> 144:ef7eb2e8f9f7 787 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
<> 144:ef7eb2e8f9f7 788 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
<> 144:ef7eb2e8f9f7 789 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
<> 144:ef7eb2e8f9f7 790 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
<> 144:ef7eb2e8f9f7 791 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
<> 144:ef7eb2e8f9f7 792 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
<> 144:ef7eb2e8f9f7 793 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
<> 144:ef7eb2e8f9f7 794 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
<> 144:ef7eb2e8f9f7 795 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797 USB_OTG_GlobalTypeDef;
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /**
<> 144:ef7eb2e8f9f7 802 * @brief __device_Registers
<> 144:ef7eb2e8f9f7 803 */
<> 144:ef7eb2e8f9f7 804 typedef struct {
<> 144:ef7eb2e8f9f7 805 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
<> 144:ef7eb2e8f9f7 806 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
<> 144:ef7eb2e8f9f7 807 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
<> 144:ef7eb2e8f9f7 808 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
<> 144:ef7eb2e8f9f7 809 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
<> 144:ef7eb2e8f9f7 810 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
<> 144:ef7eb2e8f9f7 811 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
<> 144:ef7eb2e8f9f7 812 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
<> 144:ef7eb2e8f9f7 813 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
<> 144:ef7eb2e8f9f7 814 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
<> 144:ef7eb2e8f9f7 815 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
<> 144:ef7eb2e8f9f7 816 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
<> 144:ef7eb2e8f9f7 817 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
<> 144:ef7eb2e8f9f7 818 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
<> 144:ef7eb2e8f9f7 819 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
<> 144:ef7eb2e8f9f7 820 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
<> 144:ef7eb2e8f9f7 821 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
<> 144:ef7eb2e8f9f7 822 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
<> 144:ef7eb2e8f9f7 823 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
<> 144:ef7eb2e8f9f7 824 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826 USB_OTG_DeviceTypeDef;
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /**
<> 144:ef7eb2e8f9f7 830 * @brief __IN_Endpoint-Specific_Register
<> 144:ef7eb2e8f9f7 831 */
<> 144:ef7eb2e8f9f7 832 typedef struct {
<> 144:ef7eb2e8f9f7 833 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
<> 144:ef7eb2e8f9f7 834 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
<> 144:ef7eb2e8f9f7 835 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
<> 144:ef7eb2e8f9f7 836 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
<> 144:ef7eb2e8f9f7 837 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
<> 144:ef7eb2e8f9f7 838 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
<> 144:ef7eb2e8f9f7 839 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
<> 144:ef7eb2e8f9f7 840 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 USB_OTG_INEndpointTypeDef;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @brief __OUT_Endpoint-Specific_Registers
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 typedef struct {
<> 144:ef7eb2e8f9f7 849 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
<> 144:ef7eb2e8f9f7 850 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
<> 144:ef7eb2e8f9f7 851 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
<> 144:ef7eb2e8f9f7 852 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
<> 144:ef7eb2e8f9f7 853 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
<> 144:ef7eb2e8f9f7 854 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
<> 144:ef7eb2e8f9f7 855 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857 USB_OTG_OUTEndpointTypeDef;
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /**
<> 144:ef7eb2e8f9f7 861 * @brief __Host_Mode_Register_Structures
<> 144:ef7eb2e8f9f7 862 */
<> 144:ef7eb2e8f9f7 863 typedef struct {
<> 144:ef7eb2e8f9f7 864 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
<> 144:ef7eb2e8f9f7 865 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
<> 144:ef7eb2e8f9f7 866 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
<> 144:ef7eb2e8f9f7 867 uint32_t Reserved40C; /* Reserved 40Ch*/
<> 144:ef7eb2e8f9f7 868 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
<> 144:ef7eb2e8f9f7 869 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
<> 144:ef7eb2e8f9f7 870 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872 USB_OTG_HostTypeDef;
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 /**
<> 144:ef7eb2e8f9f7 876 * @brief __Host_Channel_Specific_Registers
<> 144:ef7eb2e8f9f7 877 */
<> 144:ef7eb2e8f9f7 878 typedef struct {
<> 144:ef7eb2e8f9f7 879 __IO uint32_t HCCHAR;
<> 144:ef7eb2e8f9f7 880 __IO uint32_t HCSPLT;
<> 144:ef7eb2e8f9f7 881 __IO uint32_t HCINT;
<> 144:ef7eb2e8f9f7 882 __IO uint32_t HCINTMSK;
<> 144:ef7eb2e8f9f7 883 __IO uint32_t HCTSIZ;
<> 144:ef7eb2e8f9f7 884 __IO uint32_t HCDMA;
<> 144:ef7eb2e8f9f7 885 uint32_t Reserved[2];
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887 USB_OTG_HostChannelTypeDef;
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /**
<> 144:ef7eb2e8f9f7 891 * @brief Peripheral_memory_map
<> 144:ef7eb2e8f9f7 892 */
<> 144:ef7eb2e8f9f7 893 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
<> 144:ef7eb2e8f9f7 894 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 895 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 896 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
<> 144:ef7eb2e8f9f7 897 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 898 #define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
<> 144:ef7eb2e8f9f7 899 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
<> 144:ef7eb2e8f9f7 900 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
<> 144:ef7eb2e8f9f7 901 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
<> 144:ef7eb2e8f9f7 902 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
<> 144:ef7eb2e8f9f7 903 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* Legacy defines */
<> 144:ef7eb2e8f9f7 906 #define SRAM_BASE SRAM1_BASE
<> 144:ef7eb2e8f9f7 907 #define SRAM_BB_BASE SRAM1_BB_BASE
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /*!< Peripheral memory map */
<> 144:ef7eb2e8f9f7 911 #define APB1PERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 912 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 144:ef7eb2e8f9f7 913 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 144:ef7eb2e8f9f7 914 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 917 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 918 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 919 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 920 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 921 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 922 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 923 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 924 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 925 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 926 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 927 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 928 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 929 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 930 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 931 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 932 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 933 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
<> 144:ef7eb2e8f9f7 934 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 935 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 936 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 937 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 144:ef7eb2e8f9f7 938 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 939 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
<> 144:ef7eb2e8f9f7 940 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 144:ef7eb2e8f9f7 941 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 944 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 945 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 946 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 947 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 948 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 949 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
<> 144:ef7eb2e8f9f7 950 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
<> 144:ef7eb2e8f9f7 951 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
<> 144:ef7eb2e8f9f7 952 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 953 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 954 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 955 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 956 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 957 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 958 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /*!< AHB1 peripherals */
<> 144:ef7eb2e8f9f7 961 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 962 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 963 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 964 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 965 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 966 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 967 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 968 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 969 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 970 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 971 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 972 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 973 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 974 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 975 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 976 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 977 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 978 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 979 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 980 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 981 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 982 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 983 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 984 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 985 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 986 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 987 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 988 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 989 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 990 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 991 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
<> 144:ef7eb2e8f9f7 992 #define ETH_MAC_BASE (ETH_BASE)
<> 144:ef7eb2e8f9f7 993 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
<> 144:ef7eb2e8f9f7 994 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
<> 144:ef7eb2e8f9f7 995 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /*!< AHB2 peripherals */
<> 144:ef7eb2e8f9f7 998 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
<> 144:ef7eb2e8f9f7 999 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /*!< FSMC Bankx registers base address */
<> 144:ef7eb2e8f9f7 1002 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1003 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
<> 144:ef7eb2e8f9f7 1004 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
<> 144:ef7eb2e8f9f7 1005 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Debug MCU registers base address */
<> 144:ef7eb2e8f9f7 1008 #define DBGMCU_BASE 0xE0042000U
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /*!< USB registers base address */
<> 144:ef7eb2e8f9f7 1011 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
<> 144:ef7eb2e8f9f7 1012 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 #define USB_OTG_GLOBAL_BASE 0x000U
<> 144:ef7eb2e8f9f7 1015 #define USB_OTG_DEVICE_BASE 0x800U
<> 144:ef7eb2e8f9f7 1016 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 144:ef7eb2e8f9f7 1017 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 144:ef7eb2e8f9f7 1018 #define USB_OTG_EP_REG_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1019 #define USB_OTG_HOST_BASE 0x400U
<> 144:ef7eb2e8f9f7 1020 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 144:ef7eb2e8f9f7 1021 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 144:ef7eb2e8f9f7 1022 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1023 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 144:ef7eb2e8f9f7 1024 #define USB_OTG_FIFO_BASE 0x1000U
<> 144:ef7eb2e8f9f7 1025 #define USB_OTG_FIFO_SIZE 0x1000U
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /**
<> 144:ef7eb2e8f9f7 1028 * @}
<> 144:ef7eb2e8f9f7 1029 */
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /** @addtogroup Peripheral_declaration
<> 144:ef7eb2e8f9f7 1032 * @{
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 144:ef7eb2e8f9f7 1035 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 144:ef7eb2e8f9f7 1036 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 144:ef7eb2e8f9f7 1037 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 144:ef7eb2e8f9f7 1038 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 144:ef7eb2e8f9f7 1039 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 144:ef7eb2e8f9f7 1040 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
<> 144:ef7eb2e8f9f7 1041 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
<> 144:ef7eb2e8f9f7 1042 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
<> 144:ef7eb2e8f9f7 1043 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 144:ef7eb2e8f9f7 1044 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 144:ef7eb2e8f9f7 1045 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 144:ef7eb2e8f9f7 1046 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 144:ef7eb2e8f9f7 1047 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 144:ef7eb2e8f9f7 1048 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 144:ef7eb2e8f9f7 1049 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 144:ef7eb2e8f9f7 1050 #define UART4 ((USART_TypeDef *) UART4_BASE)
<> 144:ef7eb2e8f9f7 1051 #define UART5 ((USART_TypeDef *) UART5_BASE)
<> 144:ef7eb2e8f9f7 1052 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 144:ef7eb2e8f9f7 1053 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 144:ef7eb2e8f9f7 1054 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 144:ef7eb2e8f9f7 1055 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
<> 144:ef7eb2e8f9f7 1056 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
<> 144:ef7eb2e8f9f7 1057 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 144:ef7eb2e8f9f7 1058 #define DAC ((DAC_TypeDef *) DAC_BASE)
<> 144:ef7eb2e8f9f7 1059 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 144:ef7eb2e8f9f7 1060 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
<> 144:ef7eb2e8f9f7 1061 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 144:ef7eb2e8f9f7 1062 #define USART6 ((USART_TypeDef *) USART6_BASE)
<> 144:ef7eb2e8f9f7 1063 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
<> 144:ef7eb2e8f9f7 1064 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 144:ef7eb2e8f9f7 1065 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
<> 144:ef7eb2e8f9f7 1066 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
<> 144:ef7eb2e8f9f7 1067 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
<> 144:ef7eb2e8f9f7 1068 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 144:ef7eb2e8f9f7 1069 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 144:ef7eb2e8f9f7 1070 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 144:ef7eb2e8f9f7 1071 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 144:ef7eb2e8f9f7 1072 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 144:ef7eb2e8f9f7 1073 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 144:ef7eb2e8f9f7 1074 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 144:ef7eb2e8f9f7 1075 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 144:ef7eb2e8f9f7 1076 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 144:ef7eb2e8f9f7 1077 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 144:ef7eb2e8f9f7 1078 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 144:ef7eb2e8f9f7 1079 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 144:ef7eb2e8f9f7 1080 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
<> 144:ef7eb2e8f9f7 1081 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 144:ef7eb2e8f9f7 1082 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
<> 144:ef7eb2e8f9f7 1083 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 144:ef7eb2e8f9f7 1084 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 144:ef7eb2e8f9f7 1085 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 144:ef7eb2e8f9f7 1086 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 144:ef7eb2e8f9f7 1087 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
<> 144:ef7eb2e8f9f7 1088 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
<> 144:ef7eb2e8f9f7 1089 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
<> 144:ef7eb2e8f9f7 1090 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
<> 144:ef7eb2e8f9f7 1091 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
<> 144:ef7eb2e8f9f7 1092 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
<> 144:ef7eb2e8f9f7 1093 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
<> 144:ef7eb2e8f9f7 1094 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
<> 144:ef7eb2e8f9f7 1095 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 144:ef7eb2e8f9f7 1096 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
<> 144:ef7eb2e8f9f7 1097 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
<> 144:ef7eb2e8f9f7 1098 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
<> 144:ef7eb2e8f9f7 1099 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
<> 144:ef7eb2e8f9f7 1100 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
<> 144:ef7eb2e8f9f7 1101 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
<> 144:ef7eb2e8f9f7 1102 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
<> 144:ef7eb2e8f9f7 1103 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
<> 144:ef7eb2e8f9f7 1104 #define ETH ((ETH_TypeDef *) ETH_BASE)
<> 144:ef7eb2e8f9f7 1105 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
<> 144:ef7eb2e8f9f7 1106 #define RNG ((RNG_TypeDef *) RNG_BASE)
<> 144:ef7eb2e8f9f7 1107 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
<> 144:ef7eb2e8f9f7 1108 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
<> 144:ef7eb2e8f9f7 1109 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
<> 144:ef7eb2e8f9f7 1110 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 144:ef7eb2e8f9f7 1115 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /**
<> 144:ef7eb2e8f9f7 1118 * @}
<> 144:ef7eb2e8f9f7 1119 */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /** @addtogroup Exported_constants
<> 144:ef7eb2e8f9f7 1122 * @{
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 144:ef7eb2e8f9f7 1126 * @{
<> 144:ef7eb2e8f9f7 1127 */
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1130 /* Peripheral Registers_Bits_Definition */
<> 144:ef7eb2e8f9f7 1131 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1134 /* */
<> 144:ef7eb2e8f9f7 1135 /* Analog to Digital Converter */
<> 144:ef7eb2e8f9f7 1136 /* */
<> 144:ef7eb2e8f9f7 1137 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1138 /******************** Bit definition for ADC_SR register ********************/
<> 144:ef7eb2e8f9f7 1139 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1140 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
<> 144:ef7eb2e8f9f7 1141 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1142 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1143 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1144 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /******************* Bit definition for ADC_CR1 register ********************/
<> 144:ef7eb2e8f9f7 1147 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 144:ef7eb2e8f9f7 1148 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1149 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1150 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1151 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1152 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1153 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
<> 144:ef7eb2e8f9f7 1154 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
<> 144:ef7eb2e8f9f7 1155 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
<> 144:ef7eb2e8f9f7 1156 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
<> 144:ef7eb2e8f9f7 1157 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
<> 144:ef7eb2e8f9f7 1158 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
<> 144:ef7eb2e8f9f7 1159 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
<> 144:ef7eb2e8f9f7 1160 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
<> 144:ef7eb2e8f9f7 1161 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
<> 144:ef7eb2e8f9f7 1162 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1163 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1164 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1165 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
<> 144:ef7eb2e8f9f7 1166 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
<> 144:ef7eb2e8f9f7 1167 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
<> 144:ef7eb2e8f9f7 1168 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1169 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1170 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /******************* Bit definition for ADC_CR2 register ********************/
<> 144:ef7eb2e8f9f7 1173 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
<> 144:ef7eb2e8f9f7 1174 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
<> 144:ef7eb2e8f9f7 1175 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
<> 144:ef7eb2e8f9f7 1176 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
<> 144:ef7eb2e8f9f7 1177 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
<> 144:ef7eb2e8f9f7 1178 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
<> 144:ef7eb2e8f9f7 1179 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
<> 144:ef7eb2e8f9f7 1180 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1181 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1182 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1183 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1184 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
<> 144:ef7eb2e8f9f7 1185 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1186 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1187 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
<> 144:ef7eb2e8f9f7 1188 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
<> 144:ef7eb2e8f9f7 1189 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1190 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1191 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1192 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1193 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
<> 144:ef7eb2e8f9f7 1194 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1195 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1196 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 144:ef7eb2e8f9f7 1199 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
<> 144:ef7eb2e8f9f7 1200 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1201 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1202 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1203 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
<> 144:ef7eb2e8f9f7 1204 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1205 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1206 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1207 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
<> 144:ef7eb2e8f9f7 1208 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1209 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1210 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1211 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
<> 144:ef7eb2e8f9f7 1212 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1213 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1214 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1215 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
<> 144:ef7eb2e8f9f7 1216 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1217 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1218 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1219 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
<> 144:ef7eb2e8f9f7 1220 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1221 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1222 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1223 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
<> 144:ef7eb2e8f9f7 1224 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1225 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1226 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1227 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
<> 144:ef7eb2e8f9f7 1228 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1229 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1230 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1231 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
<> 144:ef7eb2e8f9f7 1232 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1233 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1234 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 144:ef7eb2e8f9f7 1237 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
<> 144:ef7eb2e8f9f7 1238 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1239 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1240 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1241 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
<> 144:ef7eb2e8f9f7 1242 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1243 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1244 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1245 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
<> 144:ef7eb2e8f9f7 1246 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1247 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1248 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1249 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
<> 144:ef7eb2e8f9f7 1250 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1251 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1252 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1253 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
<> 144:ef7eb2e8f9f7 1254 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1255 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1256 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1257 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
<> 144:ef7eb2e8f9f7 1258 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1259 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1260 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1261 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
<> 144:ef7eb2e8f9f7 1262 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1263 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1264 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1265 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
<> 144:ef7eb2e8f9f7 1266 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1267 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1268 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1269 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
<> 144:ef7eb2e8f9f7 1270 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1271 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1272 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1273 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
<> 144:ef7eb2e8f9f7 1274 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1275 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1276 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 144:ef7eb2e8f9f7 1279 #define ADC_JOFR1_JOFFSET1 0x00000FFFU /*!<Data offset for injected channel 1 */
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 144:ef7eb2e8f9f7 1282 #define ADC_JOFR2_JOFFSET2 0x00000FFFU /*!<Data offset for injected channel 2 */
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 144:ef7eb2e8f9f7 1285 #define ADC_JOFR3_JOFFSET3 0x00000FFFU /*!<Data offset for injected channel 3 */
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 144:ef7eb2e8f9f7 1288 #define ADC_JOFR4_JOFFSET4 0x00000FFFU /*!<Data offset for injected channel 4 */
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 /******************* Bit definition for ADC_HTR register ********************/
<> 144:ef7eb2e8f9f7 1291 #define ADC_HTR_HT 0x00000FFFU /*!<Analog watchdog high threshold */
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 /******************* Bit definition for ADC_LTR register ********************/
<> 144:ef7eb2e8f9f7 1294 #define ADC_LTR_LT 0x00000FFFU /*!<Analog watchdog low threshold */
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /******************* Bit definition for ADC_SQR1 register *******************/
<> 144:ef7eb2e8f9f7 1297 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1298 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1299 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1300 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1301 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1302 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1303 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1304 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1305 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1306 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1307 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1308 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1309 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1310 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1311 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1312 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1313 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1314 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1315 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1316 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1317 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1318 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1319 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1320 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1321 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
<> 144:ef7eb2e8f9f7 1322 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1323 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1324 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1325 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /******************* Bit definition for ADC_SQR2 register *******************/
<> 144:ef7eb2e8f9f7 1328 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1329 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1330 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1331 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1332 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1333 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1334 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1335 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1336 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1337 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1338 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1339 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1340 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1341 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1342 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1343 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1344 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1345 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1346 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1347 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1348 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1349 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1350 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1351 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1352 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1353 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1354 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1355 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1356 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1357 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1358 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1359 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1360 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1361 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1362 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1363 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1364
<> 144:ef7eb2e8f9f7 1365 /******************* Bit definition for ADC_SQR3 register *******************/
<> 144:ef7eb2e8f9f7 1366 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1367 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1368 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1369 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1370 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1371 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1372 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1373 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1374 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1375 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1376 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1377 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1378 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1379 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1380 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1381 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1382 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1383 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1384 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1385 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1386 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1387 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1388 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1389 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1390 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1391 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1392 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1393 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1394 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1395 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1396 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1397 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1398 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1399 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1400 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1401 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /******************* Bit definition for ADC_JSQR register *******************/
<> 144:ef7eb2e8f9f7 1404 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1405 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1406 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1407 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1408 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1409 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1410 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1411 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1412 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1413 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1414 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1415 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1416 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1417 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1418 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1419 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1420 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1421 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1422 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1423 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1424 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1425 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1426 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1427 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1428 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
<> 144:ef7eb2e8f9f7 1429 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1430 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /******************* Bit definition for ADC_JDR1 register *******************/
<> 144:ef7eb2e8f9f7 1433 #define ADC_JDR1_JDATA 0x0000FFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /******************* Bit definition for ADC_JDR2 register *******************/
<> 144:ef7eb2e8f9f7 1436 #define ADC_JDR2_JDATA 0x0000FFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 /******************* Bit definition for ADC_JDR3 register *******************/
<> 144:ef7eb2e8f9f7 1439 #define ADC_JDR3_JDATA 0x0000FFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /******************* Bit definition for ADC_JDR4 register *******************/
<> 144:ef7eb2e8f9f7 1442 #define ADC_JDR4_JDATA 0x0000FFFFU /*!<Injected data */
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /******************** Bit definition for ADC_DR register ********************/
<> 144:ef7eb2e8f9f7 1445 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
<> 144:ef7eb2e8f9f7 1446 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /******************* Bit definition for ADC_CSR register ********************/
<> 144:ef7eb2e8f9f7 1449 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1450 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
<> 144:ef7eb2e8f9f7 1451 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1452 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1453 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1454 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1455 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1456 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
<> 144:ef7eb2e8f9f7 1457 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1458 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1459 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1460 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1461 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1462 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
<> 144:ef7eb2e8f9f7 1463 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1464 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1465 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1466 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1469 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 144:ef7eb2e8f9f7 1470 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 144:ef7eb2e8f9f7 1471 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /******************* Bit definition for ADC_CCR register ********************/
<> 144:ef7eb2e8f9f7 1474 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
<> 144:ef7eb2e8f9f7 1475 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1476 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1477 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1478 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1479 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1480 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
<> 144:ef7eb2e8f9f7 1481 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1482 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1483 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1484 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1485 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
<> 144:ef7eb2e8f9f7 1486 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
<> 144:ef7eb2e8f9f7 1487 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1488 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1489 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
<> 144:ef7eb2e8f9f7 1490 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1491 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1492 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
<> 144:ef7eb2e8f9f7 1493 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /******************* Bit definition for ADC_CDR register ********************/
<> 144:ef7eb2e8f9f7 1496 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
<> 144:ef7eb2e8f9f7 1497 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
<> 144:ef7eb2e8f9f7 1498
<> 144:ef7eb2e8f9f7 1499 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1500 /* */
<> 144:ef7eb2e8f9f7 1501 /* Controller Area Network */
<> 144:ef7eb2e8f9f7 1502 /* */
<> 144:ef7eb2e8f9f7 1503 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1504 /*!<CAN control and status registers */
<> 144:ef7eb2e8f9f7 1505 /******************* Bit definition for CAN_MCR register ********************/
<> 144:ef7eb2e8f9f7 1506 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
<> 144:ef7eb2e8f9f7 1507 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
<> 144:ef7eb2e8f9f7 1508 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
<> 144:ef7eb2e8f9f7 1509 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
<> 144:ef7eb2e8f9f7 1510 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
<> 144:ef7eb2e8f9f7 1511 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
<> 144:ef7eb2e8f9f7 1512 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
<> 144:ef7eb2e8f9f7 1513 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
<> 144:ef7eb2e8f9f7 1514 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
<> 144:ef7eb2e8f9f7 1515 #define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
<> 144:ef7eb2e8f9f7 1516 /******************* Bit definition for CAN_MSR register ********************/
<> 144:ef7eb2e8f9f7 1517 #define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */
<> 144:ef7eb2e8f9f7 1518 #define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */
<> 144:ef7eb2e8f9f7 1519 #define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */
<> 144:ef7eb2e8f9f7 1520 #define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 1521 #define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */
<> 144:ef7eb2e8f9f7 1522 #define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */
<> 144:ef7eb2e8f9f7 1523 #define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */
<> 144:ef7eb2e8f9f7 1524 #define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */
<> 144:ef7eb2e8f9f7 1525 #define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 /******************* Bit definition for CAN_TSR register ********************/
<> 144:ef7eb2e8f9f7 1528 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
<> 144:ef7eb2e8f9f7 1529 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
<> 144:ef7eb2e8f9f7 1530 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
<> 144:ef7eb2e8f9f7 1531 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
<> 144:ef7eb2e8f9f7 1532 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
<> 144:ef7eb2e8f9f7 1533 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
<> 144:ef7eb2e8f9f7 1534 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
<> 144:ef7eb2e8f9f7 1535 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
<> 144:ef7eb2e8f9f7 1536 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
<> 144:ef7eb2e8f9f7 1537 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
<> 144:ef7eb2e8f9f7 1538 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
<> 144:ef7eb2e8f9f7 1539 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
<> 144:ef7eb2e8f9f7 1540 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
<> 144:ef7eb2e8f9f7 1541 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
<> 144:ef7eb2e8f9f7 1542 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
<> 144:ef7eb2e8f9f7 1543 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
<> 144:ef7eb2e8f9f7 1546 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
<> 144:ef7eb2e8f9f7 1547 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
<> 144:ef7eb2e8f9f7 1548 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
<> 144:ef7eb2e8f9f7 1551 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
<> 144:ef7eb2e8f9f7 1552 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
<> 144:ef7eb2e8f9f7 1553 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 /******************* Bit definition for CAN_RF0R register *******************/
<> 144:ef7eb2e8f9f7 1556 #define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */
<> 144:ef7eb2e8f9f7 1557 #define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */
<> 144:ef7eb2e8f9f7 1558 #define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */
<> 144:ef7eb2e8f9f7 1559 #define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 /******************* Bit definition for CAN_RF1R register *******************/
<> 144:ef7eb2e8f9f7 1562 #define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */
<> 144:ef7eb2e8f9f7 1563 #define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */
<> 144:ef7eb2e8f9f7 1564 #define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */
<> 144:ef7eb2e8f9f7 1565 #define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 /******************** Bit definition for CAN_IER register *******************/
<> 144:ef7eb2e8f9f7 1568 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 1569 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
<> 144:ef7eb2e8f9f7 1570 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
<> 144:ef7eb2e8f9f7 1571 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
<> 144:ef7eb2e8f9f7 1572 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
<> 144:ef7eb2e8f9f7 1573 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
<> 144:ef7eb2e8f9f7 1574 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
<> 144:ef7eb2e8f9f7 1575 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
<> 144:ef7eb2e8f9f7 1576 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
<> 144:ef7eb2e8f9f7 1577 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
<> 144:ef7eb2e8f9f7 1578 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
<> 144:ef7eb2e8f9f7 1579 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 1580 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
<> 144:ef7eb2e8f9f7 1581 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
<> 144:ef7eb2e8f9f7 1582
<> 144:ef7eb2e8f9f7 1583 /******************** Bit definition for CAN_ESR register *******************/
<> 144:ef7eb2e8f9f7 1584 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
<> 144:ef7eb2e8f9f7 1585 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
<> 144:ef7eb2e8f9f7 1586 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
<> 144:ef7eb2e8f9f7 1589 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1590 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1591 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
<> 144:ef7eb2e8f9f7 1594 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 /******************* Bit definition for CAN_BTR register ********************/
<> 144:ef7eb2e8f9f7 1597 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
<> 144:ef7eb2e8f9f7 1598 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
<> 144:ef7eb2e8f9f7 1599 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1600 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1601 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1602 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1603 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
<> 144:ef7eb2e8f9f7 1604 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1605 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1606 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1607 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
<> 144:ef7eb2e8f9f7 1608 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1609 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1610 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
<> 144:ef7eb2e8f9f7 1611 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /*!<Mailbox registers */
<> 144:ef7eb2e8f9f7 1615 /****************** Bit definition for CAN_TI0R register ********************/
<> 144:ef7eb2e8f9f7 1616 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1617 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1618 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1619 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1620 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 /****************** Bit definition for CAN_TDT0R register *******************/
<> 144:ef7eb2e8f9f7 1623 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1624 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1625 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 /****************** Bit definition for CAN_TDL0R register *******************/
<> 144:ef7eb2e8f9f7 1628 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1629 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1630 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1631 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 /****************** Bit definition for CAN_TDH0R register *******************/
<> 144:ef7eb2e8f9f7 1634 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1635 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1636 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1637 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 /******************* Bit definition for CAN_TI1R register *******************/
<> 144:ef7eb2e8f9f7 1640 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1641 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1642 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1643 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1644 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1645
<> 144:ef7eb2e8f9f7 1646 /******************* Bit definition for CAN_TDT1R register ******************/
<> 144:ef7eb2e8f9f7 1647 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1648 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1649 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 /******************* Bit definition for CAN_TDL1R register ******************/
<> 144:ef7eb2e8f9f7 1652 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1653 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1654 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1655 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /******************* Bit definition for CAN_TDH1R register ******************/
<> 144:ef7eb2e8f9f7 1658 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1659 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1660 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1661 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 /******************* Bit definition for CAN_TI2R register *******************/
<> 144:ef7eb2e8f9f7 1664 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1665 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1666 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1667 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
<> 144:ef7eb2e8f9f7 1668 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 /******************* Bit definition for CAN_TDT2R register ******************/
<> 144:ef7eb2e8f9f7 1671 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1672 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1673 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1674
<> 144:ef7eb2e8f9f7 1675 /******************* Bit definition for CAN_TDL2R register ******************/
<> 144:ef7eb2e8f9f7 1676 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1677 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1678 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1679 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1680
<> 144:ef7eb2e8f9f7 1681 /******************* Bit definition for CAN_TDH2R register ******************/
<> 144:ef7eb2e8f9f7 1682 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1683 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1684 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1685 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /******************* Bit definition for CAN_RI0R register *******************/
<> 144:ef7eb2e8f9f7 1688 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1689 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1690 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1691 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 /******************* Bit definition for CAN_RDT0R register ******************/
<> 144:ef7eb2e8f9f7 1694 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1695 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
<> 144:ef7eb2e8f9f7 1696 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 /******************* Bit definition for CAN_RDL0R register ******************/
<> 144:ef7eb2e8f9f7 1699 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1700 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1701 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1702 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 /******************* Bit definition for CAN_RDH0R register ******************/
<> 144:ef7eb2e8f9f7 1705 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1706 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1707 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1708 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 /******************* Bit definition for CAN_RI1R register *******************/
<> 144:ef7eb2e8f9f7 1711 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1712 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1713 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
<> 144:ef7eb2e8f9f7 1714 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /******************* Bit definition for CAN_RDT1R register ******************/
<> 144:ef7eb2e8f9f7 1717 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1718 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
<> 144:ef7eb2e8f9f7 1719 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /******************* Bit definition for CAN_RDL1R register ******************/
<> 144:ef7eb2e8f9f7 1722 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1723 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1724 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1725 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 1726
<> 144:ef7eb2e8f9f7 1727 /******************* Bit definition for CAN_RDH1R register ******************/
<> 144:ef7eb2e8f9f7 1728 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1729 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1730 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1731 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 /*!<CAN filter registers */
<> 144:ef7eb2e8f9f7 1734 /******************* Bit definition for CAN_FMR register ********************/
<> 144:ef7eb2e8f9f7 1735 #define CAN_FMR_FINIT 0x00000001U /*!<Filter Init Mode */
<> 144:ef7eb2e8f9f7 1736 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
<> 144:ef7eb2e8f9f7 1737
<> 144:ef7eb2e8f9f7 1738 /************* Bit definition for CAN_FM1R register *******************/
<> 144:ef7eb2e8f9f7 1739 #define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
<> 144:ef7eb2e8f9f7 1740 #define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
<> 144:ef7eb2e8f9f7 1741 #define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
<> 144:ef7eb2e8f9f7 1742 #define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
<> 144:ef7eb2e8f9f7 1743 #define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
<> 144:ef7eb2e8f9f7 1744 #define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
<> 144:ef7eb2e8f9f7 1745 #define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
<> 144:ef7eb2e8f9f7 1746 #define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
<> 144:ef7eb2e8f9f7 1747 #define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
<> 144:ef7eb2e8f9f7 1748 #define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
<> 144:ef7eb2e8f9f7 1749 #define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
<> 144:ef7eb2e8f9f7 1750 #define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
<> 144:ef7eb2e8f9f7 1751 #define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
<> 144:ef7eb2e8f9f7 1752 #define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
<> 144:ef7eb2e8f9f7 1753 #define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
<> 144:ef7eb2e8f9f7 1754 #define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
<> 144:ef7eb2e8f9f7 1755 #define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
<> 144:ef7eb2e8f9f7 1756 #define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
<> 144:ef7eb2e8f9f7 1757 #define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
<> 144:ef7eb2e8f9f7 1758 #define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
<> 144:ef7eb2e8f9f7 1759 #define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
<> 144:ef7eb2e8f9f7 1760 #define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
<> 144:ef7eb2e8f9f7 1761 #define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
<> 144:ef7eb2e8f9f7 1762 #define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
<> 144:ef7eb2e8f9f7 1763 #define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
<> 144:ef7eb2e8f9f7 1764 #define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
<> 144:ef7eb2e8f9f7 1765 #define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
<> 144:ef7eb2e8f9f7 1766 #define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
<> 144:ef7eb2e8f9f7 1767 #define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 /******************* Bit definition for CAN_FS1R register *******************/
<> 144:ef7eb2e8f9f7 1770 #define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
<> 144:ef7eb2e8f9f7 1771 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
<> 144:ef7eb2e8f9f7 1772 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
<> 144:ef7eb2e8f9f7 1773 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
<> 144:ef7eb2e8f9f7 1774 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
<> 144:ef7eb2e8f9f7 1775 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
<> 144:ef7eb2e8f9f7 1776 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
<> 144:ef7eb2e8f9f7 1777 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
<> 144:ef7eb2e8f9f7 1778 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
<> 144:ef7eb2e8f9f7 1779 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
<> 144:ef7eb2e8f9f7 1780 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
<> 144:ef7eb2e8f9f7 1781 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
<> 144:ef7eb2e8f9f7 1782 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
<> 144:ef7eb2e8f9f7 1783 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
<> 144:ef7eb2e8f9f7 1784 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
<> 144:ef7eb2e8f9f7 1785 #define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
<> 144:ef7eb2e8f9f7 1786 #define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
<> 144:ef7eb2e8f9f7 1787 #define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
<> 144:ef7eb2e8f9f7 1788 #define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
<> 144:ef7eb2e8f9f7 1789 #define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
<> 144:ef7eb2e8f9f7 1790 #define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
<> 144:ef7eb2e8f9f7 1791 #define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
<> 144:ef7eb2e8f9f7 1792 #define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
<> 144:ef7eb2e8f9f7 1793 #define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
<> 144:ef7eb2e8f9f7 1794 #define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
<> 144:ef7eb2e8f9f7 1795 #define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
<> 144:ef7eb2e8f9f7 1796 #define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
<> 144:ef7eb2e8f9f7 1797 #define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
<> 144:ef7eb2e8f9f7 1798 #define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
<> 144:ef7eb2e8f9f7 1799
<> 144:ef7eb2e8f9f7 1800 /****************** Bit definition for CAN_FFA1R register *******************/
<> 144:ef7eb2e8f9f7 1801 #define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
<> 144:ef7eb2e8f9f7 1802 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
<> 144:ef7eb2e8f9f7 1803 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
<> 144:ef7eb2e8f9f7 1804 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
<> 144:ef7eb2e8f9f7 1805 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
<> 144:ef7eb2e8f9f7 1806 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
<> 144:ef7eb2e8f9f7 1807 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
<> 144:ef7eb2e8f9f7 1808 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
<> 144:ef7eb2e8f9f7 1809 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
<> 144:ef7eb2e8f9f7 1810 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
<> 144:ef7eb2e8f9f7 1811 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
<> 144:ef7eb2e8f9f7 1812 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
<> 144:ef7eb2e8f9f7 1813 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
<> 144:ef7eb2e8f9f7 1814 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
<> 144:ef7eb2e8f9f7 1815 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
<> 144:ef7eb2e8f9f7 1816 #define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
<> 144:ef7eb2e8f9f7 1817 #define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
<> 144:ef7eb2e8f9f7 1818 #define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
<> 144:ef7eb2e8f9f7 1819 #define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
<> 144:ef7eb2e8f9f7 1820 #define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
<> 144:ef7eb2e8f9f7 1821 #define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
<> 144:ef7eb2e8f9f7 1822 #define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
<> 144:ef7eb2e8f9f7 1823 #define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
<> 144:ef7eb2e8f9f7 1824 #define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
<> 144:ef7eb2e8f9f7 1825 #define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
<> 144:ef7eb2e8f9f7 1826 #define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
<> 144:ef7eb2e8f9f7 1827 #define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
<> 144:ef7eb2e8f9f7 1828 #define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
<> 144:ef7eb2e8f9f7 1829 #define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /******************* Bit definition for CAN_FA1R register *******************/
<> 144:ef7eb2e8f9f7 1832 #define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
<> 144:ef7eb2e8f9f7 1833 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
<> 144:ef7eb2e8f9f7 1834 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
<> 144:ef7eb2e8f9f7 1835 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
<> 144:ef7eb2e8f9f7 1836 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
<> 144:ef7eb2e8f9f7 1837 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
<> 144:ef7eb2e8f9f7 1838 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
<> 144:ef7eb2e8f9f7 1839 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
<> 144:ef7eb2e8f9f7 1840 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
<> 144:ef7eb2e8f9f7 1841 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
<> 144:ef7eb2e8f9f7 1842 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
<> 144:ef7eb2e8f9f7 1843 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
<> 144:ef7eb2e8f9f7 1844 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
<> 144:ef7eb2e8f9f7 1845 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
<> 144:ef7eb2e8f9f7 1846 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
<> 144:ef7eb2e8f9f7 1847 #define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
<> 144:ef7eb2e8f9f7 1848 #define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
<> 144:ef7eb2e8f9f7 1849 #define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
<> 144:ef7eb2e8f9f7 1850 #define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
<> 144:ef7eb2e8f9f7 1851 #define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
<> 144:ef7eb2e8f9f7 1852 #define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
<> 144:ef7eb2e8f9f7 1853 #define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
<> 144:ef7eb2e8f9f7 1854 #define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
<> 144:ef7eb2e8f9f7 1855 #define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
<> 144:ef7eb2e8f9f7 1856 #define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
<> 144:ef7eb2e8f9f7 1857 #define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
<> 144:ef7eb2e8f9f7 1858 #define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
<> 144:ef7eb2e8f9f7 1859 #define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
<> 144:ef7eb2e8f9f7 1860 #define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 /******************* Bit definition for CAN_F0R1 register *******************/
<> 144:ef7eb2e8f9f7 1863 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 1864 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 1865 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 1866 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 1867 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 1868 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 1869 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 1870 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 1871 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 1872 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 1873 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 1874 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 1875 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 1876 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 1877 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 1878 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 1879 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 1880 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 1881 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 1882 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 1883 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 1884 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 1885 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 1886 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 1887 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 1888 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 1889 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 1890 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 1891 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 1892 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 1893 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 1894 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /******************* Bit definition for CAN_F1R1 register *******************/
<> 144:ef7eb2e8f9f7 1897 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 1898 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 1899 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 1900 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 1901 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 1902 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 1903 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 1904 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 1905 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 1906 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 1907 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 1908 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 1909 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 1910 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 1911 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 1912 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 1913 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 1914 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 1915 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 1916 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 1917 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 1918 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 1919 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 1920 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 1921 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 1922 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 1923 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 1924 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 1925 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 1926 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 1927 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 1928 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 /******************* Bit definition for CAN_F2R1 register *******************/
<> 144:ef7eb2e8f9f7 1931 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 1932 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 1933 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 1934 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 1935 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 1936 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 1937 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 1938 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 1939 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 1940 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 1941 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 1942 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 1943 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 1944 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 1945 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 1946 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 1947 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 1948 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 1949 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 1950 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 1951 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 1952 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 1953 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 1954 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 1955 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 1956 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 1957 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 1958 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 1959 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 1960 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 1961 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 1962 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 1963
<> 144:ef7eb2e8f9f7 1964 /******************* Bit definition for CAN_F3R1 register *******************/
<> 144:ef7eb2e8f9f7 1965 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 1966 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 1967 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 1968 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 1969 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 1970 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 1971 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 1972 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 1973 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 1974 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 1975 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 1976 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 1977 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 1978 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 1979 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 1980 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 1981 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 1982 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 1983 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 1984 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 1985 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 1986 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 1987 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 1988 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 1989 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 1990 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 1991 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 1992 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 1993 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 1994 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 1995 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 1996 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 1997
<> 144:ef7eb2e8f9f7 1998 /******************* Bit definition for CAN_F4R1 register *******************/
<> 144:ef7eb2e8f9f7 1999 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2000 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2001 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2002 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2003 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2004 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2005 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2006 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2007 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2008 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2009 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2010 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2011 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2012 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2013 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2014 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2015 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2016 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2017 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2018 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2019 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2020 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2021 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2022 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2023 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2024 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2025 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2026 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2027 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2028 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2029 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2030 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2031
<> 144:ef7eb2e8f9f7 2032 /******************* Bit definition for CAN_F5R1 register *******************/
<> 144:ef7eb2e8f9f7 2033 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2034 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2035 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2036 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2037 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2038 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2039 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2040 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2041 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2042 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2043 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2044 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2045 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2046 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2047 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2048 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2049 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2050 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2051 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2052 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2053 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2054 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2055 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2056 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2057 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2058 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2059 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2060 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2061 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2062 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2063 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2064 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2065
<> 144:ef7eb2e8f9f7 2066 /******************* Bit definition for CAN_F6R1 register *******************/
<> 144:ef7eb2e8f9f7 2067 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2068 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2069 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2070 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2071 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2072 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2073 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2074 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2075 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2076 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2077 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2078 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2079 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2080 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2081 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2082 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2083 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2084 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2085 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2086 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2087 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2088 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2089 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2090 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2091 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2092 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2093 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2094 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2095 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2096 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2097 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2098 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /******************* Bit definition for CAN_F7R1 register *******************/
<> 144:ef7eb2e8f9f7 2101 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2102 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2103 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2104 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2105 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2106 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2107 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2108 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2109 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2110 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2111 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2112 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2113 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2114 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2115 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2116 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2117 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2118 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2119 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2120 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2121 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2122 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2123 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2124 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2125 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2126 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2127 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2128 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2129 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2130 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2131 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2132 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2133
<> 144:ef7eb2e8f9f7 2134 /******************* Bit definition for CAN_F8R1 register *******************/
<> 144:ef7eb2e8f9f7 2135 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2136 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2137 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2138 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2139 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2140 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2141 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2142 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2143 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2144 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2145 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2146 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2147 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2148 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2149 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2150 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2151 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2152 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2153 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2154 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2155 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2156 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2157 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2158 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2159 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2160 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2161 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2162 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2163 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2164 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2165 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2166 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2167
<> 144:ef7eb2e8f9f7 2168 /******************* Bit definition for CAN_F9R1 register *******************/
<> 144:ef7eb2e8f9f7 2169 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2170 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2171 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2172 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2173 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2174 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2175 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2176 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2177 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2178 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2179 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2180 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2181 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2182 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2183 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2184 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2185 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2186 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2187 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2188 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2189 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2190 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2191 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2192 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2193 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2194 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2195 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2196 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2197 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2198 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2199 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2200 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2201
<> 144:ef7eb2e8f9f7 2202 /******************* Bit definition for CAN_F10R1 register ******************/
<> 144:ef7eb2e8f9f7 2203 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2204 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2205 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2206 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2207 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2208 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2209 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2210 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2211 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2212 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2213 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2214 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2215 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2216 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2217 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2218 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2219 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2220 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2221 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2222 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2223 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2224 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2225 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2226 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2227 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2228 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2229 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2230 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2231 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2232 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2233 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2234 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2235
<> 144:ef7eb2e8f9f7 2236 /******************* Bit definition for CAN_F11R1 register ******************/
<> 144:ef7eb2e8f9f7 2237 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2238 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2239 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2240 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2241 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2242 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2243 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2244 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2245 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2246 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2247 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2248 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2249 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2250 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2251 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2252 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2253 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2254 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2255 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2256 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2257 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2258 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2259 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2260 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2261 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2262 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2263 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2264 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2265 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2266 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2267 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2268 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2269
<> 144:ef7eb2e8f9f7 2270 /******************* Bit definition for CAN_F12R1 register ******************/
<> 144:ef7eb2e8f9f7 2271 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2272 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2273 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2274 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2275 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2276 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2277 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2278 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2279 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2280 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2281 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2282 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2283 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2284 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2285 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2286 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2287 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2288 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2289 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2290 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2291 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2292 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2293 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2294 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2295 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2296 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2297 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2298 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2299 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2300 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2301 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2302 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2303
<> 144:ef7eb2e8f9f7 2304 /******************* Bit definition for CAN_F13R1 register ******************/
<> 144:ef7eb2e8f9f7 2305 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2306 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2307 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2308 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2309 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2310 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2311 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2312 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2313 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2314 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2315 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2316 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2317 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2318 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2319 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2320 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2321 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2322 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2323 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2324 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2325 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2326 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2327 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2328 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2329 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2330 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2331 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2332 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2333 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2334 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2335 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2336 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 /******************* Bit definition for CAN_F0R2 register *******************/
<> 144:ef7eb2e8f9f7 2339 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2340 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2341 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2342 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2343 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2344 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2345 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2346 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2347 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2348 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2349 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2350 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2351 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2352 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2353 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2354 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2355 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2356 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2357 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2358 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2359 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2360 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2361 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2362 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2363 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2364 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2365 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2366 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2367 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2368 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2369 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2370 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2371
<> 144:ef7eb2e8f9f7 2372 /******************* Bit definition for CAN_F1R2 register *******************/
<> 144:ef7eb2e8f9f7 2373 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2374 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2375 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2376 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2377 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2378 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2379 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2380 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2381 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2382 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2383 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2384 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2385 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2386 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2387 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2388 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2389 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2390 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2391 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2392 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2393 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2394 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2395 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2396 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2397 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2398 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2399 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2400 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2401 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2402 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2403 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2404 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2405
<> 144:ef7eb2e8f9f7 2406 /******************* Bit definition for CAN_F2R2 register *******************/
<> 144:ef7eb2e8f9f7 2407 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2408 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2409 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2410 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2411 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2412 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2413 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2414 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2415 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2416 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2417 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2418 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2419 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2420 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2421 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2422 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2423 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2424 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2425 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2426 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2427 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2428 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2429 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2430 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2431 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2432 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2433 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2434 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2435 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2436 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2437 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2438 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2439
<> 144:ef7eb2e8f9f7 2440 /******************* Bit definition for CAN_F3R2 register *******************/
<> 144:ef7eb2e8f9f7 2441 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2442 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2443 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2444 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2445 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2446 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2447 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2448 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2449 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2450 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2451 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2452 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2453 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2454 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2455 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2456 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2457 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2458 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2459 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2460 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2461 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2462 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2463 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2464 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2465 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2466 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2467 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2468 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2469 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2470 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2471 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2472 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2473
<> 144:ef7eb2e8f9f7 2474 /******************* Bit definition for CAN_F4R2 register *******************/
<> 144:ef7eb2e8f9f7 2475 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2476 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2477 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2478 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2479 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2480 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2481 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2482 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2483 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2484 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2485 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2486 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2487 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2488 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2489 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2490 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2491 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2492 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2493 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2494 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2495 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2496 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2497 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2498 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2499 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2500 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2501 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2502 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2503 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2504 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2505 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2506 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2507
<> 144:ef7eb2e8f9f7 2508 /******************* Bit definition for CAN_F5R2 register *******************/
<> 144:ef7eb2e8f9f7 2509 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2510 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2511 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2512 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2513 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2514 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2515 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2516 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2517 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2518 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2519 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2520 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2521 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2522 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2523 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2524 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2525 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2526 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2527 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2528 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2529 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2530 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2531 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2532 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2533 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2534 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2535 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2536 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2537 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2538 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2539 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2540 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2541
<> 144:ef7eb2e8f9f7 2542 /******************* Bit definition for CAN_F6R2 register *******************/
<> 144:ef7eb2e8f9f7 2543 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2544 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2545 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2546 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2547 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2548 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2549 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2550 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2551 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2552 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2553 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2554 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2555 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2556 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2557 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2558 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2559 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2560 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2561 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2562 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2563 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2564 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2565 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2566 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2567 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2568 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2569 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2570 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2571 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2572 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2573 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2574 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2575
<> 144:ef7eb2e8f9f7 2576 /******************* Bit definition for CAN_F7R2 register *******************/
<> 144:ef7eb2e8f9f7 2577 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2578 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2579 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2580 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2581 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2582 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2583 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2584 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2585 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2586 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2587 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2588 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2589 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2590 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2591 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2592 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2593 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2594 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2595 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2596 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2597 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2598 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2599 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2600 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2601 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2602 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2603 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2604 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2605 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2606 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2607 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2608 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2609
<> 144:ef7eb2e8f9f7 2610 /******************* Bit definition for CAN_F8R2 register *******************/
<> 144:ef7eb2e8f9f7 2611 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2612 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2613 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2614 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2615 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2616 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2617 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2618 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2619 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2620 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2621 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2622 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2623 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2624 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2625 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2626 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2627 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2628 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2629 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2630 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2631 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2632 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2633 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2634 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2635 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2636 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2637 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2638 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2639 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2640 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2641 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2642 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2643
<> 144:ef7eb2e8f9f7 2644 /******************* Bit definition for CAN_F9R2 register *******************/
<> 144:ef7eb2e8f9f7 2645 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2646 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2647 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2648 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2649 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2650 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2651 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2652 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2653 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2654 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2655 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2656 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2657 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2658 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2659 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2660 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2661 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2662 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2663 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2664 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2665 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2666 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2667 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2668 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2669 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2670 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2671 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2672 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2673 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2674 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2675 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2676 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2677
<> 144:ef7eb2e8f9f7 2678 /******************* Bit definition for CAN_F10R2 register ******************/
<> 144:ef7eb2e8f9f7 2679 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2680 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2681 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2682 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2683 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2684 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2685 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2686 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2687 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2688 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2689 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2690 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2691 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2692 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2693 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2694 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2695 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2696 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2697 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2698 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2699 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2700 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2701 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2702 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2703 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2704 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2705 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2706 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2707 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2708 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2709 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2710 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2711
<> 144:ef7eb2e8f9f7 2712 /******************* Bit definition for CAN_F11R2 register ******************/
<> 144:ef7eb2e8f9f7 2713 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2714 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2715 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2716 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2717 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2718 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2719 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2720 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2721 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2722 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2723 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2724 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2725 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2726 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2727 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2728 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2729 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2730 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2731 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2732 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2733 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2734 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2735 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2736 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2737 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2738 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2739 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2740 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2741 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2742 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2743 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2744 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2745
<> 144:ef7eb2e8f9f7 2746 /******************* Bit definition for CAN_F12R2 register ******************/
<> 144:ef7eb2e8f9f7 2747 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2748 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2749 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2750 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2751 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2752 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2753 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2754 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2755 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2756 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2757 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2758 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2759 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2760 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2761 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2762 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2763 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2764 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2765 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2766 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2767 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2768 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2769 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2770 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2771 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2772 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2773 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2774 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2775 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2776 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2777 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2778 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2779
<> 144:ef7eb2e8f9f7 2780 /******************* Bit definition for CAN_F13R2 register ******************/
<> 144:ef7eb2e8f9f7 2781 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2782 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2783 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2784 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2785 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2786 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2787 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2788 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2789 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2790 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2791 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2792 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2793 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2794 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2795 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2796 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2797 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2798 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2799 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2800 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2801 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2802 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2803 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2804 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2805 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2806 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2807 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2808 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2809 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2810 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2811 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2812 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2813
<> 144:ef7eb2e8f9f7 2814 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2815 /* */
<> 144:ef7eb2e8f9f7 2816 /* CRC calculation unit */
<> 144:ef7eb2e8f9f7 2817 /* */
<> 144:ef7eb2e8f9f7 2818 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2819 /******************* Bit definition for CRC_DR register *********************/
<> 144:ef7eb2e8f9f7 2820 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
<> 144:ef7eb2e8f9f7 2821
<> 144:ef7eb2e8f9f7 2822
<> 144:ef7eb2e8f9f7 2823 /******************* Bit definition for CRC_IDR register ********************/
<> 144:ef7eb2e8f9f7 2824 #define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */
<> 144:ef7eb2e8f9f7 2825
<> 144:ef7eb2e8f9f7 2826
<> 144:ef7eb2e8f9f7 2827 /******************** Bit definition for CRC_CR register ********************/
<> 144:ef7eb2e8f9f7 2828 #define CRC_CR_RESET 0x00000001U /*!< RESET bit */
<> 144:ef7eb2e8f9f7 2829
<> 144:ef7eb2e8f9f7 2830 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2831 /* */
<> 144:ef7eb2e8f9f7 2832 /* Digital to Analog Converter */
<> 144:ef7eb2e8f9f7 2833 /* */
<> 144:ef7eb2e8f9f7 2834 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2835 /******************** Bit definition for DAC_CR register ********************/
<> 144:ef7eb2e8f9f7 2836 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
<> 144:ef7eb2e8f9f7 2837 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
<> 144:ef7eb2e8f9f7 2838 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
<> 144:ef7eb2e8f9f7 2839
<> 144:ef7eb2e8f9f7 2840 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 144:ef7eb2e8f9f7 2841 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2842 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2843 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2844
<> 144:ef7eb2e8f9f7 2845 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 2846 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2847 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2848
<> 144:ef7eb2e8f9f7 2849 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 2850 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2851 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2852 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2853 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2854
<> 144:ef7eb2e8f9f7 2855 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
<> 144:ef7eb2e8f9f7 2856 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
<> 144:ef7eb2e8f9f7 2857 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
<> 144:ef7eb2e8f9f7 2858 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
<> 144:ef7eb2e8f9f7 2859 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
<> 144:ef7eb2e8f9f7 2860
<> 144:ef7eb2e8f9f7 2861 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 144:ef7eb2e8f9f7 2862 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2863 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2864 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2865
<> 144:ef7eb2e8f9f7 2866 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 2867 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2868 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2869
<> 144:ef7eb2e8f9f7 2870 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 2871 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 2872 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 2873 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 2874 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 2875
<> 144:ef7eb2e8f9f7 2876 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
<> 144:ef7eb2e8f9f7 2877 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
<> 144:ef7eb2e8f9f7 2878
<> 144:ef7eb2e8f9f7 2879 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 144:ef7eb2e8f9f7 2880 #define DAC_SWTRIGR_SWTRIG1 0x00000001U /*!<DAC channel1 software trigger */
<> 144:ef7eb2e8f9f7 2881 #define DAC_SWTRIGR_SWTRIG2 0x00000002U /*!<DAC channel2 software trigger */
<> 144:ef7eb2e8f9f7 2882
<> 144:ef7eb2e8f9f7 2883 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 144:ef7eb2e8f9f7 2884 #define DAC_DHR12R1_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2885
<> 144:ef7eb2e8f9f7 2886 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 144:ef7eb2e8f9f7 2887 #define DAC_DHR12L1_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 2888
<> 144:ef7eb2e8f9f7 2889 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 144:ef7eb2e8f9f7 2890 #define DAC_DHR8R1_DACC1DHR 0x000000FFU /*!<DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2891
<> 144:ef7eb2e8f9f7 2892 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 144:ef7eb2e8f9f7 2893 #define DAC_DHR12R2_DACC2DHR 0x00000FFFU /*!<DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2894
<> 144:ef7eb2e8f9f7 2895 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 144:ef7eb2e8f9f7 2896 #define DAC_DHR12L2_DACC2DHR 0x0000FFF0U /*!<DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 2897
<> 144:ef7eb2e8f9f7 2898 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 144:ef7eb2e8f9f7 2899 #define DAC_DHR8R2_DACC2DHR 0x000000FFU /*!<DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2900
<> 144:ef7eb2e8f9f7 2901 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 144:ef7eb2e8f9f7 2902 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2903 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2904
<> 144:ef7eb2e8f9f7 2905 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 144:ef7eb2e8f9f7 2906 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 2907 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 2908
<> 144:ef7eb2e8f9f7 2909 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 144:ef7eb2e8f9f7 2910 #define DAC_DHR8RD_DACC1DHR 0x000000FFU /*!<DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2911 #define DAC_DHR8RD_DACC2DHR 0x0000FF00U /*!<DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 2912
<> 144:ef7eb2e8f9f7 2913 /******************* Bit definition for DAC_DOR1 register *******************/
<> 144:ef7eb2e8f9f7 2914 #define DAC_DOR1_DACC1DOR 0x00000FFFU /*!<DAC channel1 data output */
<> 144:ef7eb2e8f9f7 2915
<> 144:ef7eb2e8f9f7 2916 /******************* Bit definition for DAC_DOR2 register *******************/
<> 144:ef7eb2e8f9f7 2917 #define DAC_DOR2_DACC2DOR 0x00000FFFU /*!<DAC channel2 data output */
<> 144:ef7eb2e8f9f7 2918
<> 144:ef7eb2e8f9f7 2919 /******************** Bit definition for DAC_SR register ********************/
<> 144:ef7eb2e8f9f7 2920 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
<> 144:ef7eb2e8f9f7 2921 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
<> 144:ef7eb2e8f9f7 2922
<> 144:ef7eb2e8f9f7 2923 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2924 /* */
<> 144:ef7eb2e8f9f7 2925 /* Debug MCU */
<> 144:ef7eb2e8f9f7 2926 /* */
<> 144:ef7eb2e8f9f7 2927 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2928
<> 144:ef7eb2e8f9f7 2929 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2930 /* */
<> 144:ef7eb2e8f9f7 2931 /* DCMI */
<> 144:ef7eb2e8f9f7 2932 /* */
<> 144:ef7eb2e8f9f7 2933 /******************************************************************************/
<> 144:ef7eb2e8f9f7 2934 /******************** Bits definition for DCMI_CR register ******************/
<> 144:ef7eb2e8f9f7 2935 #define DCMI_CR_CAPTURE 0x00000001U
<> 144:ef7eb2e8f9f7 2936 #define DCMI_CR_CM 0x00000002U
<> 144:ef7eb2e8f9f7 2937 #define DCMI_CR_CROP 0x00000004U
<> 144:ef7eb2e8f9f7 2938 #define DCMI_CR_JPEG 0x00000008U
<> 144:ef7eb2e8f9f7 2939 #define DCMI_CR_ESS 0x00000010U
<> 144:ef7eb2e8f9f7 2940 #define DCMI_CR_PCKPOL 0x00000020U
<> 144:ef7eb2e8f9f7 2941 #define DCMI_CR_HSPOL 0x00000040U
<> 144:ef7eb2e8f9f7 2942 #define DCMI_CR_VSPOL 0x00000080U
<> 144:ef7eb2e8f9f7 2943 #define DCMI_CR_FCRC_0 0x00000100U
<> 144:ef7eb2e8f9f7 2944 #define DCMI_CR_FCRC_1 0x00000200U
<> 144:ef7eb2e8f9f7 2945 #define DCMI_CR_EDM_0 0x00000400U
<> 144:ef7eb2e8f9f7 2946 #define DCMI_CR_EDM_1 0x00000800U
<> 144:ef7eb2e8f9f7 2947 #define DCMI_CR_CRE 0x00001000U
<> 144:ef7eb2e8f9f7 2948 #define DCMI_CR_ENABLE 0x00004000U
<> 144:ef7eb2e8f9f7 2949
<> 144:ef7eb2e8f9f7 2950 /******************** Bits definition for DCMI_SR register ******************/
<> 144:ef7eb2e8f9f7 2951 #define DCMI_SR_HSYNC 0x00000001U
<> 144:ef7eb2e8f9f7 2952 #define DCMI_SR_VSYNC 0x00000002U
<> 144:ef7eb2e8f9f7 2953 #define DCMI_SR_FNE 0x00000004U
<> 144:ef7eb2e8f9f7 2954
<> 144:ef7eb2e8f9f7 2955 /******************** Bits definition for DCMI_RIS register *****************/
<> 144:ef7eb2e8f9f7 2956 #define DCMI_RIS_FRAME_RIS 0x00000001U
<> 144:ef7eb2e8f9f7 2957 #define DCMI_RIS_OVR_RIS 0x00000002U
<> 144:ef7eb2e8f9f7 2958 #define DCMI_RIS_ERR_RIS 0x00000004U
<> 144:ef7eb2e8f9f7 2959 #define DCMI_RIS_VSYNC_RIS 0x00000008U
<> 144:ef7eb2e8f9f7 2960 #define DCMI_RIS_LINE_RIS 0x00000010U
<> 144:ef7eb2e8f9f7 2961 /* Legacy defines */
<> 144:ef7eb2e8f9f7 2962 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
<> 144:ef7eb2e8f9f7 2963 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
<> 144:ef7eb2e8f9f7 2964 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
<> 144:ef7eb2e8f9f7 2965 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
<> 144:ef7eb2e8f9f7 2966 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
<> 144:ef7eb2e8f9f7 2967
<> 144:ef7eb2e8f9f7 2968 /******************** Bits definition for DCMI_IER register *****************/
<> 144:ef7eb2e8f9f7 2969 #define DCMI_IER_FRAME_IE 0x00000001U
<> 144:ef7eb2e8f9f7 2970 #define DCMI_IER_OVR_IE 0x00000002U
<> 144:ef7eb2e8f9f7 2971 #define DCMI_IER_ERR_IE 0x00000004U
<> 144:ef7eb2e8f9f7 2972 #define DCMI_IER_VSYNC_IE 0x00000008U
<> 144:ef7eb2e8f9f7 2973 #define DCMI_IER_LINE_IE 0x00000010U
<> 144:ef7eb2e8f9f7 2974 /* Legacy defines */
<> 144:ef7eb2e8f9f7 2975 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
<> 144:ef7eb2e8f9f7 2976
<> 144:ef7eb2e8f9f7 2977 /******************** Bits definition for DCMI_MIS register *****************/
<> 144:ef7eb2e8f9f7 2978 #define DCMI_MIS_FRAME_MIS 0x00000001U
<> 144:ef7eb2e8f9f7 2979 #define DCMI_MIS_OVR_MIS 0x00000002U
<> 144:ef7eb2e8f9f7 2980 #define DCMI_MIS_ERR_MIS 0x00000004U
<> 144:ef7eb2e8f9f7 2981 #define DCMI_MIS_VSYNC_MIS 0x00000008U
<> 144:ef7eb2e8f9f7 2982 #define DCMI_MIS_LINE_MIS 0x00000010U
<> 144:ef7eb2e8f9f7 2983
<> 144:ef7eb2e8f9f7 2984 /* Legacy defines */
<> 144:ef7eb2e8f9f7 2985 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
<> 144:ef7eb2e8f9f7 2986 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
<> 144:ef7eb2e8f9f7 2987 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
<> 144:ef7eb2e8f9f7 2988 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
<> 144:ef7eb2e8f9f7 2989 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
<> 144:ef7eb2e8f9f7 2990
<> 144:ef7eb2e8f9f7 2991 /******************** Bits definition for DCMI_ICR register *****************/
<> 144:ef7eb2e8f9f7 2992 #define DCMI_ICR_FRAME_ISC 0x00000001U
<> 144:ef7eb2e8f9f7 2993 #define DCMI_ICR_OVR_ISC 0x00000002U
<> 144:ef7eb2e8f9f7 2994 #define DCMI_ICR_ERR_ISC 0x00000004U
<> 144:ef7eb2e8f9f7 2995 #define DCMI_ICR_VSYNC_ISC 0x00000008U
<> 144:ef7eb2e8f9f7 2996 #define DCMI_ICR_LINE_ISC 0x00000010U
<> 144:ef7eb2e8f9f7 2997
<> 144:ef7eb2e8f9f7 2998 /* Legacy defines */
<> 144:ef7eb2e8f9f7 2999 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
<> 144:ef7eb2e8f9f7 3000
<> 144:ef7eb2e8f9f7 3001 /******************** Bits definition for DCMI_ESCR register ******************/
<> 144:ef7eb2e8f9f7 3002 #define DCMI_ESCR_FSC 0x000000FFU
<> 144:ef7eb2e8f9f7 3003 #define DCMI_ESCR_LSC 0x0000FF00U
<> 144:ef7eb2e8f9f7 3004 #define DCMI_ESCR_LEC 0x00FF0000U
<> 144:ef7eb2e8f9f7 3005 #define DCMI_ESCR_FEC 0xFF000000U
<> 144:ef7eb2e8f9f7 3006
<> 144:ef7eb2e8f9f7 3007 /******************** Bits definition for DCMI_ESUR register ******************/
<> 144:ef7eb2e8f9f7 3008 #define DCMI_ESUR_FSU 0x000000FFU
<> 144:ef7eb2e8f9f7 3009 #define DCMI_ESUR_LSU 0x0000FF00U
<> 144:ef7eb2e8f9f7 3010 #define DCMI_ESUR_LEU 0x00FF0000U
<> 144:ef7eb2e8f9f7 3011 #define DCMI_ESUR_FEU 0xFF000000U
<> 144:ef7eb2e8f9f7 3012
<> 144:ef7eb2e8f9f7 3013 /******************** Bits definition for DCMI_CWSTRT register ******************/
<> 144:ef7eb2e8f9f7 3014 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
<> 144:ef7eb2e8f9f7 3015 #define DCMI_CWSTRT_VST 0x1FFF0000U
<> 144:ef7eb2e8f9f7 3016
<> 144:ef7eb2e8f9f7 3017 /******************** Bits definition for DCMI_CWSIZE register ******************/
<> 144:ef7eb2e8f9f7 3018 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
<> 144:ef7eb2e8f9f7 3019 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
<> 144:ef7eb2e8f9f7 3020
<> 144:ef7eb2e8f9f7 3021 /******************** Bits definition for DCMI_DR register ******************/
<> 144:ef7eb2e8f9f7 3022 #define DCMI_DR_BYTE0 0x000000FFU
<> 144:ef7eb2e8f9f7 3023 #define DCMI_DR_BYTE1 0x0000FF00U
<> 144:ef7eb2e8f9f7 3024 #define DCMI_DR_BYTE2 0x00FF0000U
<> 144:ef7eb2e8f9f7 3025 #define DCMI_DR_BYTE3 0xFF000000U
<> 144:ef7eb2e8f9f7 3026
<> 144:ef7eb2e8f9f7 3027 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3028 /* */
<> 144:ef7eb2e8f9f7 3029 /* DMA Controller */
<> 144:ef7eb2e8f9f7 3030 /* */
<> 144:ef7eb2e8f9f7 3031 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3032 /******************** Bits definition for DMA_SxCR register *****************/
<> 144:ef7eb2e8f9f7 3033 #define DMA_SxCR_CHSEL 0x0E000000U
<> 144:ef7eb2e8f9f7 3034 #define DMA_SxCR_CHSEL_0 0x02000000U
<> 144:ef7eb2e8f9f7 3035 #define DMA_SxCR_CHSEL_1 0x04000000U
<> 144:ef7eb2e8f9f7 3036 #define DMA_SxCR_CHSEL_2 0x08000000U
<> 144:ef7eb2e8f9f7 3037 #define DMA_SxCR_MBURST 0x01800000U
<> 144:ef7eb2e8f9f7 3038 #define DMA_SxCR_MBURST_0 0x00800000U
<> 144:ef7eb2e8f9f7 3039 #define DMA_SxCR_MBURST_1 0x01000000U
<> 144:ef7eb2e8f9f7 3040 #define DMA_SxCR_PBURST 0x00600000U
<> 144:ef7eb2e8f9f7 3041 #define DMA_SxCR_PBURST_0 0x00200000U
<> 144:ef7eb2e8f9f7 3042 #define DMA_SxCR_PBURST_1 0x00400000U
<> 144:ef7eb2e8f9f7 3043 #define DMA_SxCR_CT 0x00080000U
<> 144:ef7eb2e8f9f7 3044 #define DMA_SxCR_DBM 0x00040000U
<> 144:ef7eb2e8f9f7 3045 #define DMA_SxCR_PL 0x00030000U
<> 144:ef7eb2e8f9f7 3046 #define DMA_SxCR_PL_0 0x00010000U
<> 144:ef7eb2e8f9f7 3047 #define DMA_SxCR_PL_1 0x00020000U
<> 144:ef7eb2e8f9f7 3048 #define DMA_SxCR_PINCOS 0x00008000U
<> 144:ef7eb2e8f9f7 3049 #define DMA_SxCR_MSIZE 0x00006000U
<> 144:ef7eb2e8f9f7 3050 #define DMA_SxCR_MSIZE_0 0x00002000U
<> 144:ef7eb2e8f9f7 3051 #define DMA_SxCR_MSIZE_1 0x00004000U
<> 144:ef7eb2e8f9f7 3052 #define DMA_SxCR_PSIZE 0x00001800U
<> 144:ef7eb2e8f9f7 3053 #define DMA_SxCR_PSIZE_0 0x00000800U
<> 144:ef7eb2e8f9f7 3054 #define DMA_SxCR_PSIZE_1 0x00001000U
<> 144:ef7eb2e8f9f7 3055 #define DMA_SxCR_MINC 0x00000400U
<> 144:ef7eb2e8f9f7 3056 #define DMA_SxCR_PINC 0x00000200U
<> 144:ef7eb2e8f9f7 3057 #define DMA_SxCR_CIRC 0x00000100U
<> 144:ef7eb2e8f9f7 3058 #define DMA_SxCR_DIR 0x000000C0U
<> 144:ef7eb2e8f9f7 3059 #define DMA_SxCR_DIR_0 0x00000040U
<> 144:ef7eb2e8f9f7 3060 #define DMA_SxCR_DIR_1 0x00000080U
<> 144:ef7eb2e8f9f7 3061 #define DMA_SxCR_PFCTRL 0x00000020U
<> 144:ef7eb2e8f9f7 3062 #define DMA_SxCR_TCIE 0x00000010U
<> 144:ef7eb2e8f9f7 3063 #define DMA_SxCR_HTIE 0x00000008U
<> 144:ef7eb2e8f9f7 3064 #define DMA_SxCR_TEIE 0x00000004U
<> 144:ef7eb2e8f9f7 3065 #define DMA_SxCR_DMEIE 0x00000002U
<> 144:ef7eb2e8f9f7 3066 #define DMA_SxCR_EN 0x00000001U
<> 144:ef7eb2e8f9f7 3067
<> 144:ef7eb2e8f9f7 3068 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3069 #define DMA_SxCR_ACK 0x00100000U
<> 144:ef7eb2e8f9f7 3070
<> 144:ef7eb2e8f9f7 3071 /******************** Bits definition for DMA_SxCNDTR register **************/
<> 144:ef7eb2e8f9f7 3072 #define DMA_SxNDT 0x0000FFFFU
<> 144:ef7eb2e8f9f7 3073 #define DMA_SxNDT_0 0x00000001U
<> 144:ef7eb2e8f9f7 3074 #define DMA_SxNDT_1 0x00000002U
<> 144:ef7eb2e8f9f7 3075 #define DMA_SxNDT_2 0x00000004U
<> 144:ef7eb2e8f9f7 3076 #define DMA_SxNDT_3 0x00000008U
<> 144:ef7eb2e8f9f7 3077 #define DMA_SxNDT_4 0x00000010U
<> 144:ef7eb2e8f9f7 3078 #define DMA_SxNDT_5 0x00000020U
<> 144:ef7eb2e8f9f7 3079 #define DMA_SxNDT_6 0x00000040U
<> 144:ef7eb2e8f9f7 3080 #define DMA_SxNDT_7 0x00000080U
<> 144:ef7eb2e8f9f7 3081 #define DMA_SxNDT_8 0x00000100U
<> 144:ef7eb2e8f9f7 3082 #define DMA_SxNDT_9 0x00000200U
<> 144:ef7eb2e8f9f7 3083 #define DMA_SxNDT_10 0x00000400U
<> 144:ef7eb2e8f9f7 3084 #define DMA_SxNDT_11 0x00000800U
<> 144:ef7eb2e8f9f7 3085 #define DMA_SxNDT_12 0x00001000U
<> 144:ef7eb2e8f9f7 3086 #define DMA_SxNDT_13 0x00002000U
<> 144:ef7eb2e8f9f7 3087 #define DMA_SxNDT_14 0x00004000U
<> 144:ef7eb2e8f9f7 3088 #define DMA_SxNDT_15 0x00008000U
<> 144:ef7eb2e8f9f7 3089
<> 144:ef7eb2e8f9f7 3090 /******************** Bits definition for DMA_SxFCR register ****************/
<> 144:ef7eb2e8f9f7 3091 #define DMA_SxFCR_FEIE 0x00000080U
<> 144:ef7eb2e8f9f7 3092 #define DMA_SxFCR_FS 0x00000038U
<> 144:ef7eb2e8f9f7 3093 #define DMA_SxFCR_FS_0 0x00000008U
<> 144:ef7eb2e8f9f7 3094 #define DMA_SxFCR_FS_1 0x00000010U
<> 144:ef7eb2e8f9f7 3095 #define DMA_SxFCR_FS_2 0x00000020U
<> 144:ef7eb2e8f9f7 3096 #define DMA_SxFCR_DMDIS 0x00000004U
<> 144:ef7eb2e8f9f7 3097 #define DMA_SxFCR_FTH 0x00000003U
<> 144:ef7eb2e8f9f7 3098 #define DMA_SxFCR_FTH_0 0x00000001U
<> 144:ef7eb2e8f9f7 3099 #define DMA_SxFCR_FTH_1 0x00000002U
<> 144:ef7eb2e8f9f7 3100
<> 144:ef7eb2e8f9f7 3101 /******************** Bits definition for DMA_LISR register *****************/
<> 144:ef7eb2e8f9f7 3102 #define DMA_LISR_TCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 3103 #define DMA_LISR_HTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 3104 #define DMA_LISR_TEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 3105 #define DMA_LISR_DMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 3106 #define DMA_LISR_FEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 3107 #define DMA_LISR_TCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 3108 #define DMA_LISR_HTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 3109 #define DMA_LISR_TEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 3110 #define DMA_LISR_DMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 3111 #define DMA_LISR_FEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 3112 #define DMA_LISR_TCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 3113 #define DMA_LISR_HTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 3114 #define DMA_LISR_TEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 3115 #define DMA_LISR_DMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 3116 #define DMA_LISR_FEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 3117 #define DMA_LISR_TCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 3118 #define DMA_LISR_HTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 3119 #define DMA_LISR_TEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 3120 #define DMA_LISR_DMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 3121 #define DMA_LISR_FEIF0 0x00000001U
<> 144:ef7eb2e8f9f7 3122
<> 144:ef7eb2e8f9f7 3123 /******************** Bits definition for DMA_HISR register *****************/
<> 144:ef7eb2e8f9f7 3124 #define DMA_HISR_TCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 3125 #define DMA_HISR_HTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 3126 #define DMA_HISR_TEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 3127 #define DMA_HISR_DMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 3128 #define DMA_HISR_FEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 3129 #define DMA_HISR_TCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 3130 #define DMA_HISR_HTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 3131 #define DMA_HISR_TEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 3132 #define DMA_HISR_DMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 3133 #define DMA_HISR_FEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 3134 #define DMA_HISR_TCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 3135 #define DMA_HISR_HTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 3136 #define DMA_HISR_TEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 3137 #define DMA_HISR_DMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 3138 #define DMA_HISR_FEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 3139 #define DMA_HISR_TCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 3140 #define DMA_HISR_HTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 3141 #define DMA_HISR_TEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 3142 #define DMA_HISR_DMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 3143 #define DMA_HISR_FEIF4 0x00000001U
<> 144:ef7eb2e8f9f7 3144
<> 144:ef7eb2e8f9f7 3145 /******************** Bits definition for DMA_LIFCR register ****************/
<> 144:ef7eb2e8f9f7 3146 #define DMA_LIFCR_CTCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 3147 #define DMA_LIFCR_CHTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 3148 #define DMA_LIFCR_CTEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 3149 #define DMA_LIFCR_CDMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 3150 #define DMA_LIFCR_CFEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 3151 #define DMA_LIFCR_CTCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 3152 #define DMA_LIFCR_CHTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 3153 #define DMA_LIFCR_CTEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 3154 #define DMA_LIFCR_CDMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 3155 #define DMA_LIFCR_CFEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 3156 #define DMA_LIFCR_CTCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 3157 #define DMA_LIFCR_CHTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 3158 #define DMA_LIFCR_CTEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 3159 #define DMA_LIFCR_CDMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 3160 #define DMA_LIFCR_CFEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 3161 #define DMA_LIFCR_CTCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 3162 #define DMA_LIFCR_CHTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 3163 #define DMA_LIFCR_CTEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 3164 #define DMA_LIFCR_CDMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 3165 #define DMA_LIFCR_CFEIF0 0x00000001U
<> 144:ef7eb2e8f9f7 3166
<> 144:ef7eb2e8f9f7 3167 /******************** Bits definition for DMA_HIFCR register ****************/
<> 144:ef7eb2e8f9f7 3168 #define DMA_HIFCR_CTCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 3169 #define DMA_HIFCR_CHTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 3170 #define DMA_HIFCR_CTEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 3171 #define DMA_HIFCR_CDMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 3172 #define DMA_HIFCR_CFEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 3173 #define DMA_HIFCR_CTCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 3174 #define DMA_HIFCR_CHTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 3175 #define DMA_HIFCR_CTEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 3176 #define DMA_HIFCR_CDMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 3177 #define DMA_HIFCR_CFEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 3178 #define DMA_HIFCR_CTCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 3179 #define DMA_HIFCR_CHTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 3180 #define DMA_HIFCR_CTEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 3181 #define DMA_HIFCR_CDMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 3182 #define DMA_HIFCR_CFEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 3183 #define DMA_HIFCR_CTCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 3184 #define DMA_HIFCR_CHTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 3185 #define DMA_HIFCR_CTEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 3186 #define DMA_HIFCR_CDMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 3187 #define DMA_HIFCR_CFEIF4 0x00000001U
<> 144:ef7eb2e8f9f7 3188
<> 144:ef7eb2e8f9f7 3189
<> 144:ef7eb2e8f9f7 3190 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3191 /* */
<> 144:ef7eb2e8f9f7 3192 /* External Interrupt/Event Controller */
<> 144:ef7eb2e8f9f7 3193 /* */
<> 144:ef7eb2e8f9f7 3194 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3195 /******************* Bit definition for EXTI_IMR register *******************/
<> 144:ef7eb2e8f9f7 3196 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
<> 144:ef7eb2e8f9f7 3197 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
<> 144:ef7eb2e8f9f7 3198 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
<> 144:ef7eb2e8f9f7 3199 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
<> 144:ef7eb2e8f9f7 3200 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
<> 144:ef7eb2e8f9f7 3201 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
<> 144:ef7eb2e8f9f7 3202 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
<> 144:ef7eb2e8f9f7 3203 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
<> 144:ef7eb2e8f9f7 3204 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
<> 144:ef7eb2e8f9f7 3205 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
<> 144:ef7eb2e8f9f7 3206 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
<> 144:ef7eb2e8f9f7 3207 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
<> 144:ef7eb2e8f9f7 3208 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
<> 144:ef7eb2e8f9f7 3209 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
<> 144:ef7eb2e8f9f7 3210 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
<> 144:ef7eb2e8f9f7 3211 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
<> 144:ef7eb2e8f9f7 3212 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
<> 144:ef7eb2e8f9f7 3213 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
<> 144:ef7eb2e8f9f7 3214 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
<> 144:ef7eb2e8f9f7 3215 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
<> 144:ef7eb2e8f9f7 3216 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
<> 144:ef7eb2e8f9f7 3217 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
<> 144:ef7eb2e8f9f7 3218 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
<> 144:ef7eb2e8f9f7 3219
<> 144:ef7eb2e8f9f7 3220 /******************* Bit definition for EXTI_EMR register *******************/
<> 144:ef7eb2e8f9f7 3221 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
<> 144:ef7eb2e8f9f7 3222 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
<> 144:ef7eb2e8f9f7 3223 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
<> 144:ef7eb2e8f9f7 3224 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
<> 144:ef7eb2e8f9f7 3225 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
<> 144:ef7eb2e8f9f7 3226 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
<> 144:ef7eb2e8f9f7 3227 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
<> 144:ef7eb2e8f9f7 3228 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
<> 144:ef7eb2e8f9f7 3229 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
<> 144:ef7eb2e8f9f7 3230 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
<> 144:ef7eb2e8f9f7 3231 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
<> 144:ef7eb2e8f9f7 3232 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
<> 144:ef7eb2e8f9f7 3233 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
<> 144:ef7eb2e8f9f7 3234 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
<> 144:ef7eb2e8f9f7 3235 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
<> 144:ef7eb2e8f9f7 3236 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
<> 144:ef7eb2e8f9f7 3237 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
<> 144:ef7eb2e8f9f7 3238 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
<> 144:ef7eb2e8f9f7 3239 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
<> 144:ef7eb2e8f9f7 3240 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
<> 144:ef7eb2e8f9f7 3241 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
<> 144:ef7eb2e8f9f7 3242 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
<> 144:ef7eb2e8f9f7 3243 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
<> 144:ef7eb2e8f9f7 3244
<> 144:ef7eb2e8f9f7 3245 /****************** Bit definition for EXTI_RTSR register *******************/
<> 144:ef7eb2e8f9f7 3246 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 3247 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 3248 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 3249 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 3250 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 3251 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 3252 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 3253 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 3254 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 3255 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 3256 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 3257 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 3258 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 3259 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 3260 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 3261 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 3262 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 3263 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 3264 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 3265 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 3266 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 3267 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 3268 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 3269
<> 144:ef7eb2e8f9f7 3270 /****************** Bit definition for EXTI_FTSR register *******************/
<> 144:ef7eb2e8f9f7 3271 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 3272 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 3273 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 3274 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 3275 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 3276 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 3277 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 3278 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 3279 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 3280 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 3281 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 3282 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 3283 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 3284 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 3285 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 3286 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 3287 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 3288 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 3289 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 3290 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 3291 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 3292 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 3293 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 3294
<> 144:ef7eb2e8f9f7 3295 /****************** Bit definition for EXTI_SWIER register ******************/
<> 144:ef7eb2e8f9f7 3296 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
<> 144:ef7eb2e8f9f7 3297 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
<> 144:ef7eb2e8f9f7 3298 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
<> 144:ef7eb2e8f9f7 3299 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
<> 144:ef7eb2e8f9f7 3300 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
<> 144:ef7eb2e8f9f7 3301 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
<> 144:ef7eb2e8f9f7 3302 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
<> 144:ef7eb2e8f9f7 3303 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
<> 144:ef7eb2e8f9f7 3304 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
<> 144:ef7eb2e8f9f7 3305 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
<> 144:ef7eb2e8f9f7 3306 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
<> 144:ef7eb2e8f9f7 3307 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
<> 144:ef7eb2e8f9f7 3308 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
<> 144:ef7eb2e8f9f7 3309 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
<> 144:ef7eb2e8f9f7 3310 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
<> 144:ef7eb2e8f9f7 3311 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
<> 144:ef7eb2e8f9f7 3312 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
<> 144:ef7eb2e8f9f7 3313 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
<> 144:ef7eb2e8f9f7 3314 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
<> 144:ef7eb2e8f9f7 3315 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
<> 144:ef7eb2e8f9f7 3316 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
<> 144:ef7eb2e8f9f7 3317 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
<> 144:ef7eb2e8f9f7 3318 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
<> 144:ef7eb2e8f9f7 3319
<> 144:ef7eb2e8f9f7 3320 /******************* Bit definition for EXTI_PR register ********************/
<> 144:ef7eb2e8f9f7 3321 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
<> 144:ef7eb2e8f9f7 3322 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
<> 144:ef7eb2e8f9f7 3323 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
<> 144:ef7eb2e8f9f7 3324 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
<> 144:ef7eb2e8f9f7 3325 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
<> 144:ef7eb2e8f9f7 3326 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
<> 144:ef7eb2e8f9f7 3327 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
<> 144:ef7eb2e8f9f7 3328 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
<> 144:ef7eb2e8f9f7 3329 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
<> 144:ef7eb2e8f9f7 3330 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
<> 144:ef7eb2e8f9f7 3331 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
<> 144:ef7eb2e8f9f7 3332 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
<> 144:ef7eb2e8f9f7 3333 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
<> 144:ef7eb2e8f9f7 3334 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
<> 144:ef7eb2e8f9f7 3335 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
<> 144:ef7eb2e8f9f7 3336 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
<> 144:ef7eb2e8f9f7 3337 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
<> 144:ef7eb2e8f9f7 3338 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
<> 144:ef7eb2e8f9f7 3339 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
<> 144:ef7eb2e8f9f7 3340 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
<> 144:ef7eb2e8f9f7 3341 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
<> 144:ef7eb2e8f9f7 3342 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
<> 144:ef7eb2e8f9f7 3343 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
<> 144:ef7eb2e8f9f7 3344
<> 144:ef7eb2e8f9f7 3345 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3346 /* */
<> 144:ef7eb2e8f9f7 3347 /* FLASH */
<> 144:ef7eb2e8f9f7 3348 /* */
<> 144:ef7eb2e8f9f7 3349 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3350 /******************* Bits definition for FLASH_ACR register *****************/
<> 144:ef7eb2e8f9f7 3351 #define FLASH_ACR_LATENCY 0x0000000FU
<> 144:ef7eb2e8f9f7 3352 #define FLASH_ACR_LATENCY_0WS 0x00000000U
<> 144:ef7eb2e8f9f7 3353 #define FLASH_ACR_LATENCY_1WS 0x00000001U
<> 144:ef7eb2e8f9f7 3354 #define FLASH_ACR_LATENCY_2WS 0x00000002U
<> 144:ef7eb2e8f9f7 3355 #define FLASH_ACR_LATENCY_3WS 0x00000003U
<> 144:ef7eb2e8f9f7 3356 #define FLASH_ACR_LATENCY_4WS 0x00000004U
<> 144:ef7eb2e8f9f7 3357 #define FLASH_ACR_LATENCY_5WS 0x00000005U
<> 144:ef7eb2e8f9f7 3358 #define FLASH_ACR_LATENCY_6WS 0x00000006U
<> 144:ef7eb2e8f9f7 3359 #define FLASH_ACR_LATENCY_7WS 0x00000007U
<> 144:ef7eb2e8f9f7 3360
<> 144:ef7eb2e8f9f7 3361 #define FLASH_ACR_PRFTEN 0x00000100U
<> 144:ef7eb2e8f9f7 3362 #define FLASH_ACR_ICEN 0x00000200U
<> 144:ef7eb2e8f9f7 3363 #define FLASH_ACR_DCEN 0x00000400U
<> 144:ef7eb2e8f9f7 3364 #define FLASH_ACR_ICRST 0x00000800U
<> 144:ef7eb2e8f9f7 3365 #define FLASH_ACR_DCRST 0x00001000U
<> 144:ef7eb2e8f9f7 3366 #define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
<> 144:ef7eb2e8f9f7 3367 #define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
<> 144:ef7eb2e8f9f7 3368
<> 144:ef7eb2e8f9f7 3369 /******************* Bits definition for FLASH_SR register ******************/
<> 144:ef7eb2e8f9f7 3370 #define FLASH_SR_EOP 0x00000001U
<> 144:ef7eb2e8f9f7 3371 #define FLASH_SR_SOP 0x00000002U
<> 144:ef7eb2e8f9f7 3372 #define FLASH_SR_WRPERR 0x00000010U
<> 144:ef7eb2e8f9f7 3373 #define FLASH_SR_PGAERR 0x00000020U
<> 144:ef7eb2e8f9f7 3374 #define FLASH_SR_PGPERR 0x00000040U
<> 144:ef7eb2e8f9f7 3375 #define FLASH_SR_PGSERR 0x00000080U
<> 144:ef7eb2e8f9f7 3376 #define FLASH_SR_BSY 0x00010000U
<> 144:ef7eb2e8f9f7 3377
<> 144:ef7eb2e8f9f7 3378 /******************* Bits definition for FLASH_CR register ******************/
<> 144:ef7eb2e8f9f7 3379 #define FLASH_CR_PG 0x00000001U
<> 144:ef7eb2e8f9f7 3380 #define FLASH_CR_SER 0x00000002U
<> 144:ef7eb2e8f9f7 3381 #define FLASH_CR_MER 0x00000004U
<> 144:ef7eb2e8f9f7 3382 #define FLASH_CR_SNB 0x000000F8U
<> 144:ef7eb2e8f9f7 3383 #define FLASH_CR_SNB_0 0x00000008U
<> 144:ef7eb2e8f9f7 3384 #define FLASH_CR_SNB_1 0x00000010U
<> 144:ef7eb2e8f9f7 3385 #define FLASH_CR_SNB_2 0x00000020U
<> 144:ef7eb2e8f9f7 3386 #define FLASH_CR_SNB_3 0x00000040U
<> 144:ef7eb2e8f9f7 3387 #define FLASH_CR_SNB_4 0x00000080U
<> 144:ef7eb2e8f9f7 3388 #define FLASH_CR_PSIZE 0x00000300U
<> 144:ef7eb2e8f9f7 3389 #define FLASH_CR_PSIZE_0 0x00000100U
<> 144:ef7eb2e8f9f7 3390 #define FLASH_CR_PSIZE_1 0x00000200U
<> 144:ef7eb2e8f9f7 3391 #define FLASH_CR_STRT 0x00010000U
<> 144:ef7eb2e8f9f7 3392 #define FLASH_CR_EOPIE 0x01000000U
<> 144:ef7eb2e8f9f7 3393 #define FLASH_CR_LOCK 0x80000000U
<> 144:ef7eb2e8f9f7 3394
<> 144:ef7eb2e8f9f7 3395 /******************* Bits definition for FLASH_OPTCR register ***************/
<> 144:ef7eb2e8f9f7 3396 #define FLASH_OPTCR_OPTLOCK 0x00000001U
<> 144:ef7eb2e8f9f7 3397 #define FLASH_OPTCR_OPTSTRT 0x00000002U
<> 144:ef7eb2e8f9f7 3398 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
<> 144:ef7eb2e8f9f7 3399 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
<> 144:ef7eb2e8f9f7 3400 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
<> 144:ef7eb2e8f9f7 3401
<> 144:ef7eb2e8f9f7 3402 #define FLASH_OPTCR_WDG_SW 0x00000020U
<> 144:ef7eb2e8f9f7 3403 #define FLASH_OPTCR_nRST_STOP 0x00000040U
<> 144:ef7eb2e8f9f7 3404 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
<> 144:ef7eb2e8f9f7 3405 #define FLASH_OPTCR_RDP 0x0000FF00U
<> 144:ef7eb2e8f9f7 3406 #define FLASH_OPTCR_RDP_0 0x00000100U
<> 144:ef7eb2e8f9f7 3407 #define FLASH_OPTCR_RDP_1 0x00000200U
<> 144:ef7eb2e8f9f7 3408 #define FLASH_OPTCR_RDP_2 0x00000400U
<> 144:ef7eb2e8f9f7 3409 #define FLASH_OPTCR_RDP_3 0x00000800U
<> 144:ef7eb2e8f9f7 3410 #define FLASH_OPTCR_RDP_4 0x00001000U
<> 144:ef7eb2e8f9f7 3411 #define FLASH_OPTCR_RDP_5 0x00002000U
<> 144:ef7eb2e8f9f7 3412 #define FLASH_OPTCR_RDP_6 0x00004000U
<> 144:ef7eb2e8f9f7 3413 #define FLASH_OPTCR_RDP_7 0x00008000U
<> 144:ef7eb2e8f9f7 3414 #define FLASH_OPTCR_nWRP 0x0FFF0000U
<> 144:ef7eb2e8f9f7 3415 #define FLASH_OPTCR_nWRP_0 0x00010000U
<> 144:ef7eb2e8f9f7 3416 #define FLASH_OPTCR_nWRP_1 0x00020000U
<> 144:ef7eb2e8f9f7 3417 #define FLASH_OPTCR_nWRP_2 0x00040000U
<> 144:ef7eb2e8f9f7 3418 #define FLASH_OPTCR_nWRP_3 0x00080000U
<> 144:ef7eb2e8f9f7 3419 #define FLASH_OPTCR_nWRP_4 0x00100000U
<> 144:ef7eb2e8f9f7 3420 #define FLASH_OPTCR_nWRP_5 0x00200000U
<> 144:ef7eb2e8f9f7 3421 #define FLASH_OPTCR_nWRP_6 0x00400000U
<> 144:ef7eb2e8f9f7 3422 #define FLASH_OPTCR_nWRP_7 0x00800000U
<> 144:ef7eb2e8f9f7 3423 #define FLASH_OPTCR_nWRP_8 0x01000000U
<> 144:ef7eb2e8f9f7 3424 #define FLASH_OPTCR_nWRP_9 0x02000000U
<> 144:ef7eb2e8f9f7 3425 #define FLASH_OPTCR_nWRP_10 0x04000000U
<> 144:ef7eb2e8f9f7 3426 #define FLASH_OPTCR_nWRP_11 0x08000000U
<> 144:ef7eb2e8f9f7 3427
<> 144:ef7eb2e8f9f7 3428 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3429 /* */
<> 144:ef7eb2e8f9f7 3430 /* Flexible Static Memory Controller */
<> 144:ef7eb2e8f9f7 3431 /* */
<> 144:ef7eb2e8f9f7 3432 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3433 /****************** Bit definition for FSMC_BCR1 register *******************/
<> 144:ef7eb2e8f9f7 3434 #define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 3435 #define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 3436
<> 144:ef7eb2e8f9f7 3437 #define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 3438 #define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3439 #define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3440
<> 144:ef7eb2e8f9f7 3441 #define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 3442 #define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3443 #define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3444
<> 144:ef7eb2e8f9f7 3445 #define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 3446 #define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 3447 #define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 3448 #define FSMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 3449 #define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 3450 #define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 3451 #define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 3452 #define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 3453 #define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 3454 #define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 3455
<> 144:ef7eb2e8f9f7 3456 /****************** Bit definition for FSMC_BCR2 register *******************/
<> 144:ef7eb2e8f9f7 3457 #define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 3458 #define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 3459
<> 144:ef7eb2e8f9f7 3460 #define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 3461 #define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3462 #define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3463
<> 144:ef7eb2e8f9f7 3464 #define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 3465 #define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3466 #define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3467
<> 144:ef7eb2e8f9f7 3468 #define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 3469 #define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 3470 #define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 3471 #define FSMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 3472 #define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 3473 #define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 3474 #define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 3475 #define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 3476 #define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 3477 #define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 3478
<> 144:ef7eb2e8f9f7 3479 /****************** Bit definition for FSMC_BCR3 register *******************/
<> 144:ef7eb2e8f9f7 3480 #define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 3481 #define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 3482
<> 144:ef7eb2e8f9f7 3483 #define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 3484 #define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3485 #define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3486
<> 144:ef7eb2e8f9f7 3487 #define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 3488 #define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3489 #define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3490
<> 144:ef7eb2e8f9f7 3491 #define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 3492 #define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 3493 #define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 3494 #define FSMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 3495 #define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 3496 #define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 3497 #define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 3498 #define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 3499 #define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 3500 #define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 3501
<> 144:ef7eb2e8f9f7 3502 /****************** Bit definition for FSMC_BCR4 register *******************/
<> 144:ef7eb2e8f9f7 3503 #define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 3504 #define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 3505
<> 144:ef7eb2e8f9f7 3506 #define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 3507 #define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3508 #define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3509
<> 144:ef7eb2e8f9f7 3510 #define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 3511 #define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3512 #define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3513
<> 144:ef7eb2e8f9f7 3514 #define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 3515 #define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 3516 #define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 3517 #define FSMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 3518 #define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 3519 #define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 3520 #define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 3521 #define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 3522 #define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 3523 #define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 3524
<> 144:ef7eb2e8f9f7 3525 /****************** Bit definition for FSMC_BTR1 register ******************/
<> 144:ef7eb2e8f9f7 3526 #define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3527 #define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3528 #define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3529 #define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3530 #define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3531
<> 144:ef7eb2e8f9f7 3532 #define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3533 #define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3534 #define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3535 #define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3536 #define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3537
<> 144:ef7eb2e8f9f7 3538 #define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3539 #define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3540 #define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3541 #define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3542 #define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3543 #define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3544 #define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3545 #define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3546 #define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3547
<> 144:ef7eb2e8f9f7 3548 #define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 3549 #define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3550 #define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3551 #define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3552 #define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3553
<> 144:ef7eb2e8f9f7 3554 #define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 3555 #define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3556 #define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3557 #define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3558 #define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3559
<> 144:ef7eb2e8f9f7 3560 #define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 3561 #define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3562 #define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3563 #define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3564 #define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3565
<> 144:ef7eb2e8f9f7 3566 #define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3567 #define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3568 #define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3569
<> 144:ef7eb2e8f9f7 3570 /****************** Bit definition for FSMC_BTR2 register *******************/
<> 144:ef7eb2e8f9f7 3571 #define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3572 #define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3573 #define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3574 #define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3575 #define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3576
<> 144:ef7eb2e8f9f7 3577 #define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3578 #define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3579 #define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3580 #define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3581 #define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3582
<> 144:ef7eb2e8f9f7 3583 #define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3584 #define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3585 #define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3586 #define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3587 #define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3588 #define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3589 #define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3590 #define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3591 #define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3592
<> 144:ef7eb2e8f9f7 3593 #define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 3594 #define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3595 #define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3596 #define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3597 #define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3598
<> 144:ef7eb2e8f9f7 3599 #define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 3600 #define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3601 #define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3602 #define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3603 #define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3604
<> 144:ef7eb2e8f9f7 3605 #define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 3606 #define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3607 #define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3608 #define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3609 #define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3610
<> 144:ef7eb2e8f9f7 3611 #define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3612 #define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3613 #define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3614
<> 144:ef7eb2e8f9f7 3615 /******************* Bit definition for FSMC_BTR3 register *******************/
<> 144:ef7eb2e8f9f7 3616 #define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3617 #define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3618 #define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3619 #define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3620 #define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3621
<> 144:ef7eb2e8f9f7 3622 #define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3623 #define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3624 #define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3625 #define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3626 #define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3627
<> 144:ef7eb2e8f9f7 3628 #define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3629 #define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3630 #define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3631 #define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3632 #define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3633 #define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3634 #define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3635 #define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3636 #define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3637
<> 144:ef7eb2e8f9f7 3638 #define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 3639 #define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3640 #define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3641 #define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3642 #define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3643
<> 144:ef7eb2e8f9f7 3644 #define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 3645 #define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3646 #define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3647 #define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3648 #define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3649
<> 144:ef7eb2e8f9f7 3650 #define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 3651 #define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3652 #define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3653 #define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3654 #define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3655
<> 144:ef7eb2e8f9f7 3656 #define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3657 #define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3658 #define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3659
<> 144:ef7eb2e8f9f7 3660 /****************** Bit definition for FSMC_BTR4 register *******************/
<> 144:ef7eb2e8f9f7 3661 #define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3662 #define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3663 #define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3664 #define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3665 #define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3666
<> 144:ef7eb2e8f9f7 3667 #define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3668 #define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3669 #define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3670 #define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3671 #define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3672
<> 144:ef7eb2e8f9f7 3673 #define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3674 #define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3675 #define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3676 #define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3677 #define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3678 #define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3679 #define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3680 #define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3681 #define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3682
<> 144:ef7eb2e8f9f7 3683 #define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 3684 #define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3685 #define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3686 #define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3687 #define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3688
<> 144:ef7eb2e8f9f7 3689 #define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 3690 #define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3691 #define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3692 #define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3693 #define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3694
<> 144:ef7eb2e8f9f7 3695 #define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 3696 #define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3697 #define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3698 #define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3699 #define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3700
<> 144:ef7eb2e8f9f7 3701 #define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3702 #define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3703 #define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3704
<> 144:ef7eb2e8f9f7 3705 /****************** Bit definition for FSMC_BWTR1 register ******************/
<> 144:ef7eb2e8f9f7 3706 #define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3707 #define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3708 #define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3709 #define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3710 #define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3711
<> 144:ef7eb2e8f9f7 3712 #define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3713 #define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3714 #define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3715 #define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3716 #define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3717
<> 144:ef7eb2e8f9f7 3718 #define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3719 #define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3720 #define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3721 #define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3722 #define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3723 #define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3724 #define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3725 #define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3726 #define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3727
<> 144:ef7eb2e8f9f7 3728 #define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
<> 144:ef7eb2e8f9f7 3729 #define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3730 #define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3731 #define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3732 #define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3733
<> 144:ef7eb2e8f9f7 3734 #define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3735 #define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3736 #define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3737
<> 144:ef7eb2e8f9f7 3738 /****************** Bit definition for FSMC_BWTR2 register ******************/
<> 144:ef7eb2e8f9f7 3739 #define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3740 #define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3741 #define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3742 #define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3743 #define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3744
<> 144:ef7eb2e8f9f7 3745 #define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3746 #define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3747 #define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3748 #define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3749 #define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3750
<> 144:ef7eb2e8f9f7 3751 #define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3752 #define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3753 #define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3754 #define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3755 #define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3756 #define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3757 #define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3758 #define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3759 #define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3760
<> 144:ef7eb2e8f9f7 3761 #define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
<> 144:ef7eb2e8f9f7 3762 #define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3763 #define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3764 #define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3765 #define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3766
<> 144:ef7eb2e8f9f7 3767 #define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3768 #define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3769 #define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3770
<> 144:ef7eb2e8f9f7 3771 /****************** Bit definition for FSMC_BWTR3 register ******************/
<> 144:ef7eb2e8f9f7 3772 #define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3773 #define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3774 #define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3775 #define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3776 #define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3777
<> 144:ef7eb2e8f9f7 3778 #define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3779 #define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3780 #define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3781 #define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3782 #define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3783
<> 144:ef7eb2e8f9f7 3784 #define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3785 #define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3786 #define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3787 #define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3788 #define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3789 #define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3790 #define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3791 #define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3792 #define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3793
<> 144:ef7eb2e8f9f7 3794 #define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
<> 144:ef7eb2e8f9f7 3795 #define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3796 #define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3797 #define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3798 #define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3799
<> 144:ef7eb2e8f9f7 3800 #define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3801 #define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3802 #define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3803
<> 144:ef7eb2e8f9f7 3804 /****************** Bit definition for FSMC_BWTR4 register ******************/
<> 144:ef7eb2e8f9f7 3805 #define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 3806 #define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3807 #define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3808 #define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3809 #define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3810
<> 144:ef7eb2e8f9f7 3811 #define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 3812 #define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3813 #define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3814 #define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3815 #define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3816
<> 144:ef7eb2e8f9f7 3817 #define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 3818 #define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3819 #define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3820 #define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3821 #define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3822 #define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3823 #define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3824 #define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3825 #define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3826
<> 144:ef7eb2e8f9f7 3827 #define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
<> 144:ef7eb2e8f9f7 3828 #define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3829 #define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3830 #define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3831 #define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3832
<> 144:ef7eb2e8f9f7 3833 #define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 3834 #define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3835 #define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3836
<> 144:ef7eb2e8f9f7 3837 /****************** Bit definition for FSMC_PCR2 register *******************/
<> 144:ef7eb2e8f9f7 3838 #define FSMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
<> 144:ef7eb2e8f9f7 3839 #define FSMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
<> 144:ef7eb2e8f9f7 3840 #define FSMC_PCR2_PTYP 0x00000008U /*!<Memory type */
<> 144:ef7eb2e8f9f7 3841
<> 144:ef7eb2e8f9f7 3842 #define FSMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 144:ef7eb2e8f9f7 3843 #define FSMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3844 #define FSMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3845
<> 144:ef7eb2e8f9f7 3846 #define FSMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
<> 144:ef7eb2e8f9f7 3847
<> 144:ef7eb2e8f9f7 3848 #define FSMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 144:ef7eb2e8f9f7 3849 #define FSMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3850 #define FSMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3851 #define FSMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3852 #define FSMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3853
<> 144:ef7eb2e8f9f7 3854 #define FSMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
<> 144:ef7eb2e8f9f7 3855 #define FSMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3856 #define FSMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3857 #define FSMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3858 #define FSMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3859
<> 144:ef7eb2e8f9f7 3860 #define FSMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
<> 144:ef7eb2e8f9f7 3861 #define FSMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3862 #define FSMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3863 #define FSMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3864
<> 144:ef7eb2e8f9f7 3865 /****************** Bit definition for FSMC_PCR3 register *******************/
<> 144:ef7eb2e8f9f7 3866 #define FSMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
<> 144:ef7eb2e8f9f7 3867 #define FSMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
<> 144:ef7eb2e8f9f7 3868 #define FSMC_PCR3_PTYP 0x00000008U /*!<Memory type */
<> 144:ef7eb2e8f9f7 3869
<> 144:ef7eb2e8f9f7 3870 #define FSMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 144:ef7eb2e8f9f7 3871 #define FSMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3872 #define FSMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3873
<> 144:ef7eb2e8f9f7 3874 #define FSMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
<> 144:ef7eb2e8f9f7 3875
<> 144:ef7eb2e8f9f7 3876 #define FSMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 144:ef7eb2e8f9f7 3877 #define FSMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3878 #define FSMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3879 #define FSMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3880 #define FSMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3881
<> 144:ef7eb2e8f9f7 3882 #define FSMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
<> 144:ef7eb2e8f9f7 3883 #define FSMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3884 #define FSMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3885 #define FSMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3886 #define FSMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3887
<> 144:ef7eb2e8f9f7 3888 #define FSMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
<> 144:ef7eb2e8f9f7 3889 #define FSMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3890 #define FSMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3891 #define FSMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3892
<> 144:ef7eb2e8f9f7 3893 /****************** Bit definition for FSMC_PCR4 register *******************/
<> 144:ef7eb2e8f9f7 3894 #define FSMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
<> 144:ef7eb2e8f9f7 3895 #define FSMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
<> 144:ef7eb2e8f9f7 3896 #define FSMC_PCR4_PTYP 0x00000008U /*!<Memory type */
<> 144:ef7eb2e8f9f7 3897
<> 144:ef7eb2e8f9f7 3898 #define FSMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 144:ef7eb2e8f9f7 3899 #define FSMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3900 #define FSMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3901
<> 144:ef7eb2e8f9f7 3902 #define FSMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
<> 144:ef7eb2e8f9f7 3903
<> 144:ef7eb2e8f9f7 3904 #define FSMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 144:ef7eb2e8f9f7 3905 #define FSMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3906 #define FSMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3907 #define FSMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3908 #define FSMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3909
<> 144:ef7eb2e8f9f7 3910 #define FSMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
<> 144:ef7eb2e8f9f7 3911 #define FSMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3912 #define FSMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3913 #define FSMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3914 #define FSMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3915
<> 144:ef7eb2e8f9f7 3916 #define FSMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
<> 144:ef7eb2e8f9f7 3917 #define FSMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3918 #define FSMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3919 #define FSMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3920
<> 144:ef7eb2e8f9f7 3921 /******************* Bit definition for FSMC_SR2 register *******************/
<> 144:ef7eb2e8f9f7 3922 #define FSMC_SR2_IRS 0x00000001U /*!<Interrupt Rising Edge status */
<> 144:ef7eb2e8f9f7 3923 #define FSMC_SR2_ILS 0x00000002U /*!<Interrupt Level status */
<> 144:ef7eb2e8f9f7 3924 #define FSMC_SR2_IFS 0x00000004U /*!<Interrupt Falling Edge status */
<> 144:ef7eb2e8f9f7 3925 #define FSMC_SR2_IREN 0x00000008U /*!<Interrupt Rising Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 3926 #define FSMC_SR2_ILEN 0x00000010U /*!<Interrupt Level detection Enable bit */
<> 144:ef7eb2e8f9f7 3927 #define FSMC_SR2_IFEN 0x00000020U /*!<Interrupt Falling Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 3928 #define FSMC_SR2_FEMPT 0x00000040U /*!<FIFO empty */
<> 144:ef7eb2e8f9f7 3929
<> 144:ef7eb2e8f9f7 3930 /******************* Bit definition for FSMC_SR3 register *******************/
<> 144:ef7eb2e8f9f7 3931 #define FSMC_SR3_IRS 0x00000001U /*!<Interrupt Rising Edge status */
<> 144:ef7eb2e8f9f7 3932 #define FSMC_SR3_ILS 0x00000002U /*!<Interrupt Level status */
<> 144:ef7eb2e8f9f7 3933 #define FSMC_SR3_IFS 0x00000004U /*!<Interrupt Falling Edge status */
<> 144:ef7eb2e8f9f7 3934 #define FSMC_SR3_IREN 0x00000008U /*!<Interrupt Rising Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 3935 #define FSMC_SR3_ILEN 0x00000010U /*!<Interrupt Level detection Enable bit */
<> 144:ef7eb2e8f9f7 3936 #define FSMC_SR3_IFEN 0x00000020U /*!<Interrupt Falling Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 3937 #define FSMC_SR3_FEMPT 0x00000040U /*!<FIFO empty */
<> 144:ef7eb2e8f9f7 3938
<> 144:ef7eb2e8f9f7 3939 /******************* Bit definition for FSMC_SR4 register *******************/
<> 144:ef7eb2e8f9f7 3940 #define FSMC_SR4_IRS 0x00000001U /*!<Interrupt Rising Edge status */
<> 144:ef7eb2e8f9f7 3941 #define FSMC_SR4_ILS 0x00000002U /*!<Interrupt Level status */
<> 144:ef7eb2e8f9f7 3942 #define FSMC_SR4_IFS 0x00000004U /*!<Interrupt Falling Edge status */
<> 144:ef7eb2e8f9f7 3943 #define FSMC_SR4_IREN 0x00000008U /*!<Interrupt Rising Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 3944 #define FSMC_SR4_ILEN 0x00000010U /*!<Interrupt Level detection Enable bit */
<> 144:ef7eb2e8f9f7 3945 #define FSMC_SR4_IFEN 0x00000020U /*!<Interrupt Falling Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 3946 #define FSMC_SR4_FEMPT 0x00000040U /*!<FIFO empty */
<> 144:ef7eb2e8f9f7 3947
<> 144:ef7eb2e8f9f7 3948 /****************** Bit definition for FSMC_PMEM2 register ******************/
<> 144:ef7eb2e8f9f7 3949 #define FSMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
<> 144:ef7eb2e8f9f7 3950 #define FSMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3951 #define FSMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3952 #define FSMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3953 #define FSMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3954 #define FSMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3955 #define FSMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3956 #define FSMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3957 #define FSMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3958
<> 144:ef7eb2e8f9f7 3959 #define FSMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
<> 144:ef7eb2e8f9f7 3960 #define FSMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3961 #define FSMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3962 #define FSMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3963 #define FSMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3964 #define FSMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3965 #define FSMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3966 #define FSMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3967 #define FSMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3968
<> 144:ef7eb2e8f9f7 3969 #define FSMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
<> 144:ef7eb2e8f9f7 3970 #define FSMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3971 #define FSMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3972 #define FSMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3973 #define FSMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3974 #define FSMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3975 #define FSMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3976 #define FSMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3977 #define FSMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3978
<> 144:ef7eb2e8f9f7 3979 #define FSMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
<> 144:ef7eb2e8f9f7 3980 #define FSMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3981 #define FSMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3982 #define FSMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3983 #define FSMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3984 #define FSMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3985 #define FSMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3986 #define FSMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3987 #define FSMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3988
<> 144:ef7eb2e8f9f7 3989 /****************** Bit definition for FSMC_PMEM3 register ******************/
<> 144:ef7eb2e8f9f7 3990 #define FSMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
<> 144:ef7eb2e8f9f7 3991 #define FSMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3992 #define FSMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3993 #define FSMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3994 #define FSMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3995 #define FSMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 3996 #define FSMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 3997 #define FSMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 3998 #define FSMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 3999
<> 144:ef7eb2e8f9f7 4000 #define FSMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
<> 144:ef7eb2e8f9f7 4001 #define FSMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4002 #define FSMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4003 #define FSMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4004 #define FSMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4005 #define FSMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4006 #define FSMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4007 #define FSMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4008 #define FSMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4009
<> 144:ef7eb2e8f9f7 4010 #define FSMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
<> 144:ef7eb2e8f9f7 4011 #define FSMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4012 #define FSMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4013 #define FSMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4014 #define FSMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4015 #define FSMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4016 #define FSMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4017 #define FSMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4018 #define FSMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4019
<> 144:ef7eb2e8f9f7 4020 #define FSMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4021 #define FSMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4022 #define FSMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4023 #define FSMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4024 #define FSMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4025 #define FSMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4026 #define FSMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4027 #define FSMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4028 #define FSMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4029
<> 144:ef7eb2e8f9f7 4030 /****************** Bit definition for FSMC_PMEM4 register ******************/
<> 144:ef7eb2e8f9f7 4031 #define FSMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
<> 144:ef7eb2e8f9f7 4032 #define FSMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4033 #define FSMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4034 #define FSMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4035 #define FSMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4036 #define FSMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4037 #define FSMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4038 #define FSMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4039 #define FSMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4040
<> 144:ef7eb2e8f9f7 4041 #define FSMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
<> 144:ef7eb2e8f9f7 4042 #define FSMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4043 #define FSMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4044 #define FSMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4045 #define FSMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4046 #define FSMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4047 #define FSMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4048 #define FSMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4049 #define FSMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4050
<> 144:ef7eb2e8f9f7 4051 #define FSMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
<> 144:ef7eb2e8f9f7 4052 #define FSMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4053 #define FSMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4054 #define FSMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4055 #define FSMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4056 #define FSMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4057 #define FSMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4058 #define FSMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4059 #define FSMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4060
<> 144:ef7eb2e8f9f7 4061 #define FSMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4062 #define FSMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4063 #define FSMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4064 #define FSMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4065 #define FSMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4066 #define FSMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4067 #define FSMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4068 #define FSMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4069 #define FSMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4070
<> 144:ef7eb2e8f9f7 4071 /****************** Bit definition for FSMC_PATT2 register ******************/
<> 144:ef7eb2e8f9f7 4072 #define FSMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
<> 144:ef7eb2e8f9f7 4073 #define FSMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4074 #define FSMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4075 #define FSMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4076 #define FSMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4077 #define FSMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4078 #define FSMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4079 #define FSMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4080 #define FSMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4081
<> 144:ef7eb2e8f9f7 4082 #define FSMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
<> 144:ef7eb2e8f9f7 4083 #define FSMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4084 #define FSMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4085 #define FSMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4086 #define FSMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4087 #define FSMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4088 #define FSMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4089 #define FSMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4090 #define FSMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4091
<> 144:ef7eb2e8f9f7 4092 #define FSMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
<> 144:ef7eb2e8f9f7 4093 #define FSMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4094 #define FSMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4095 #define FSMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4096 #define FSMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4097 #define FSMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4098 #define FSMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4099 #define FSMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4100 #define FSMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4101
<> 144:ef7eb2e8f9f7 4102 #define FSMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4103 #define FSMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4104 #define FSMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4105 #define FSMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4106 #define FSMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4107 #define FSMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4108 #define FSMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4109 #define FSMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4110 #define FSMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4111
<> 144:ef7eb2e8f9f7 4112 /****************** Bit definition for FSMC_PATT3 register ******************/
<> 144:ef7eb2e8f9f7 4113 #define FSMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
<> 144:ef7eb2e8f9f7 4114 #define FSMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4115 #define FSMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4116 #define FSMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4117 #define FSMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4118 #define FSMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4119 #define FSMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4120 #define FSMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4121 #define FSMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4122
<> 144:ef7eb2e8f9f7 4123 #define FSMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
<> 144:ef7eb2e8f9f7 4124 #define FSMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4125 #define FSMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4126 #define FSMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4127 #define FSMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4128 #define FSMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4129 #define FSMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4130 #define FSMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4131 #define FSMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4132
<> 144:ef7eb2e8f9f7 4133 #define FSMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
<> 144:ef7eb2e8f9f7 4134 #define FSMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4135 #define FSMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4136 #define FSMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4137 #define FSMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4138 #define FSMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4139 #define FSMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4140 #define FSMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4141 #define FSMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4142
<> 144:ef7eb2e8f9f7 4143 #define FSMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4144 #define FSMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4145 #define FSMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4146 #define FSMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4147 #define FSMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4148 #define FSMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4149 #define FSMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4150 #define FSMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4151 #define FSMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4152
<> 144:ef7eb2e8f9f7 4153 /****************** Bit definition for FSMC_PATT4 register ******************/
<> 144:ef7eb2e8f9f7 4154 #define FSMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
<> 144:ef7eb2e8f9f7 4155 #define FSMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4156 #define FSMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4157 #define FSMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4158 #define FSMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4159 #define FSMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4160 #define FSMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4161 #define FSMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4162 #define FSMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4163
<> 144:ef7eb2e8f9f7 4164 #define FSMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
<> 144:ef7eb2e8f9f7 4165 #define FSMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4166 #define FSMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4167 #define FSMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4168 #define FSMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4169 #define FSMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4170 #define FSMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4171 #define FSMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4172 #define FSMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4173
<> 144:ef7eb2e8f9f7 4174 #define FSMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
<> 144:ef7eb2e8f9f7 4175 #define FSMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4176 #define FSMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4177 #define FSMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4178 #define FSMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4179 #define FSMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4180 #define FSMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4181 #define FSMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4182 #define FSMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4183
<> 144:ef7eb2e8f9f7 4184 #define FSMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4185 #define FSMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4186 #define FSMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4187 #define FSMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4188 #define FSMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4189 #define FSMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4190 #define FSMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4191 #define FSMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4192 #define FSMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4193
<> 144:ef7eb2e8f9f7 4194 /****************** Bit definition for FSMC_PIO4 register *******************/
<> 144:ef7eb2e8f9f7 4195 #define FSMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
<> 144:ef7eb2e8f9f7 4196 #define FSMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4197 #define FSMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4198 #define FSMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4199 #define FSMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4200 #define FSMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4201 #define FSMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4202 #define FSMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4203 #define FSMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4204
<> 144:ef7eb2e8f9f7 4205 #define FSMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
<> 144:ef7eb2e8f9f7 4206 #define FSMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4207 #define FSMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4208 #define FSMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4209 #define FSMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4210 #define FSMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4211 #define FSMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4212 #define FSMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4213 #define FSMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4214
<> 144:ef7eb2e8f9f7 4215 #define FSMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
<> 144:ef7eb2e8f9f7 4216 #define FSMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4217 #define FSMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4218 #define FSMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4219 #define FSMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4220 #define FSMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4221 #define FSMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4222 #define FSMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4223 #define FSMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4224
<> 144:ef7eb2e8f9f7 4225 #define FSMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4226 #define FSMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4227 #define FSMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4228 #define FSMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4229 #define FSMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4230 #define FSMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4231 #define FSMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4232 #define FSMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4233 #define FSMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4234
<> 144:ef7eb2e8f9f7 4235 /****************** Bit definition for FSMC_ECCR2 register ******************/
<> 144:ef7eb2e8f9f7 4236 #define FSMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
<> 144:ef7eb2e8f9f7 4237
<> 144:ef7eb2e8f9f7 4238 /****************** Bit definition for FSMC_ECCR3 register ******************/
<> 144:ef7eb2e8f9f7 4239 #define FSMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
<> 144:ef7eb2e8f9f7 4240
<> 144:ef7eb2e8f9f7 4241 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4242 /* */
<> 144:ef7eb2e8f9f7 4243 /* General Purpose I/O */
<> 144:ef7eb2e8f9f7 4244 /* */
<> 144:ef7eb2e8f9f7 4245 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4246 /****************** Bits definition for GPIO_MODER register *****************/
<> 144:ef7eb2e8f9f7 4247 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 4248 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4249 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4250 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
<> 144:ef7eb2e8f9f7 4251 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4252 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4253 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 4254 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4255 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4256 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
<> 144:ef7eb2e8f9f7 4257 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4258 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4259 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
<> 144:ef7eb2e8f9f7 4260 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4261 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4262 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
<> 144:ef7eb2e8f9f7 4263 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4264 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4265 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
<> 144:ef7eb2e8f9f7 4266 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4267 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4268 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
<> 144:ef7eb2e8f9f7 4269 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4270 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4271 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
<> 144:ef7eb2e8f9f7 4272 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 4273 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 4274 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
<> 144:ef7eb2e8f9f7 4275 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 4276 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 4277 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 4278 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 4279 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 4280 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
<> 144:ef7eb2e8f9f7 4281 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 4282 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 4283 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
<> 144:ef7eb2e8f9f7 4284 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 4285 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 4286 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
<> 144:ef7eb2e8f9f7 4287 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 4288 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 4289 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 4290 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 4291 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 4292 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
<> 144:ef7eb2e8f9f7 4293 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 4294 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 4295 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4296 #define GPIO_MODER_MODER0 0x00000003U
<> 144:ef7eb2e8f9f7 4297 #define GPIO_MODER_MODER0_0 0x00000001U
<> 144:ef7eb2e8f9f7 4298 #define GPIO_MODER_MODER0_1 0x00000002U
<> 144:ef7eb2e8f9f7 4299 #define GPIO_MODER_MODER1 0x0000000CU
<> 144:ef7eb2e8f9f7 4300 #define GPIO_MODER_MODER1_0 0x00000004U
<> 144:ef7eb2e8f9f7 4301 #define GPIO_MODER_MODER1_1 0x00000008U
<> 144:ef7eb2e8f9f7 4302 #define GPIO_MODER_MODER2 0x00000030U
<> 144:ef7eb2e8f9f7 4303 #define GPIO_MODER_MODER2_0 0x00000010U
<> 144:ef7eb2e8f9f7 4304 #define GPIO_MODER_MODER2_1 0x00000020U
<> 144:ef7eb2e8f9f7 4305 #define GPIO_MODER_MODER3 0x000000C0U
<> 144:ef7eb2e8f9f7 4306 #define GPIO_MODER_MODER3_0 0x00000040U
<> 144:ef7eb2e8f9f7 4307 #define GPIO_MODER_MODER3_1 0x00000080U
<> 144:ef7eb2e8f9f7 4308 #define GPIO_MODER_MODER4 0x00000300U
<> 144:ef7eb2e8f9f7 4309 #define GPIO_MODER_MODER4_0 0x00000100U
<> 144:ef7eb2e8f9f7 4310 #define GPIO_MODER_MODER4_1 0x00000200U
<> 144:ef7eb2e8f9f7 4311 #define GPIO_MODER_MODER5 0x00000C00U
<> 144:ef7eb2e8f9f7 4312 #define GPIO_MODER_MODER5_0 0x00000400U
<> 144:ef7eb2e8f9f7 4313 #define GPIO_MODER_MODER5_1 0x00000800U
<> 144:ef7eb2e8f9f7 4314 #define GPIO_MODER_MODER6 0x00003000U
<> 144:ef7eb2e8f9f7 4315 #define GPIO_MODER_MODER6_0 0x00001000U
<> 144:ef7eb2e8f9f7 4316 #define GPIO_MODER_MODER6_1 0x00002000U
<> 144:ef7eb2e8f9f7 4317 #define GPIO_MODER_MODER7 0x0000C000U
<> 144:ef7eb2e8f9f7 4318 #define GPIO_MODER_MODER7_0 0x00004000U
<> 144:ef7eb2e8f9f7 4319 #define GPIO_MODER_MODER7_1 0x00008000U
<> 144:ef7eb2e8f9f7 4320 #define GPIO_MODER_MODER8 0x00030000U
<> 144:ef7eb2e8f9f7 4321 #define GPIO_MODER_MODER8_0 0x00010000U
<> 144:ef7eb2e8f9f7 4322 #define GPIO_MODER_MODER8_1 0x00020000U
<> 144:ef7eb2e8f9f7 4323 #define GPIO_MODER_MODER9 0x000C0000U
<> 144:ef7eb2e8f9f7 4324 #define GPIO_MODER_MODER9_0 0x00040000U
<> 144:ef7eb2e8f9f7 4325 #define GPIO_MODER_MODER9_1 0x00080000U
<> 144:ef7eb2e8f9f7 4326 #define GPIO_MODER_MODER10 0x00300000U
<> 144:ef7eb2e8f9f7 4327 #define GPIO_MODER_MODER10_0 0x00100000U
<> 144:ef7eb2e8f9f7 4328 #define GPIO_MODER_MODER10_1 0x00200000U
<> 144:ef7eb2e8f9f7 4329 #define GPIO_MODER_MODER11 0x00C00000U
<> 144:ef7eb2e8f9f7 4330 #define GPIO_MODER_MODER11_0 0x00400000U
<> 144:ef7eb2e8f9f7 4331 #define GPIO_MODER_MODER11_1 0x00800000U
<> 144:ef7eb2e8f9f7 4332 #define GPIO_MODER_MODER12 0x03000000U
<> 144:ef7eb2e8f9f7 4333 #define GPIO_MODER_MODER12_0 0x01000000U
<> 144:ef7eb2e8f9f7 4334 #define GPIO_MODER_MODER12_1 0x02000000U
<> 144:ef7eb2e8f9f7 4335 #define GPIO_MODER_MODER13 0x0C000000U
<> 144:ef7eb2e8f9f7 4336 #define GPIO_MODER_MODER13_0 0x04000000U
<> 144:ef7eb2e8f9f7 4337 #define GPIO_MODER_MODER13_1 0x08000000U
<> 144:ef7eb2e8f9f7 4338 #define GPIO_MODER_MODER14 0x30000000U
<> 144:ef7eb2e8f9f7 4339 #define GPIO_MODER_MODER14_0 0x10000000U
<> 144:ef7eb2e8f9f7 4340 #define GPIO_MODER_MODER14_1 0x20000000U
<> 144:ef7eb2e8f9f7 4341 #define GPIO_MODER_MODER15 0xC0000000U
<> 144:ef7eb2e8f9f7 4342 #define GPIO_MODER_MODER15_0 0x40000000U
<> 144:ef7eb2e8f9f7 4343 #define GPIO_MODER_MODER15_1 0x80000000U
<> 144:ef7eb2e8f9f7 4344
<> 144:ef7eb2e8f9f7 4345 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 144:ef7eb2e8f9f7 4346 #define GPIO_OTYPER_OT0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4347 #define GPIO_OTYPER_OT1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4348 #define GPIO_OTYPER_OT2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4349 #define GPIO_OTYPER_OT3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4350 #define GPIO_OTYPER_OT4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4351 #define GPIO_OTYPER_OT5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4352 #define GPIO_OTYPER_OT6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4353 #define GPIO_OTYPER_OT7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4354 #define GPIO_OTYPER_OT8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4355 #define GPIO_OTYPER_OT9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4356 #define GPIO_OTYPER_OT10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4357 #define GPIO_OTYPER_OT11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4358 #define GPIO_OTYPER_OT12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4359 #define GPIO_OTYPER_OT13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4360 #define GPIO_OTYPER_OT14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4361 #define GPIO_OTYPER_OT15 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4362
<> 144:ef7eb2e8f9f7 4363 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4364 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
<> 144:ef7eb2e8f9f7 4365 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
<> 144:ef7eb2e8f9f7 4366 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
<> 144:ef7eb2e8f9f7 4367 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
<> 144:ef7eb2e8f9f7 4368 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
<> 144:ef7eb2e8f9f7 4369 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
<> 144:ef7eb2e8f9f7 4370 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
<> 144:ef7eb2e8f9f7 4371 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
<> 144:ef7eb2e8f9f7 4372 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
<> 144:ef7eb2e8f9f7 4373 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
<> 144:ef7eb2e8f9f7 4374 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
<> 144:ef7eb2e8f9f7 4375 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
<> 144:ef7eb2e8f9f7 4376 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
<> 144:ef7eb2e8f9f7 4377 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
<> 144:ef7eb2e8f9f7 4378 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
<> 144:ef7eb2e8f9f7 4379 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
<> 144:ef7eb2e8f9f7 4380
<> 144:ef7eb2e8f9f7 4381 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 144:ef7eb2e8f9f7 4382 #define GPIO_OSPEEDR_OSPEED0 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 4383 #define GPIO_OSPEEDR_OSPEED0_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4384 #define GPIO_OSPEEDR_OSPEED0_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4385 #define GPIO_OSPEEDR_OSPEED1 ((uint32_t)0x0000000CU)
<> 144:ef7eb2e8f9f7 4386 #define GPIO_OSPEEDR_OSPEED1_0 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4387 #define GPIO_OSPEEDR_OSPEED1_1 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4388 #define GPIO_OSPEEDR_OSPEED2 ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 4389 #define GPIO_OSPEEDR_OSPEED2_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4390 #define GPIO_OSPEEDR_OSPEED2_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4391 #define GPIO_OSPEEDR_OSPEED3 ((uint32_t)0x000000C0U)
<> 144:ef7eb2e8f9f7 4392 #define GPIO_OSPEEDR_OSPEED3_0 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4393 #define GPIO_OSPEEDR_OSPEED3_1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4394 #define GPIO_OSPEEDR_OSPEED4 ((uint32_t)0x00000300U)
<> 144:ef7eb2e8f9f7 4395 #define GPIO_OSPEEDR_OSPEED4_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4396 #define GPIO_OSPEEDR_OSPEED4_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4397 #define GPIO_OSPEEDR_OSPEED5 ((uint32_t)0x00000C00U)
<> 144:ef7eb2e8f9f7 4398 #define GPIO_OSPEEDR_OSPEED5_0 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4399 #define GPIO_OSPEEDR_OSPEED5_1 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4400 #define GPIO_OSPEEDR_OSPEED6 ((uint32_t)0x00003000U)
<> 144:ef7eb2e8f9f7 4401 #define GPIO_OSPEEDR_OSPEED6_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4402 #define GPIO_OSPEEDR_OSPEED6_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4403 #define GPIO_OSPEEDR_OSPEED7 ((uint32_t)0x0000C000U)
<> 144:ef7eb2e8f9f7 4404 #define GPIO_OSPEEDR_OSPEED7_0 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4405 #define GPIO_OSPEEDR_OSPEED7_1 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4406 #define GPIO_OSPEEDR_OSPEED8 ((uint32_t)0x00030000U)
<> 144:ef7eb2e8f9f7 4407 #define GPIO_OSPEEDR_OSPEED8_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 4408 #define GPIO_OSPEEDR_OSPEED8_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 4409 #define GPIO_OSPEEDR_OSPEED9 ((uint32_t)0x000C0000U)
<> 144:ef7eb2e8f9f7 4410 #define GPIO_OSPEEDR_OSPEED9_0 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 4411 #define GPIO_OSPEEDR_OSPEED9_1 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 4412 #define GPIO_OSPEEDR_OSPEED10 ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 4413 #define GPIO_OSPEEDR_OSPEED10_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 4414 #define GPIO_OSPEEDR_OSPEED10_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 4415 #define GPIO_OSPEEDR_OSPEED11 ((uint32_t)0x00C00000U)
<> 144:ef7eb2e8f9f7 4416 #define GPIO_OSPEEDR_OSPEED11_0 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 4417 #define GPIO_OSPEEDR_OSPEED11_1 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 4418 #define GPIO_OSPEEDR_OSPEED12 ((uint32_t)0x03000000U)
<> 144:ef7eb2e8f9f7 4419 #define GPIO_OSPEEDR_OSPEED12_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 4420 #define GPIO_OSPEEDR_OSPEED12_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 4421 #define GPIO_OSPEEDR_OSPEED13 ((uint32_t)0x0C000000U)
<> 144:ef7eb2e8f9f7 4422 #define GPIO_OSPEEDR_OSPEED13_0 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 4423 #define GPIO_OSPEEDR_OSPEED13_1 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 4424 #define GPIO_OSPEEDR_OSPEED14 ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 4425 #define GPIO_OSPEEDR_OSPEED14_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 4426 #define GPIO_OSPEEDR_OSPEED14_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 4427 #define GPIO_OSPEEDR_OSPEED15 ((uint32_t)0xC0000000U)
<> 144:ef7eb2e8f9f7 4428 #define GPIO_OSPEEDR_OSPEED15_0 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 4429 #define GPIO_OSPEEDR_OSPEED15_1 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 4430
<> 144:ef7eb2e8f9f7 4431 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4432 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
<> 144:ef7eb2e8f9f7 4433 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
<> 144:ef7eb2e8f9f7 4434 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
<> 144:ef7eb2e8f9f7 4435 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
<> 144:ef7eb2e8f9f7 4436 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
<> 144:ef7eb2e8f9f7 4437 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
<> 144:ef7eb2e8f9f7 4438 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
<> 144:ef7eb2e8f9f7 4439 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
<> 144:ef7eb2e8f9f7 4440 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
<> 144:ef7eb2e8f9f7 4441 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
<> 144:ef7eb2e8f9f7 4442 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
<> 144:ef7eb2e8f9f7 4443 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
<> 144:ef7eb2e8f9f7 4444 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
<> 144:ef7eb2e8f9f7 4445 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
<> 144:ef7eb2e8f9f7 4446 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
<> 144:ef7eb2e8f9f7 4447 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
<> 144:ef7eb2e8f9f7 4448 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
<> 144:ef7eb2e8f9f7 4449 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
<> 144:ef7eb2e8f9f7 4450 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
<> 144:ef7eb2e8f9f7 4451 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
<> 144:ef7eb2e8f9f7 4452 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
<> 144:ef7eb2e8f9f7 4453 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
<> 144:ef7eb2e8f9f7 4454 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
<> 144:ef7eb2e8f9f7 4455 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
<> 144:ef7eb2e8f9f7 4456 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
<> 144:ef7eb2e8f9f7 4457 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
<> 144:ef7eb2e8f9f7 4458 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
<> 144:ef7eb2e8f9f7 4459 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
<> 144:ef7eb2e8f9f7 4460 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
<> 144:ef7eb2e8f9f7 4461 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
<> 144:ef7eb2e8f9f7 4462 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
<> 144:ef7eb2e8f9f7 4463 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
<> 144:ef7eb2e8f9f7 4464 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
<> 144:ef7eb2e8f9f7 4465 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
<> 144:ef7eb2e8f9f7 4466 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
<> 144:ef7eb2e8f9f7 4467 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
<> 144:ef7eb2e8f9f7 4468 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
<> 144:ef7eb2e8f9f7 4469 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
<> 144:ef7eb2e8f9f7 4470 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
<> 144:ef7eb2e8f9f7 4471 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
<> 144:ef7eb2e8f9f7 4472 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
<> 144:ef7eb2e8f9f7 4473 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
<> 144:ef7eb2e8f9f7 4474 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
<> 144:ef7eb2e8f9f7 4475 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
<> 144:ef7eb2e8f9f7 4476 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
<> 144:ef7eb2e8f9f7 4477 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
<> 144:ef7eb2e8f9f7 4478 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
<> 144:ef7eb2e8f9f7 4479 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
<> 144:ef7eb2e8f9f7 4480
<> 144:ef7eb2e8f9f7 4481 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 144:ef7eb2e8f9f7 4482 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 4483 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4484 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4485 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
<> 144:ef7eb2e8f9f7 4486 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4487 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4488 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
<> 144:ef7eb2e8f9f7 4489 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4490 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4491 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
<> 144:ef7eb2e8f9f7 4492 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4493 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4494 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
<> 144:ef7eb2e8f9f7 4495 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4496 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4497 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
<> 144:ef7eb2e8f9f7 4498 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4499 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4500 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
<> 144:ef7eb2e8f9f7 4501 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4502 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4503 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
<> 144:ef7eb2e8f9f7 4504 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4505 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4506 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
<> 144:ef7eb2e8f9f7 4507 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 4508 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 4509 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
<> 144:ef7eb2e8f9f7 4510 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 4511 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 4512 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
<> 144:ef7eb2e8f9f7 4513 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 4514 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 4515 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
<> 144:ef7eb2e8f9f7 4516 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 4517 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 4518 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
<> 144:ef7eb2e8f9f7 4519 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 4520 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 4521 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
<> 144:ef7eb2e8f9f7 4522 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 4523 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 4524 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
<> 144:ef7eb2e8f9f7 4525 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 4526 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 4527 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
<> 144:ef7eb2e8f9f7 4528 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 4529 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 4530
<> 144:ef7eb2e8f9f7 4531 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4532 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
<> 144:ef7eb2e8f9f7 4533 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
<> 144:ef7eb2e8f9f7 4534 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
<> 144:ef7eb2e8f9f7 4535 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
<> 144:ef7eb2e8f9f7 4536 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
<> 144:ef7eb2e8f9f7 4537 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
<> 144:ef7eb2e8f9f7 4538 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
<> 144:ef7eb2e8f9f7 4539 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
<> 144:ef7eb2e8f9f7 4540 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
<> 144:ef7eb2e8f9f7 4541 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
<> 144:ef7eb2e8f9f7 4542 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
<> 144:ef7eb2e8f9f7 4543 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
<> 144:ef7eb2e8f9f7 4544 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
<> 144:ef7eb2e8f9f7 4545 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
<> 144:ef7eb2e8f9f7 4546 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
<> 144:ef7eb2e8f9f7 4547 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
<> 144:ef7eb2e8f9f7 4548 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
<> 144:ef7eb2e8f9f7 4549 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
<> 144:ef7eb2e8f9f7 4550 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
<> 144:ef7eb2e8f9f7 4551 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
<> 144:ef7eb2e8f9f7 4552 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
<> 144:ef7eb2e8f9f7 4553 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
<> 144:ef7eb2e8f9f7 4554 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
<> 144:ef7eb2e8f9f7 4555 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
<> 144:ef7eb2e8f9f7 4556 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
<> 144:ef7eb2e8f9f7 4557 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
<> 144:ef7eb2e8f9f7 4558 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
<> 144:ef7eb2e8f9f7 4559 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
<> 144:ef7eb2e8f9f7 4560 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
<> 144:ef7eb2e8f9f7 4561 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
<> 144:ef7eb2e8f9f7 4562 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
<> 144:ef7eb2e8f9f7 4563 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
<> 144:ef7eb2e8f9f7 4564 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
<> 144:ef7eb2e8f9f7 4565 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
<> 144:ef7eb2e8f9f7 4566 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
<> 144:ef7eb2e8f9f7 4567 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
<> 144:ef7eb2e8f9f7 4568 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
<> 144:ef7eb2e8f9f7 4569 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
<> 144:ef7eb2e8f9f7 4570 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
<> 144:ef7eb2e8f9f7 4571 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
<> 144:ef7eb2e8f9f7 4572 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
<> 144:ef7eb2e8f9f7 4573 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
<> 144:ef7eb2e8f9f7 4574 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
<> 144:ef7eb2e8f9f7 4575 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
<> 144:ef7eb2e8f9f7 4576 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
<> 144:ef7eb2e8f9f7 4577 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
<> 144:ef7eb2e8f9f7 4578 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
<> 144:ef7eb2e8f9f7 4579 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
<> 144:ef7eb2e8f9f7 4580
<> 144:ef7eb2e8f9f7 4581 /****************** Bits definition for GPIO_IDR register *******************/
<> 144:ef7eb2e8f9f7 4582 #define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4583 #define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4584 #define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4585 #define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4586 #define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4587 #define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4588 #define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4589 #define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4590 #define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4591 #define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4592 #define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4593 #define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4594 #define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4595 #define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4596 #define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4597 #define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4598
<> 144:ef7eb2e8f9f7 4599 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4600 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
<> 144:ef7eb2e8f9f7 4601 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
<> 144:ef7eb2e8f9f7 4602 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
<> 144:ef7eb2e8f9f7 4603 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
<> 144:ef7eb2e8f9f7 4604 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
<> 144:ef7eb2e8f9f7 4605 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
<> 144:ef7eb2e8f9f7 4606 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
<> 144:ef7eb2e8f9f7 4607 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
<> 144:ef7eb2e8f9f7 4608 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
<> 144:ef7eb2e8f9f7 4609 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
<> 144:ef7eb2e8f9f7 4610 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
<> 144:ef7eb2e8f9f7 4611 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
<> 144:ef7eb2e8f9f7 4612 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
<> 144:ef7eb2e8f9f7 4613 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
<> 144:ef7eb2e8f9f7 4614 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
<> 144:ef7eb2e8f9f7 4615 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
<> 144:ef7eb2e8f9f7 4616
<> 144:ef7eb2e8f9f7 4617 /****************** Bits definition for GPIO_ODR register *******************/
<> 144:ef7eb2e8f9f7 4618 #define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4619 #define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4620 #define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4621 #define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4622 #define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4623 #define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4624 #define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4625 #define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4626 #define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4627 #define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4628 #define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4629 #define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4630 #define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4631 #define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4632 #define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4633 #define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4634
<> 144:ef7eb2e8f9f7 4635 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4636 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
<> 144:ef7eb2e8f9f7 4637 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
<> 144:ef7eb2e8f9f7 4638 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
<> 144:ef7eb2e8f9f7 4639 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
<> 144:ef7eb2e8f9f7 4640 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
<> 144:ef7eb2e8f9f7 4641 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
<> 144:ef7eb2e8f9f7 4642 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
<> 144:ef7eb2e8f9f7 4643 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
<> 144:ef7eb2e8f9f7 4644 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
<> 144:ef7eb2e8f9f7 4645 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
<> 144:ef7eb2e8f9f7 4646 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
<> 144:ef7eb2e8f9f7 4647 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
<> 144:ef7eb2e8f9f7 4648 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
<> 144:ef7eb2e8f9f7 4649 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
<> 144:ef7eb2e8f9f7 4650 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
<> 144:ef7eb2e8f9f7 4651 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
<> 144:ef7eb2e8f9f7 4652
<> 144:ef7eb2e8f9f7 4653 /****************** Bits definition for GPIO_BSRR register ******************/
<> 144:ef7eb2e8f9f7 4654 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4655 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4656 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4657 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4658 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4659 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4660 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4661 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4662 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4663 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4664 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4665 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4666 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4667 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4668 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4669 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4670 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 4671 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 4672 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 4673 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 4674 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 4675 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 4676 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 4677 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 4678 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 4679 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 4680 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 4681 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 4682 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 4683 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 4684 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 4685 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 4686
<> 144:ef7eb2e8f9f7 4687 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4688 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
<> 144:ef7eb2e8f9f7 4689 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
<> 144:ef7eb2e8f9f7 4690 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
<> 144:ef7eb2e8f9f7 4691 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
<> 144:ef7eb2e8f9f7 4692 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
<> 144:ef7eb2e8f9f7 4693 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
<> 144:ef7eb2e8f9f7 4694 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
<> 144:ef7eb2e8f9f7 4695 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
<> 144:ef7eb2e8f9f7 4696 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
<> 144:ef7eb2e8f9f7 4697 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
<> 144:ef7eb2e8f9f7 4698 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
<> 144:ef7eb2e8f9f7 4699 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
<> 144:ef7eb2e8f9f7 4700 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
<> 144:ef7eb2e8f9f7 4701 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
<> 144:ef7eb2e8f9f7 4702 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
<> 144:ef7eb2e8f9f7 4703 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
<> 144:ef7eb2e8f9f7 4704 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
<> 144:ef7eb2e8f9f7 4705 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
<> 144:ef7eb2e8f9f7 4706 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
<> 144:ef7eb2e8f9f7 4707 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
<> 144:ef7eb2e8f9f7 4708 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
<> 144:ef7eb2e8f9f7 4709 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
<> 144:ef7eb2e8f9f7 4710 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
<> 144:ef7eb2e8f9f7 4711 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
<> 144:ef7eb2e8f9f7 4712 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
<> 144:ef7eb2e8f9f7 4713 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
<> 144:ef7eb2e8f9f7 4714 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
<> 144:ef7eb2e8f9f7 4715 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
<> 144:ef7eb2e8f9f7 4716 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
<> 144:ef7eb2e8f9f7 4717 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
<> 144:ef7eb2e8f9f7 4718 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
<> 144:ef7eb2e8f9f7 4719 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
<> 144:ef7eb2e8f9f7 4720
<> 144:ef7eb2e8f9f7 4721 /****************** Bit definition for GPIO_LCKR register *********************/
<> 144:ef7eb2e8f9f7 4722 #define GPIO_LCKR_LCK0 0x00000001U
<> 144:ef7eb2e8f9f7 4723 #define GPIO_LCKR_LCK1 0x00000002U
<> 144:ef7eb2e8f9f7 4724 #define GPIO_LCKR_LCK2 0x00000004U
<> 144:ef7eb2e8f9f7 4725 #define GPIO_LCKR_LCK3 0x00000008U
<> 144:ef7eb2e8f9f7 4726 #define GPIO_LCKR_LCK4 0x00000010U
<> 144:ef7eb2e8f9f7 4727 #define GPIO_LCKR_LCK5 0x00000020U
<> 144:ef7eb2e8f9f7 4728 #define GPIO_LCKR_LCK6 0x00000040U
<> 144:ef7eb2e8f9f7 4729 #define GPIO_LCKR_LCK7 0x00000080U
<> 144:ef7eb2e8f9f7 4730 #define GPIO_LCKR_LCK8 0x00000100U
<> 144:ef7eb2e8f9f7 4731 #define GPIO_LCKR_LCK9 0x00000200U
<> 144:ef7eb2e8f9f7 4732 #define GPIO_LCKR_LCK10 0x00000400U
<> 144:ef7eb2e8f9f7 4733 #define GPIO_LCKR_LCK11 0x00000800U
<> 144:ef7eb2e8f9f7 4734 #define GPIO_LCKR_LCK12 0x00001000U
<> 144:ef7eb2e8f9f7 4735 #define GPIO_LCKR_LCK13 0x00002000U
<> 144:ef7eb2e8f9f7 4736 #define GPIO_LCKR_LCK14 0x00004000U
<> 144:ef7eb2e8f9f7 4737 #define GPIO_LCKR_LCK15 0x00008000U
<> 144:ef7eb2e8f9f7 4738 #define GPIO_LCKR_LCKK 0x00010000U
<> 144:ef7eb2e8f9f7 4739
<> 144:ef7eb2e8f9f7 4740 /****************** Bit definition for GPIO_AFRL register *********************/
<> 144:ef7eb2e8f9f7 4741 #define GPIO_AFRL_AFSEL0 ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 4742 #define GPIO_AFRL_AFSEL0_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4743 #define GPIO_AFRL_AFSEL0_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4744 #define GPIO_AFRL_AFSEL0_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4745 #define GPIO_AFRL_AFSEL0_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4746 #define GPIO_AFRL_AFSEL1 ((uint32_t)0x000000F0U)
<> 144:ef7eb2e8f9f7 4747 #define GPIO_AFRL_AFSEL1_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4748 #define GPIO_AFRL_AFSEL1_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4749 #define GPIO_AFRL_AFSEL1_2 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4750 #define GPIO_AFRL_AFSEL1_3 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4751 #define GPIO_AFRL_AFSEL2 ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 4752 #define GPIO_AFRL_AFSEL2_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4753 #define GPIO_AFRL_AFSEL2_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4754 #define GPIO_AFRL_AFSEL2_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4755 #define GPIO_AFRL_AFSEL2_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4756 #define GPIO_AFRL_AFSEL3 ((uint32_t)0x0000F000U)
<> 144:ef7eb2e8f9f7 4757 #define GPIO_AFRL_AFSEL3_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4758 #define GPIO_AFRL_AFSEL3_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4759 #define GPIO_AFRL_AFSEL3_2 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4760 #define GPIO_AFRL_AFSEL3_3 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4761 #define GPIO_AFRL_AFSEL4 ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 4762 #define GPIO_AFRL_AFSEL4_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 4763 #define GPIO_AFRL_AFSEL4_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 4764 #define GPIO_AFRL_AFSEL4_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 4765 #define GPIO_AFRL_AFSEL4_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 4766 #define GPIO_AFRL_AFSEL5 ((uint32_t)0x00F00000U)
<> 144:ef7eb2e8f9f7 4767 #define GPIO_AFRL_AFSEL5_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 4768 #define GPIO_AFRL_AFSEL5_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 4769 #define GPIO_AFRL_AFSEL5_2 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 4770 #define GPIO_AFRL_AFSEL5_3 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 4771 #define GPIO_AFRL_AFSEL6 ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 4772 #define GPIO_AFRL_AFSEL6_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 4773 #define GPIO_AFRL_AFSEL6_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 4774 #define GPIO_AFRL_AFSEL6_2 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 4775 #define GPIO_AFRL_AFSEL6_3 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 4776 #define GPIO_AFRL_AFSEL7 ((uint32_t)0xF0000000U)
<> 144:ef7eb2e8f9f7 4777 #define GPIO_AFRL_AFSEL7_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 4778 #define GPIO_AFRL_AFSEL7_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 4779 #define GPIO_AFRL_AFSEL7_2 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 4780 #define GPIO_AFRL_AFSEL7_3 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 4781
<> 144:ef7eb2e8f9f7 4782 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4783 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
<> 144:ef7eb2e8f9f7 4784 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
<> 144:ef7eb2e8f9f7 4785 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
<> 144:ef7eb2e8f9f7 4786 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
<> 144:ef7eb2e8f9f7 4787 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
<> 144:ef7eb2e8f9f7 4788 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
<> 144:ef7eb2e8f9f7 4789 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
<> 144:ef7eb2e8f9f7 4790 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
<> 144:ef7eb2e8f9f7 4791 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
<> 144:ef7eb2e8f9f7 4792 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
<> 144:ef7eb2e8f9f7 4793 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
<> 144:ef7eb2e8f9f7 4794 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
<> 144:ef7eb2e8f9f7 4795 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
<> 144:ef7eb2e8f9f7 4796 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
<> 144:ef7eb2e8f9f7 4797 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
<> 144:ef7eb2e8f9f7 4798 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
<> 144:ef7eb2e8f9f7 4799 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
<> 144:ef7eb2e8f9f7 4800 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
<> 144:ef7eb2e8f9f7 4801 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
<> 144:ef7eb2e8f9f7 4802 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
<> 144:ef7eb2e8f9f7 4803 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
<> 144:ef7eb2e8f9f7 4804 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
<> 144:ef7eb2e8f9f7 4805 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
<> 144:ef7eb2e8f9f7 4806 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
<> 144:ef7eb2e8f9f7 4807 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
<> 144:ef7eb2e8f9f7 4808 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
<> 144:ef7eb2e8f9f7 4809 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
<> 144:ef7eb2e8f9f7 4810 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
<> 144:ef7eb2e8f9f7 4811 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
<> 144:ef7eb2e8f9f7 4812 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
<> 144:ef7eb2e8f9f7 4813 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
<> 144:ef7eb2e8f9f7 4814 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
<> 144:ef7eb2e8f9f7 4815 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
<> 144:ef7eb2e8f9f7 4816 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
<> 144:ef7eb2e8f9f7 4817 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
<> 144:ef7eb2e8f9f7 4818 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
<> 144:ef7eb2e8f9f7 4819 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
<> 144:ef7eb2e8f9f7 4820 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
<> 144:ef7eb2e8f9f7 4821 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
<> 144:ef7eb2e8f9f7 4822 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
<> 144:ef7eb2e8f9f7 4823
<> 144:ef7eb2e8f9f7 4824 /****************** Bit definition for GPIO_AFRH register *********************/
<> 144:ef7eb2e8f9f7 4825 #define GPIO_AFRH_AFSEL8 ((uint32_t)0x0000000FU)
<> 144:ef7eb2e8f9f7 4826 #define GPIO_AFRH_AFSEL8_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4827 #define GPIO_AFRH_AFSEL8_1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4828 #define GPIO_AFRH_AFSEL8_2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4829 #define GPIO_AFRH_AFSEL8_3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4830 #define GPIO_AFRH_AFSEL9 ((uint32_t)0x000000F0U)
<> 144:ef7eb2e8f9f7 4831 #define GPIO_AFRH_AFSEL9_0 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4832 #define GPIO_AFRH_AFSEL9_1 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4833 #define GPIO_AFRH_AFSEL9_2 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4834 #define GPIO_AFRH_AFSEL9_3 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4835 #define GPIO_AFRH_AFSEL10 ((uint32_t)0x00000F00U)
<> 144:ef7eb2e8f9f7 4836 #define GPIO_AFRH_AFSEL10_0 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4837 #define GPIO_AFRH_AFSEL10_1 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4838 #define GPIO_AFRH_AFSEL10_2 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4839 #define GPIO_AFRH_AFSEL10_3 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4840 #define GPIO_AFRH_AFSEL11 ((uint32_t)0x0000F000U)
<> 144:ef7eb2e8f9f7 4841 #define GPIO_AFRH_AFSEL11_0 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4842 #define GPIO_AFRH_AFSEL11_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4843 #define GPIO_AFRH_AFSEL11_2 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4844 #define GPIO_AFRH_AFSEL11_3 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4845 #define GPIO_AFRH_AFSEL12 ((uint32_t)0x000F0000U)
<> 144:ef7eb2e8f9f7 4846 #define GPIO_AFRH_AFSEL12_0 ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 4847 #define GPIO_AFRH_AFSEL12_1 ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 4848 #define GPIO_AFRH_AFSEL12_2 ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 4849 #define GPIO_AFRH_AFSEL12_3 ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 4850 #define GPIO_AFRH_AFSEL13 ((uint32_t)0x00F00000U)
<> 144:ef7eb2e8f9f7 4851 #define GPIO_AFRH_AFSEL13_0 ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 4852 #define GPIO_AFRH_AFSEL13_1 ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 4853 #define GPIO_AFRH_AFSEL13_2 ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 4854 #define GPIO_AFRH_AFSEL13_3 ((uint32_t)0x00800000U)
<> 144:ef7eb2e8f9f7 4855 #define GPIO_AFRH_AFSEL14 ((uint32_t)0x0F000000U)
<> 144:ef7eb2e8f9f7 4856 #define GPIO_AFRH_AFSEL14_0 ((uint32_t)0x01000000U)
<> 144:ef7eb2e8f9f7 4857 #define GPIO_AFRH_AFSEL14_1 ((uint32_t)0x02000000U)
<> 144:ef7eb2e8f9f7 4858 #define GPIO_AFRH_AFSEL14_2 ((uint32_t)0x04000000U)
<> 144:ef7eb2e8f9f7 4859 #define GPIO_AFRH_AFSEL14_3 ((uint32_t)0x08000000U)
<> 144:ef7eb2e8f9f7 4860 #define GPIO_AFRH_AFSEL15 ((uint32_t)0xF0000000U)
<> 144:ef7eb2e8f9f7 4861 #define GPIO_AFRH_AFSEL15_0 ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 4862 #define GPIO_AFRH_AFSEL15_1 ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 4863 #define GPIO_AFRH_AFSEL15_2 ((uint32_t)0x40000000U)
<> 144:ef7eb2e8f9f7 4864 #define GPIO_AFRH_AFSEL15_3 ((uint32_t)0x80000000U)
<> 144:ef7eb2e8f9f7 4865
<> 144:ef7eb2e8f9f7 4866 /* Legacy defines */
<> 144:ef7eb2e8f9f7 4867 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
<> 144:ef7eb2e8f9f7 4868 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
<> 144:ef7eb2e8f9f7 4869 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
<> 144:ef7eb2e8f9f7 4870 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
<> 144:ef7eb2e8f9f7 4871 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
<> 144:ef7eb2e8f9f7 4872 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
<> 144:ef7eb2e8f9f7 4873 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
<> 144:ef7eb2e8f9f7 4874 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
<> 144:ef7eb2e8f9f7 4875 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
<> 144:ef7eb2e8f9f7 4876 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
<> 144:ef7eb2e8f9f7 4877 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
<> 144:ef7eb2e8f9f7 4878 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
<> 144:ef7eb2e8f9f7 4879 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
<> 144:ef7eb2e8f9f7 4880 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
<> 144:ef7eb2e8f9f7 4881 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
<> 144:ef7eb2e8f9f7 4882 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
<> 144:ef7eb2e8f9f7 4883 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
<> 144:ef7eb2e8f9f7 4884 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
<> 144:ef7eb2e8f9f7 4885 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
<> 144:ef7eb2e8f9f7 4886 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
<> 144:ef7eb2e8f9f7 4887 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
<> 144:ef7eb2e8f9f7 4888 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
<> 144:ef7eb2e8f9f7 4889 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
<> 144:ef7eb2e8f9f7 4890 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
<> 144:ef7eb2e8f9f7 4891 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
<> 144:ef7eb2e8f9f7 4892 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
<> 144:ef7eb2e8f9f7 4893 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
<> 144:ef7eb2e8f9f7 4894 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
<> 144:ef7eb2e8f9f7 4895 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
<> 144:ef7eb2e8f9f7 4896 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
<> 144:ef7eb2e8f9f7 4897 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
<> 144:ef7eb2e8f9f7 4898 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
<> 144:ef7eb2e8f9f7 4899 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
<> 144:ef7eb2e8f9f7 4900 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
<> 144:ef7eb2e8f9f7 4901 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
<> 144:ef7eb2e8f9f7 4902 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
<> 144:ef7eb2e8f9f7 4903 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
<> 144:ef7eb2e8f9f7 4904 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
<> 144:ef7eb2e8f9f7 4905 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
<> 144:ef7eb2e8f9f7 4906 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
<> 144:ef7eb2e8f9f7 4907
<> 144:ef7eb2e8f9f7 4908 /****************** Bits definition for GPIO_BRR register ******************/
<> 144:ef7eb2e8f9f7 4909 #define GPIO_BRR_BR0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 4910 #define GPIO_BRR_BR1 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 4911 #define GPIO_BRR_BR2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 4912 #define GPIO_BRR_BR3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 4913 #define GPIO_BRR_BR4 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 4914 #define GPIO_BRR_BR5 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 4915 #define GPIO_BRR_BR6 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 4916 #define GPIO_BRR_BR7 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 4917 #define GPIO_BRR_BR8 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 4918 #define GPIO_BRR_BR9 ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 4919 #define GPIO_BRR_BR10 ((uint32_t)0x00000400U)
<> 144:ef7eb2e8f9f7 4920 #define GPIO_BRR_BR11 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 4921 #define GPIO_BRR_BR12 ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 4922 #define GPIO_BRR_BR13 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 4923 #define GPIO_BRR_BR14 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 4924 #define GPIO_BRR_BR15 ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 4925
<> 144:ef7eb2e8f9f7 4926 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4927 /* */
<> 144:ef7eb2e8f9f7 4928 /* Inter-integrated Circuit Interface */
<> 144:ef7eb2e8f9f7 4929 /* */
<> 144:ef7eb2e8f9f7 4930 /******************************************************************************/
<> 144:ef7eb2e8f9f7 4931 /******************* Bit definition for I2C_CR1 register ********************/
<> 144:ef7eb2e8f9f7 4932 #define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
<> 144:ef7eb2e8f9f7 4933 #define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
<> 144:ef7eb2e8f9f7 4934 #define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
<> 144:ef7eb2e8f9f7 4935 #define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
<> 144:ef7eb2e8f9f7 4936 #define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
<> 144:ef7eb2e8f9f7 4937 #define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
<> 144:ef7eb2e8f9f7 4938 #define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
<> 144:ef7eb2e8f9f7 4939 #define I2C_CR1_START 0x00000100U /*!<Start Generation */
<> 144:ef7eb2e8f9f7 4940 #define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
<> 144:ef7eb2e8f9f7 4941 #define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
<> 144:ef7eb2e8f9f7 4942 #define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
<> 144:ef7eb2e8f9f7 4943 #define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
<> 144:ef7eb2e8f9f7 4944 #define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
<> 144:ef7eb2e8f9f7 4945 #define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
<> 144:ef7eb2e8f9f7 4946
<> 144:ef7eb2e8f9f7 4947 /******************* Bit definition for I2C_CR2 register ********************/
<> 144:ef7eb2e8f9f7 4948 #define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
<> 144:ef7eb2e8f9f7 4949 #define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4950 #define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4951 #define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4952 #define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4953 #define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4954 #define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4955
<> 144:ef7eb2e8f9f7 4956 #define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 4957 #define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
<> 144:ef7eb2e8f9f7 4958 #define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
<> 144:ef7eb2e8f9f7 4959 #define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
<> 144:ef7eb2e8f9f7 4960 #define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
<> 144:ef7eb2e8f9f7 4961
<> 144:ef7eb2e8f9f7 4962 /******************* Bit definition for I2C_OAR1 register *******************/
<> 144:ef7eb2e8f9f7 4963 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
<> 144:ef7eb2e8f9f7 4964 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
<> 144:ef7eb2e8f9f7 4965
<> 144:ef7eb2e8f9f7 4966 #define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4967 #define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4968 #define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4969 #define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4970 #define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4971 #define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4972 #define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4973 #define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4974 #define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 4975 #define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
<> 144:ef7eb2e8f9f7 4976
<> 144:ef7eb2e8f9f7 4977 #define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
<> 144:ef7eb2e8f9f7 4978
<> 144:ef7eb2e8f9f7 4979 /******************* Bit definition for I2C_OAR2 register *******************/
<> 144:ef7eb2e8f9f7 4980 #define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
<> 144:ef7eb2e8f9f7 4981 #define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
<> 144:ef7eb2e8f9f7 4982
<> 144:ef7eb2e8f9f7 4983 /******************** Bit definition for I2C_DR register ********************/
<> 144:ef7eb2e8f9f7 4984 #define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
<> 144:ef7eb2e8f9f7 4985
<> 144:ef7eb2e8f9f7 4986 /******************* Bit definition for I2C_SR1 register ********************/
<> 144:ef7eb2e8f9f7 4987 #define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
<> 144:ef7eb2e8f9f7 4988 #define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
<> 144:ef7eb2e8f9f7 4989 #define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
<> 144:ef7eb2e8f9f7 4990 #define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
<> 144:ef7eb2e8f9f7 4991 #define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
<> 144:ef7eb2e8f9f7 4992 #define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
<> 144:ef7eb2e8f9f7 4993 #define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
<> 144:ef7eb2e8f9f7 4994 #define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
<> 144:ef7eb2e8f9f7 4995 #define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
<> 144:ef7eb2e8f9f7 4996 #define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
<> 144:ef7eb2e8f9f7 4997 #define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
<> 144:ef7eb2e8f9f7 4998 #define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
<> 144:ef7eb2e8f9f7 4999 #define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
<> 144:ef7eb2e8f9f7 5000 #define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
<> 144:ef7eb2e8f9f7 5001
<> 144:ef7eb2e8f9f7 5002 /******************* Bit definition for I2C_SR2 register ********************/
<> 144:ef7eb2e8f9f7 5003 #define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
<> 144:ef7eb2e8f9f7 5004 #define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
<> 144:ef7eb2e8f9f7 5005 #define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
<> 144:ef7eb2e8f9f7 5006 #define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
<> 144:ef7eb2e8f9f7 5007 #define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
<> 144:ef7eb2e8f9f7 5008 #define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
<> 144:ef7eb2e8f9f7 5009 #define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
<> 144:ef7eb2e8f9f7 5010 #define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
<> 144:ef7eb2e8f9f7 5011
<> 144:ef7eb2e8f9f7 5012 /******************* Bit definition for I2C_CCR register ********************/
<> 144:ef7eb2e8f9f7 5013 #define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
<> 144:ef7eb2e8f9f7 5014 #define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
<> 144:ef7eb2e8f9f7 5015 #define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
<> 144:ef7eb2e8f9f7 5016
<> 144:ef7eb2e8f9f7 5017 /****************** Bit definition for I2C_TRISE register *******************/
<> 144:ef7eb2e8f9f7 5018 #define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
<> 144:ef7eb2e8f9f7 5019
<> 144:ef7eb2e8f9f7 5020 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5021 /* */
<> 144:ef7eb2e8f9f7 5022 /* Independent WATCHDOG */
<> 144:ef7eb2e8f9f7 5023 /* */
<> 144:ef7eb2e8f9f7 5024 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5025 /******************* Bit definition for IWDG_KR register ********************/
<> 144:ef7eb2e8f9f7 5026 #define IWDG_KR_KEY 0x0000FFFFU /*!<Key value (write only, read 0000h) */
<> 144:ef7eb2e8f9f7 5027
<> 144:ef7eb2e8f9f7 5028 /******************* Bit definition for IWDG_PR register ********************/
<> 144:ef7eb2e8f9f7 5029 #define IWDG_PR_PR 0x00000007U /*!<PR[2:0] (Prescaler divider) */
<> 144:ef7eb2e8f9f7 5030 #define IWDG_PR_PR_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5031 #define IWDG_PR_PR_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5032 #define IWDG_PR_PR_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 5033
<> 144:ef7eb2e8f9f7 5034 /******************* Bit definition for IWDG_RLR register *******************/
<> 144:ef7eb2e8f9f7 5035 #define IWDG_RLR_RL 0x00000FFFU /*!<Watchdog counter reload value */
<> 144:ef7eb2e8f9f7 5036
<> 144:ef7eb2e8f9f7 5037 /******************* Bit definition for IWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 5038 #define IWDG_SR_PVU 0x00000001U /*!<Watchdog prescaler value update */
<> 144:ef7eb2e8f9f7 5039 #define IWDG_SR_RVU 0x00000002U /*!<Watchdog counter reload value update */
<> 144:ef7eb2e8f9f7 5040
<> 144:ef7eb2e8f9f7 5041 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5042 /* */
<> 144:ef7eb2e8f9f7 5043 /* Power Control */
<> 144:ef7eb2e8f9f7 5044 /* */
<> 144:ef7eb2e8f9f7 5045 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5046 /******************** Bit definition for PWR_CR register ********************/
<> 144:ef7eb2e8f9f7 5047 #define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
<> 144:ef7eb2e8f9f7 5048 #define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
<> 144:ef7eb2e8f9f7 5049 #define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
<> 144:ef7eb2e8f9f7 5050 #define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
<> 144:ef7eb2e8f9f7 5051 #define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
<> 144:ef7eb2e8f9f7 5052
<> 144:ef7eb2e8f9f7 5053 #define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
<> 144:ef7eb2e8f9f7 5054 #define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5055 #define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5056 #define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5057
<> 144:ef7eb2e8f9f7 5058 /*!< PVD level configuration */
<> 144:ef7eb2e8f9f7 5059 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
<> 144:ef7eb2e8f9f7 5060 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
<> 144:ef7eb2e8f9f7 5061 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
<> 144:ef7eb2e8f9f7 5062 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
<> 144:ef7eb2e8f9f7 5063 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
<> 144:ef7eb2e8f9f7 5064 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
<> 144:ef7eb2e8f9f7 5065 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
<> 144:ef7eb2e8f9f7 5066 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
<> 144:ef7eb2e8f9f7 5067
<> 144:ef7eb2e8f9f7 5068 #define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
<> 144:ef7eb2e8f9f7 5069 #define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
<> 144:ef7eb2e8f9f7 5070
<> 144:ef7eb2e8f9f7 5071 /******************* Bit definition for PWR_CSR register ********************/
<> 144:ef7eb2e8f9f7 5072 #define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
<> 144:ef7eb2e8f9f7 5073 #define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
<> 144:ef7eb2e8f9f7 5074 #define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
<> 144:ef7eb2e8f9f7 5075 #define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
<> 144:ef7eb2e8f9f7 5076 #define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
<> 144:ef7eb2e8f9f7 5077 #define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
<> 144:ef7eb2e8f9f7 5078
<> 144:ef7eb2e8f9f7 5079 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5080 /* */
<> 144:ef7eb2e8f9f7 5081 /* Reset and Clock Control */
<> 144:ef7eb2e8f9f7 5082 /* */
<> 144:ef7eb2e8f9f7 5083 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5084 /******************** Bit definition for RCC_CR register ********************/
<> 144:ef7eb2e8f9f7 5085 #define RCC_CR_HSION 0x00000001U
<> 144:ef7eb2e8f9f7 5086 #define RCC_CR_HSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 5087
<> 144:ef7eb2e8f9f7 5088 #define RCC_CR_HSITRIM 0x000000F8U
<> 144:ef7eb2e8f9f7 5089 #define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5090 #define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5091 #define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
<> 144:ef7eb2e8f9f7 5092 #define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
<> 144:ef7eb2e8f9f7 5093 #define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
<> 144:ef7eb2e8f9f7 5094
<> 144:ef7eb2e8f9f7 5095 #define RCC_CR_HSICAL 0x0000FF00U
<> 144:ef7eb2e8f9f7 5096 #define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5097 #define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5098 #define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
<> 144:ef7eb2e8f9f7 5099 #define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
<> 144:ef7eb2e8f9f7 5100 #define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
<> 144:ef7eb2e8f9f7 5101 #define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
<> 144:ef7eb2e8f9f7 5102 #define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
<> 144:ef7eb2e8f9f7 5103 #define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
<> 144:ef7eb2e8f9f7 5104
<> 144:ef7eb2e8f9f7 5105 #define RCC_CR_HSEON 0x00010000U
<> 144:ef7eb2e8f9f7 5106 #define RCC_CR_HSERDY 0x00020000U
<> 144:ef7eb2e8f9f7 5107 #define RCC_CR_HSEBYP 0x00040000U
<> 144:ef7eb2e8f9f7 5108 #define RCC_CR_CSSON 0x00080000U
<> 144:ef7eb2e8f9f7 5109 #define RCC_CR_PLLON 0x01000000U
<> 144:ef7eb2e8f9f7 5110 #define RCC_CR_PLLRDY 0x02000000U
<> 144:ef7eb2e8f9f7 5111 #define RCC_CR_PLLI2SON 0x04000000U
<> 144:ef7eb2e8f9f7 5112 #define RCC_CR_PLLI2SRDY 0x08000000U
<> 144:ef7eb2e8f9f7 5113
<> 144:ef7eb2e8f9f7 5114 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 144:ef7eb2e8f9f7 5115 #define RCC_PLLCFGR_PLLM 0x0000003FU
<> 144:ef7eb2e8f9f7 5116 #define RCC_PLLCFGR_PLLM_0 0x00000001U
<> 144:ef7eb2e8f9f7 5117 #define RCC_PLLCFGR_PLLM_1 0x00000002U
<> 144:ef7eb2e8f9f7 5118 #define RCC_PLLCFGR_PLLM_2 0x00000004U
<> 144:ef7eb2e8f9f7 5119 #define RCC_PLLCFGR_PLLM_3 0x00000008U
<> 144:ef7eb2e8f9f7 5120 #define RCC_PLLCFGR_PLLM_4 0x00000010U
<> 144:ef7eb2e8f9f7 5121 #define RCC_PLLCFGR_PLLM_5 0x00000020U
<> 144:ef7eb2e8f9f7 5122
<> 144:ef7eb2e8f9f7 5123 #define RCC_PLLCFGR_PLLN 0x00007FC0U
<> 144:ef7eb2e8f9f7 5124 #define RCC_PLLCFGR_PLLN_0 0x00000040U
<> 144:ef7eb2e8f9f7 5125 #define RCC_PLLCFGR_PLLN_1 0x00000080U
<> 144:ef7eb2e8f9f7 5126 #define RCC_PLLCFGR_PLLN_2 0x00000100U
<> 144:ef7eb2e8f9f7 5127 #define RCC_PLLCFGR_PLLN_3 0x00000200U
<> 144:ef7eb2e8f9f7 5128 #define RCC_PLLCFGR_PLLN_4 0x00000400U
<> 144:ef7eb2e8f9f7 5129 #define RCC_PLLCFGR_PLLN_5 0x00000800U
<> 144:ef7eb2e8f9f7 5130 #define RCC_PLLCFGR_PLLN_6 0x00001000U
<> 144:ef7eb2e8f9f7 5131 #define RCC_PLLCFGR_PLLN_7 0x00002000U
<> 144:ef7eb2e8f9f7 5132 #define RCC_PLLCFGR_PLLN_8 0x00004000U
<> 144:ef7eb2e8f9f7 5133
<> 144:ef7eb2e8f9f7 5134 #define RCC_PLLCFGR_PLLP 0x00030000U
<> 144:ef7eb2e8f9f7 5135 #define RCC_PLLCFGR_PLLP_0 0x00010000U
<> 144:ef7eb2e8f9f7 5136 #define RCC_PLLCFGR_PLLP_1 0x00020000U
<> 144:ef7eb2e8f9f7 5137
<> 144:ef7eb2e8f9f7 5138 #define RCC_PLLCFGR_PLLSRC 0x00400000U
<> 144:ef7eb2e8f9f7 5139 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
<> 144:ef7eb2e8f9f7 5140 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
<> 144:ef7eb2e8f9f7 5141
<> 144:ef7eb2e8f9f7 5142 #define RCC_PLLCFGR_PLLQ 0x0F000000U
<> 144:ef7eb2e8f9f7 5143 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
<> 144:ef7eb2e8f9f7 5144 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
<> 144:ef7eb2e8f9f7 5145 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
<> 144:ef7eb2e8f9f7 5146 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
<> 144:ef7eb2e8f9f7 5147
<> 144:ef7eb2e8f9f7 5148 /******************** Bit definition for RCC_CFGR register ******************/
<> 144:ef7eb2e8f9f7 5149 /*!< SW configuration */
<> 144:ef7eb2e8f9f7 5150 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
<> 144:ef7eb2e8f9f7 5151 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5152 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5153
<> 144:ef7eb2e8f9f7 5154 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
<> 144:ef7eb2e8f9f7 5155 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
<> 144:ef7eb2e8f9f7 5156 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
<> 144:ef7eb2e8f9f7 5157
<> 144:ef7eb2e8f9f7 5158 /*!< SWS configuration */
<> 144:ef7eb2e8f9f7 5159 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 144:ef7eb2e8f9f7 5160 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5161 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5162
<> 144:ef7eb2e8f9f7 5163 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
<> 144:ef7eb2e8f9f7 5164 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
<> 144:ef7eb2e8f9f7 5165 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
<> 144:ef7eb2e8f9f7 5166
<> 144:ef7eb2e8f9f7 5167 /*!< HPRE configuration */
<> 144:ef7eb2e8f9f7 5168 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
<> 144:ef7eb2e8f9f7 5169 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5170 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5171 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5172 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5173
<> 144:ef7eb2e8f9f7 5174 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
<> 144:ef7eb2e8f9f7 5175 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
<> 144:ef7eb2e8f9f7 5176 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
<> 144:ef7eb2e8f9f7 5177 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
<> 144:ef7eb2e8f9f7 5178 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
<> 144:ef7eb2e8f9f7 5179 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
<> 144:ef7eb2e8f9f7 5180 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
<> 144:ef7eb2e8f9f7 5181 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
<> 144:ef7eb2e8f9f7 5182 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
<> 144:ef7eb2e8f9f7 5183
<> 144:ef7eb2e8f9f7 5184 /*!< PPRE1 configuration */
<> 144:ef7eb2e8f9f7 5185 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 144:ef7eb2e8f9f7 5186 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5187 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5188 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5189
<> 144:ef7eb2e8f9f7 5190 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 5191 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 5192 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 5193 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 5194 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 5195
<> 144:ef7eb2e8f9f7 5196 /*!< PPRE2 configuration */
<> 144:ef7eb2e8f9f7 5197 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 144:ef7eb2e8f9f7 5198 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5199 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5200 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5201
<> 144:ef7eb2e8f9f7 5202 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 5203 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 5204 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 5205 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 5206 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 5207
<> 144:ef7eb2e8f9f7 5208 /*!< RTCPRE configuration */
<> 144:ef7eb2e8f9f7 5209 #define RCC_CFGR_RTCPRE 0x001F0000U
<> 144:ef7eb2e8f9f7 5210 #define RCC_CFGR_RTCPRE_0 0x00010000U
<> 144:ef7eb2e8f9f7 5211 #define RCC_CFGR_RTCPRE_1 0x00020000U
<> 144:ef7eb2e8f9f7 5212 #define RCC_CFGR_RTCPRE_2 0x00040000U
<> 144:ef7eb2e8f9f7 5213 #define RCC_CFGR_RTCPRE_3 0x00080000U
<> 144:ef7eb2e8f9f7 5214 #define RCC_CFGR_RTCPRE_4 0x00100000U
<> 144:ef7eb2e8f9f7 5215
<> 144:ef7eb2e8f9f7 5216 /*!< MCO1 configuration */
<> 144:ef7eb2e8f9f7 5217 #define RCC_CFGR_MCO1 0x00600000U
<> 144:ef7eb2e8f9f7 5218 #define RCC_CFGR_MCO1_0 0x00200000U
<> 144:ef7eb2e8f9f7 5219 #define RCC_CFGR_MCO1_1 0x00400000U
<> 144:ef7eb2e8f9f7 5220
<> 144:ef7eb2e8f9f7 5221 #define RCC_CFGR_I2SSRC 0x00800000U
<> 144:ef7eb2e8f9f7 5222
<> 144:ef7eb2e8f9f7 5223 #define RCC_CFGR_MCO1PRE 0x07000000U
<> 144:ef7eb2e8f9f7 5224 #define RCC_CFGR_MCO1PRE_0 0x01000000U
<> 144:ef7eb2e8f9f7 5225 #define RCC_CFGR_MCO1PRE_1 0x02000000U
<> 144:ef7eb2e8f9f7 5226 #define RCC_CFGR_MCO1PRE_2 0x04000000U
<> 144:ef7eb2e8f9f7 5227
<> 144:ef7eb2e8f9f7 5228 #define RCC_CFGR_MCO2PRE 0x38000000U
<> 144:ef7eb2e8f9f7 5229 #define RCC_CFGR_MCO2PRE_0 0x08000000U
<> 144:ef7eb2e8f9f7 5230 #define RCC_CFGR_MCO2PRE_1 0x10000000U
<> 144:ef7eb2e8f9f7 5231 #define RCC_CFGR_MCO2PRE_2 0x20000000U
<> 144:ef7eb2e8f9f7 5232
<> 144:ef7eb2e8f9f7 5233 #define RCC_CFGR_MCO2 0xC0000000U
<> 144:ef7eb2e8f9f7 5234 #define RCC_CFGR_MCO2_0 0x40000000U
<> 144:ef7eb2e8f9f7 5235 #define RCC_CFGR_MCO2_1 0x80000000U
<> 144:ef7eb2e8f9f7 5236
<> 144:ef7eb2e8f9f7 5237 /******************** Bit definition for RCC_CIR register *******************/
<> 144:ef7eb2e8f9f7 5238 #define RCC_CIR_LSIRDYF 0x00000001U
<> 144:ef7eb2e8f9f7 5239 #define RCC_CIR_LSERDYF 0x00000002U
<> 144:ef7eb2e8f9f7 5240 #define RCC_CIR_HSIRDYF 0x00000004U
<> 144:ef7eb2e8f9f7 5241 #define RCC_CIR_HSERDYF 0x00000008U
<> 144:ef7eb2e8f9f7 5242 #define RCC_CIR_PLLRDYF 0x00000010U
<> 144:ef7eb2e8f9f7 5243 #define RCC_CIR_PLLI2SRDYF 0x00000020U
<> 144:ef7eb2e8f9f7 5244
<> 144:ef7eb2e8f9f7 5245 #define RCC_CIR_CSSF 0x00000080U
<> 144:ef7eb2e8f9f7 5246 #define RCC_CIR_LSIRDYIE 0x00000100U
<> 144:ef7eb2e8f9f7 5247 #define RCC_CIR_LSERDYIE 0x00000200U
<> 144:ef7eb2e8f9f7 5248 #define RCC_CIR_HSIRDYIE 0x00000400U
<> 144:ef7eb2e8f9f7 5249 #define RCC_CIR_HSERDYIE 0x00000800U
<> 144:ef7eb2e8f9f7 5250 #define RCC_CIR_PLLRDYIE 0x00001000U
<> 144:ef7eb2e8f9f7 5251 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
<> 144:ef7eb2e8f9f7 5252
<> 144:ef7eb2e8f9f7 5253 #define RCC_CIR_LSIRDYC 0x00010000U
<> 144:ef7eb2e8f9f7 5254 #define RCC_CIR_LSERDYC 0x00020000U
<> 144:ef7eb2e8f9f7 5255 #define RCC_CIR_HSIRDYC 0x00040000U
<> 144:ef7eb2e8f9f7 5256 #define RCC_CIR_HSERDYC 0x00080000U
<> 144:ef7eb2e8f9f7 5257 #define RCC_CIR_PLLRDYC 0x00100000U
<> 144:ef7eb2e8f9f7 5258 #define RCC_CIR_PLLI2SRDYC 0x00200000U
<> 144:ef7eb2e8f9f7 5259
<> 144:ef7eb2e8f9f7 5260 #define RCC_CIR_CSSC 0x00800000U
<> 144:ef7eb2e8f9f7 5261
<> 144:ef7eb2e8f9f7 5262 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 144:ef7eb2e8f9f7 5263 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
<> 144:ef7eb2e8f9f7 5264 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
<> 144:ef7eb2e8f9f7 5265 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
<> 144:ef7eb2e8f9f7 5266 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
<> 144:ef7eb2e8f9f7 5267 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
<> 144:ef7eb2e8f9f7 5268 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
<> 144:ef7eb2e8f9f7 5269 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
<> 144:ef7eb2e8f9f7 5270 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
<> 144:ef7eb2e8f9f7 5271 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
<> 144:ef7eb2e8f9f7 5272 #define RCC_AHB1RSTR_CRCRST 0x00001000U
<> 144:ef7eb2e8f9f7 5273 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
<> 144:ef7eb2e8f9f7 5274 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
<> 144:ef7eb2e8f9f7 5275 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
<> 144:ef7eb2e8f9f7 5276 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
<> 144:ef7eb2e8f9f7 5277
<> 144:ef7eb2e8f9f7 5278 /******************** Bit definition for RCC_AHB2RSTR register **************/
<> 144:ef7eb2e8f9f7 5279 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
<> 144:ef7eb2e8f9f7 5280 #define RCC_AHB2RSTR_RNGRST 0x00000040U
<> 144:ef7eb2e8f9f7 5281 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
<> 144:ef7eb2e8f9f7 5282
<> 144:ef7eb2e8f9f7 5283 /******************** Bit definition for RCC_AHB3RSTR register **************/
<> 144:ef7eb2e8f9f7 5284
<> 144:ef7eb2e8f9f7 5285 #define RCC_AHB3RSTR_FSMCRST 0x00000001U
<> 144:ef7eb2e8f9f7 5286
<> 144:ef7eb2e8f9f7 5287 /******************** Bit definition for RCC_APB1RSTR register **************/
<> 144:ef7eb2e8f9f7 5288 #define RCC_APB1RSTR_TIM2RST 0x00000001U
<> 144:ef7eb2e8f9f7 5289 #define RCC_APB1RSTR_TIM3RST 0x00000002U
<> 144:ef7eb2e8f9f7 5290 #define RCC_APB1RSTR_TIM4RST 0x00000004U
<> 144:ef7eb2e8f9f7 5291 #define RCC_APB1RSTR_TIM5RST 0x00000008U
<> 144:ef7eb2e8f9f7 5292 #define RCC_APB1RSTR_TIM6RST 0x00000010U
<> 144:ef7eb2e8f9f7 5293 #define RCC_APB1RSTR_TIM7RST 0x00000020U
<> 144:ef7eb2e8f9f7 5294 #define RCC_APB1RSTR_TIM12RST 0x00000040U
<> 144:ef7eb2e8f9f7 5295 #define RCC_APB1RSTR_TIM13RST 0x00000080U
<> 144:ef7eb2e8f9f7 5296 #define RCC_APB1RSTR_TIM14RST 0x00000100U
<> 144:ef7eb2e8f9f7 5297 #define RCC_APB1RSTR_WWDGRST 0x00000800U
<> 144:ef7eb2e8f9f7 5298 #define RCC_APB1RSTR_SPI2RST 0x00004000U
<> 144:ef7eb2e8f9f7 5299 #define RCC_APB1RSTR_SPI3RST 0x00008000U
<> 144:ef7eb2e8f9f7 5300 #define RCC_APB1RSTR_USART2RST 0x00020000U
<> 144:ef7eb2e8f9f7 5301 #define RCC_APB1RSTR_USART3RST 0x00040000U
<> 144:ef7eb2e8f9f7 5302 #define RCC_APB1RSTR_UART4RST 0x00080000U
<> 144:ef7eb2e8f9f7 5303 #define RCC_APB1RSTR_UART5RST 0x00100000U
<> 144:ef7eb2e8f9f7 5304 #define RCC_APB1RSTR_I2C1RST 0x00200000U
<> 144:ef7eb2e8f9f7 5305 #define RCC_APB1RSTR_I2C2RST 0x00400000U
<> 144:ef7eb2e8f9f7 5306 #define RCC_APB1RSTR_I2C3RST 0x00800000U
<> 144:ef7eb2e8f9f7 5307 #define RCC_APB1RSTR_CAN1RST 0x02000000U
<> 144:ef7eb2e8f9f7 5308 #define RCC_APB1RSTR_CAN2RST 0x04000000U
<> 144:ef7eb2e8f9f7 5309 #define RCC_APB1RSTR_PWRRST 0x10000000U
<> 144:ef7eb2e8f9f7 5310 #define RCC_APB1RSTR_DACRST 0x20000000U
<> 144:ef7eb2e8f9f7 5311
<> 144:ef7eb2e8f9f7 5312 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 144:ef7eb2e8f9f7 5313 #define RCC_APB2RSTR_TIM1RST 0x00000001U
<> 144:ef7eb2e8f9f7 5314 #define RCC_APB2RSTR_TIM8RST 0x00000002U
<> 144:ef7eb2e8f9f7 5315 #define RCC_APB2RSTR_USART1RST 0x00000010U
<> 144:ef7eb2e8f9f7 5316 #define RCC_APB2RSTR_USART6RST 0x00000020U
<> 144:ef7eb2e8f9f7 5317 #define RCC_APB2RSTR_ADCRST 0x00000100U
<> 144:ef7eb2e8f9f7 5318 #define RCC_APB2RSTR_SDIORST 0x00000800U
<> 144:ef7eb2e8f9f7 5319 #define RCC_APB2RSTR_SPI1RST 0x00001000U
<> 144:ef7eb2e8f9f7 5320 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
<> 144:ef7eb2e8f9f7 5321 #define RCC_APB2RSTR_TIM9RST 0x00010000U
<> 144:ef7eb2e8f9f7 5322 #define RCC_APB2RSTR_TIM10RST 0x00020000U
<> 144:ef7eb2e8f9f7 5323 #define RCC_APB2RSTR_TIM11RST 0x00040000U
<> 144:ef7eb2e8f9f7 5324
<> 144:ef7eb2e8f9f7 5325 /* Old SPI1RST bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 5326 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
<> 144:ef7eb2e8f9f7 5327
<> 144:ef7eb2e8f9f7 5328 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 144:ef7eb2e8f9f7 5329 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
<> 144:ef7eb2e8f9f7 5330 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
<> 144:ef7eb2e8f9f7 5331 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
<> 144:ef7eb2e8f9f7 5332 #define RCC_AHB1ENR_GPIODEN 0x00000008U
<> 144:ef7eb2e8f9f7 5333 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
<> 144:ef7eb2e8f9f7 5334 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
<> 144:ef7eb2e8f9f7 5335 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
<> 144:ef7eb2e8f9f7 5336 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
<> 144:ef7eb2e8f9f7 5337 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
<> 144:ef7eb2e8f9f7 5338 #define RCC_AHB1ENR_CRCEN 0x00001000U
<> 144:ef7eb2e8f9f7 5339 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
<> 144:ef7eb2e8f9f7 5340 #define RCC_AHB1ENR_DMA1EN 0x00200000U
<> 144:ef7eb2e8f9f7 5341 #define RCC_AHB1ENR_DMA2EN 0x00400000U
<> 144:ef7eb2e8f9f7 5342
<> 144:ef7eb2e8f9f7 5343 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
<> 144:ef7eb2e8f9f7 5344 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
<> 144:ef7eb2e8f9f7 5345 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
<> 144:ef7eb2e8f9f7 5346 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
<> 144:ef7eb2e8f9f7 5347 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
<> 144:ef7eb2e8f9f7 5348 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
<> 144:ef7eb2e8f9f7 5349
<> 144:ef7eb2e8f9f7 5350 /******************** Bit definition for RCC_AHB2ENR register ***************/
<> 144:ef7eb2e8f9f7 5351 #define RCC_AHB2ENR_DCMIEN 0x00000001U
<> 144:ef7eb2e8f9f7 5352 #define RCC_AHB2ENR_RNGEN 0x00000040U
<> 144:ef7eb2e8f9f7 5353 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
<> 144:ef7eb2e8f9f7 5354
<> 144:ef7eb2e8f9f7 5355 /******************** Bit definition for RCC_AHB3ENR register ***************/
<> 144:ef7eb2e8f9f7 5356
<> 144:ef7eb2e8f9f7 5357 #define RCC_AHB3ENR_FSMCEN 0x00000001U
<> 144:ef7eb2e8f9f7 5358
<> 144:ef7eb2e8f9f7 5359 /******************** Bit definition for RCC_APB1ENR register ***************/
<> 144:ef7eb2e8f9f7 5360 #define RCC_APB1ENR_TIM2EN 0x00000001U
<> 144:ef7eb2e8f9f7 5361 #define RCC_APB1ENR_TIM3EN 0x00000002U
<> 144:ef7eb2e8f9f7 5362 #define RCC_APB1ENR_TIM4EN 0x00000004U
<> 144:ef7eb2e8f9f7 5363 #define RCC_APB1ENR_TIM5EN 0x00000008U
<> 144:ef7eb2e8f9f7 5364 #define RCC_APB1ENR_TIM6EN 0x00000010U
<> 144:ef7eb2e8f9f7 5365 #define RCC_APB1ENR_TIM7EN 0x00000020U
<> 144:ef7eb2e8f9f7 5366 #define RCC_APB1ENR_TIM12EN 0x00000040U
<> 144:ef7eb2e8f9f7 5367 #define RCC_APB1ENR_TIM13EN 0x00000080U
<> 144:ef7eb2e8f9f7 5368 #define RCC_APB1ENR_TIM14EN 0x00000100U
<> 144:ef7eb2e8f9f7 5369 #define RCC_APB1ENR_WWDGEN 0x00000800U
<> 144:ef7eb2e8f9f7 5370 #define RCC_APB1ENR_SPI2EN 0x00004000U
<> 144:ef7eb2e8f9f7 5371 #define RCC_APB1ENR_SPI3EN 0x00008000U
<> 144:ef7eb2e8f9f7 5372 #define RCC_APB1ENR_USART2EN 0x00020000U
<> 144:ef7eb2e8f9f7 5373 #define RCC_APB1ENR_USART3EN 0x00040000U
<> 144:ef7eb2e8f9f7 5374 #define RCC_APB1ENR_UART4EN 0x00080000U
<> 144:ef7eb2e8f9f7 5375 #define RCC_APB1ENR_UART5EN 0x00100000U
<> 144:ef7eb2e8f9f7 5376 #define RCC_APB1ENR_I2C1EN 0x00200000U
<> 144:ef7eb2e8f9f7 5377 #define RCC_APB1ENR_I2C2EN 0x00400000U
<> 144:ef7eb2e8f9f7 5378 #define RCC_APB1ENR_I2C3EN 0x00800000U
<> 144:ef7eb2e8f9f7 5379 #define RCC_APB1ENR_CAN1EN 0x02000000U
<> 144:ef7eb2e8f9f7 5380 #define RCC_APB1ENR_CAN2EN 0x04000000U
<> 144:ef7eb2e8f9f7 5381 #define RCC_APB1ENR_PWREN 0x10000000U
<> 144:ef7eb2e8f9f7 5382 #define RCC_APB1ENR_DACEN 0x20000000U
<> 144:ef7eb2e8f9f7 5383
<> 144:ef7eb2e8f9f7 5384 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 144:ef7eb2e8f9f7 5385 #define RCC_APB2ENR_TIM1EN 0x00000001U
<> 144:ef7eb2e8f9f7 5386 #define RCC_APB2ENR_TIM8EN 0x00000002U
<> 144:ef7eb2e8f9f7 5387 #define RCC_APB2ENR_USART1EN 0x00000010U
<> 144:ef7eb2e8f9f7 5388 #define RCC_APB2ENR_USART6EN 0x00000020U
<> 144:ef7eb2e8f9f7 5389 #define RCC_APB2ENR_ADC1EN 0x00000100U
<> 144:ef7eb2e8f9f7 5390 #define RCC_APB2ENR_ADC2EN 0x00000200U
<> 144:ef7eb2e8f9f7 5391 #define RCC_APB2ENR_ADC3EN 0x00000400U
<> 144:ef7eb2e8f9f7 5392 #define RCC_APB2ENR_SDIOEN 0x00000800U
<> 144:ef7eb2e8f9f7 5393 #define RCC_APB2ENR_SPI1EN 0x00001000U
<> 144:ef7eb2e8f9f7 5394 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
<> 144:ef7eb2e8f9f7 5395 #define RCC_APB2ENR_TIM9EN 0x00010000U
<> 144:ef7eb2e8f9f7 5396 #define RCC_APB2ENR_TIM10EN 0x00020000U
<> 144:ef7eb2e8f9f7 5397 #define RCC_APB2ENR_TIM11EN 0x00040000U
<> 144:ef7eb2e8f9f7 5398
<> 144:ef7eb2e8f9f7 5399 /******************** Bit definition for RCC_AHB1LPENR register *************/
<> 144:ef7eb2e8f9f7 5400 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5401 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
<> 144:ef7eb2e8f9f7 5402 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
<> 144:ef7eb2e8f9f7 5403 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
<> 144:ef7eb2e8f9f7 5404 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
<> 144:ef7eb2e8f9f7 5405 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
<> 144:ef7eb2e8f9f7 5406 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
<> 144:ef7eb2e8f9f7 5407 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
<> 144:ef7eb2e8f9f7 5408 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
<> 144:ef7eb2e8f9f7 5409 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
<> 144:ef7eb2e8f9f7 5410 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
<> 144:ef7eb2e8f9f7 5411 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 5412 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 5413 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
<> 144:ef7eb2e8f9f7 5414 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 5415 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 5416 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
<> 144:ef7eb2e8f9f7 5417 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
<> 144:ef7eb2e8f9f7 5418 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
<> 144:ef7eb2e8f9f7 5419 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
<> 144:ef7eb2e8f9f7 5420 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
<> 144:ef7eb2e8f9f7 5421 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
<> 144:ef7eb2e8f9f7 5422
<> 144:ef7eb2e8f9f7 5423 /******************** Bit definition for RCC_AHB2LPENR register *************/
<> 144:ef7eb2e8f9f7 5424 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5425 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
<> 144:ef7eb2e8f9f7 5426 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
<> 144:ef7eb2e8f9f7 5427
<> 144:ef7eb2e8f9f7 5428 /******************** Bit definition for RCC_AHB3LPENR register *************/
<> 144:ef7eb2e8f9f7 5429
<> 144:ef7eb2e8f9f7 5430 #define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5431
<> 144:ef7eb2e8f9f7 5432 /******************** Bit definition for RCC_APB1LPENR register *************/
<> 144:ef7eb2e8f9f7 5433 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5434 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
<> 144:ef7eb2e8f9f7 5435 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
<> 144:ef7eb2e8f9f7 5436 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
<> 144:ef7eb2e8f9f7 5437 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
<> 144:ef7eb2e8f9f7 5438 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
<> 144:ef7eb2e8f9f7 5439 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
<> 144:ef7eb2e8f9f7 5440 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
<> 144:ef7eb2e8f9f7 5441 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
<> 144:ef7eb2e8f9f7 5442 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
<> 144:ef7eb2e8f9f7 5443 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
<> 144:ef7eb2e8f9f7 5444 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
<> 144:ef7eb2e8f9f7 5445 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 5446 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
<> 144:ef7eb2e8f9f7 5447 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
<> 144:ef7eb2e8f9f7 5448 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
<> 144:ef7eb2e8f9f7 5449 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 5450 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 5451 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
<> 144:ef7eb2e8f9f7 5452 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
<> 144:ef7eb2e8f9f7 5453 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
<> 144:ef7eb2e8f9f7 5454 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
<> 144:ef7eb2e8f9f7 5455 #define RCC_APB1LPENR_DACLPEN 0x20000000U
<> 144:ef7eb2e8f9f7 5456
<> 144:ef7eb2e8f9f7 5457 /******************** Bit definition for RCC_APB2LPENR register *************/
<> 144:ef7eb2e8f9f7 5458 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5459 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
<> 144:ef7eb2e8f9f7 5460 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
<> 144:ef7eb2e8f9f7 5461 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
<> 144:ef7eb2e8f9f7 5462 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
<> 144:ef7eb2e8f9f7 5463 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
<> 144:ef7eb2e8f9f7 5464 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
<> 144:ef7eb2e8f9f7 5465 #define RCC_APB2LPENR_SDIOLPEN 0x00000800U
<> 144:ef7eb2e8f9f7 5466 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
<> 144:ef7eb2e8f9f7 5467 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
<> 144:ef7eb2e8f9f7 5468 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 5469 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 5470 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
<> 144:ef7eb2e8f9f7 5471
<> 144:ef7eb2e8f9f7 5472 /******************** Bit definition for RCC_BDCR register ******************/
<> 144:ef7eb2e8f9f7 5473 #define RCC_BDCR_LSEON 0x00000001U
<> 144:ef7eb2e8f9f7 5474 #define RCC_BDCR_LSERDY 0x00000002U
<> 144:ef7eb2e8f9f7 5475 #define RCC_BDCR_LSEBYP 0x00000004U
<> 144:ef7eb2e8f9f7 5476
<> 144:ef7eb2e8f9f7 5477 #define RCC_BDCR_RTCSEL 0x00000300U
<> 144:ef7eb2e8f9f7 5478 #define RCC_BDCR_RTCSEL_0 0x00000100U
<> 144:ef7eb2e8f9f7 5479 #define RCC_BDCR_RTCSEL_1 0x00000200U
<> 144:ef7eb2e8f9f7 5480
<> 144:ef7eb2e8f9f7 5481 #define RCC_BDCR_RTCEN 0x00008000U
<> 144:ef7eb2e8f9f7 5482 #define RCC_BDCR_BDRST 0x00010000U
<> 144:ef7eb2e8f9f7 5483
<> 144:ef7eb2e8f9f7 5484 /******************** Bit definition for RCC_CSR register *******************/
<> 144:ef7eb2e8f9f7 5485 #define RCC_CSR_LSION 0x00000001U
<> 144:ef7eb2e8f9f7 5486 #define RCC_CSR_LSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 5487 #define RCC_CSR_RMVF 0x01000000U
<> 144:ef7eb2e8f9f7 5488 #define RCC_CSR_BORRSTF 0x02000000U
<> 144:ef7eb2e8f9f7 5489 #define RCC_CSR_PADRSTF 0x04000000U
<> 144:ef7eb2e8f9f7 5490 #define RCC_CSR_PORRSTF 0x08000000U
<> 144:ef7eb2e8f9f7 5491 #define RCC_CSR_SFTRSTF 0x10000000U
<> 144:ef7eb2e8f9f7 5492 #define RCC_CSR_WDGRSTF 0x20000000U
<> 144:ef7eb2e8f9f7 5493 #define RCC_CSR_WWDGRSTF 0x40000000U
<> 144:ef7eb2e8f9f7 5494 #define RCC_CSR_LPWRRSTF 0x80000000U
<> 144:ef7eb2e8f9f7 5495
<> 144:ef7eb2e8f9f7 5496 /******************** Bit definition for RCC_SSCGR register *****************/
<> 144:ef7eb2e8f9f7 5497 #define RCC_SSCGR_MODPER 0x00001FFFU
<> 144:ef7eb2e8f9f7 5498 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
<> 144:ef7eb2e8f9f7 5499 #define RCC_SSCGR_SPREADSEL 0x40000000U
<> 144:ef7eb2e8f9f7 5500 #define RCC_SSCGR_SSCGEN 0x80000000U
<> 144:ef7eb2e8f9f7 5501
<> 144:ef7eb2e8f9f7 5502 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
<> 144:ef7eb2e8f9f7 5503 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
<> 144:ef7eb2e8f9f7 5504 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
<> 144:ef7eb2e8f9f7 5505 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
<> 144:ef7eb2e8f9f7 5506 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
<> 144:ef7eb2e8f9f7 5507 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
<> 144:ef7eb2e8f9f7 5508 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
<> 144:ef7eb2e8f9f7 5509 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
<> 144:ef7eb2e8f9f7 5510 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
<> 144:ef7eb2e8f9f7 5511 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
<> 144:ef7eb2e8f9f7 5512 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
<> 144:ef7eb2e8f9f7 5513
<> 144:ef7eb2e8f9f7 5514 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
<> 144:ef7eb2e8f9f7 5515 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
<> 144:ef7eb2e8f9f7 5516 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
<> 144:ef7eb2e8f9f7 5517 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
<> 144:ef7eb2e8f9f7 5518
<> 144:ef7eb2e8f9f7 5519 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5520 /* */
<> 144:ef7eb2e8f9f7 5521 /* RNG */
<> 144:ef7eb2e8f9f7 5522 /* */
<> 144:ef7eb2e8f9f7 5523 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5524 /******************** Bits definition for RNG_CR register *******************/
<> 144:ef7eb2e8f9f7 5525 #define RNG_CR_RNGEN 0x00000004U
<> 144:ef7eb2e8f9f7 5526 #define RNG_CR_IE 0x00000008U
<> 144:ef7eb2e8f9f7 5527
<> 144:ef7eb2e8f9f7 5528 /******************** Bits definition for RNG_SR register *******************/
<> 144:ef7eb2e8f9f7 5529 #define RNG_SR_DRDY 0x00000001U
<> 144:ef7eb2e8f9f7 5530 #define RNG_SR_CECS 0x00000002U
<> 144:ef7eb2e8f9f7 5531 #define RNG_SR_SECS 0x00000004U
<> 144:ef7eb2e8f9f7 5532 #define RNG_SR_CEIS 0x00000020U
<> 144:ef7eb2e8f9f7 5533 #define RNG_SR_SEIS 0x00000040U
<> 144:ef7eb2e8f9f7 5534
<> 144:ef7eb2e8f9f7 5535 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5536 /* */
<> 144:ef7eb2e8f9f7 5537 /* Real-Time Clock (RTC) */
<> 144:ef7eb2e8f9f7 5538 /* */
<> 144:ef7eb2e8f9f7 5539 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5540 /******************** Bits definition for RTC_TR register *******************/
<> 144:ef7eb2e8f9f7 5541 #define RTC_TR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 5542 #define RTC_TR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 5543 #define RTC_TR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 5544 #define RTC_TR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 5545 #define RTC_TR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 5546 #define RTC_TR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 5547 #define RTC_TR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 5548 #define RTC_TR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 5549 #define RTC_TR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 5550 #define RTC_TR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 5551 #define RTC_TR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 5552 #define RTC_TR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 5553 #define RTC_TR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 5554 #define RTC_TR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 5555 #define RTC_TR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 5556 #define RTC_TR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 5557 #define RTC_TR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 5558 #define RTC_TR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 5559 #define RTC_TR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 5560 #define RTC_TR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 5561 #define RTC_TR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 5562 #define RTC_TR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 5563 #define RTC_TR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 5564 #define RTC_TR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 5565 #define RTC_TR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 5566 #define RTC_TR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 5567 #define RTC_TR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 5568
<> 144:ef7eb2e8f9f7 5569 /******************** Bits definition for RTC_DR register *******************/
<> 144:ef7eb2e8f9f7 5570 #define RTC_DR_YT 0x00F00000U
<> 144:ef7eb2e8f9f7 5571 #define RTC_DR_YT_0 0x00100000U
<> 144:ef7eb2e8f9f7 5572 #define RTC_DR_YT_1 0x00200000U
<> 144:ef7eb2e8f9f7 5573 #define RTC_DR_YT_2 0x00400000U
<> 144:ef7eb2e8f9f7 5574 #define RTC_DR_YT_3 0x00800000U
<> 144:ef7eb2e8f9f7 5575 #define RTC_DR_YU 0x000F0000U
<> 144:ef7eb2e8f9f7 5576 #define RTC_DR_YU_0 0x00010000U
<> 144:ef7eb2e8f9f7 5577 #define RTC_DR_YU_1 0x00020000U
<> 144:ef7eb2e8f9f7 5578 #define RTC_DR_YU_2 0x00040000U
<> 144:ef7eb2e8f9f7 5579 #define RTC_DR_YU_3 0x00080000U
<> 144:ef7eb2e8f9f7 5580 #define RTC_DR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 5581 #define RTC_DR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 5582 #define RTC_DR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 5583 #define RTC_DR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 5584 #define RTC_DR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 5585 #define RTC_DR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 5586 #define RTC_DR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 5587 #define RTC_DR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 5588 #define RTC_DR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 5589 #define RTC_DR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 5590 #define RTC_DR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 5591 #define RTC_DR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 5592 #define RTC_DR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 5593 #define RTC_DR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 5594 #define RTC_DR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 5595 #define RTC_DR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 5596 #define RTC_DR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 5597 #define RTC_DR_DU_3 0x00000008U
<> 144:ef7eb2e8f9f7 5598
<> 144:ef7eb2e8f9f7 5599 /******************** Bits definition for RTC_CR register *******************/
<> 144:ef7eb2e8f9f7 5600 #define RTC_CR_COE 0x00800000U
<> 144:ef7eb2e8f9f7 5601 #define RTC_CR_OSEL 0x00600000U
<> 144:ef7eb2e8f9f7 5602 #define RTC_CR_OSEL_0 0x00200000U
<> 144:ef7eb2e8f9f7 5603 #define RTC_CR_OSEL_1 0x00400000U
<> 144:ef7eb2e8f9f7 5604 #define RTC_CR_POL 0x00100000U
<> 144:ef7eb2e8f9f7 5605 #define RTC_CR_BCK 0x00040000U
<> 144:ef7eb2e8f9f7 5606 #define RTC_CR_SUB1H 0x00020000U
<> 144:ef7eb2e8f9f7 5607 #define RTC_CR_ADD1H 0x00010000U
<> 144:ef7eb2e8f9f7 5608 #define RTC_CR_TSIE 0x00008000U
<> 144:ef7eb2e8f9f7 5609 #define RTC_CR_WUTIE 0x00004000U
<> 144:ef7eb2e8f9f7 5610 #define RTC_CR_ALRBIE 0x00002000U
<> 144:ef7eb2e8f9f7 5611 #define RTC_CR_ALRAIE 0x00001000U
<> 144:ef7eb2e8f9f7 5612 #define RTC_CR_TSE 0x00000800U
<> 144:ef7eb2e8f9f7 5613 #define RTC_CR_WUTE 0x00000400U
<> 144:ef7eb2e8f9f7 5614 #define RTC_CR_ALRBE 0x00000200U
<> 144:ef7eb2e8f9f7 5615 #define RTC_CR_ALRAE 0x00000100U
<> 144:ef7eb2e8f9f7 5616 #define RTC_CR_DCE 0x00000080U
<> 144:ef7eb2e8f9f7 5617 #define RTC_CR_FMT 0x00000040U
<> 144:ef7eb2e8f9f7 5618 #define RTC_CR_REFCKON 0x00000010U
<> 144:ef7eb2e8f9f7 5619 #define RTC_CR_TSEDGE 0x00000008U
<> 144:ef7eb2e8f9f7 5620 #define RTC_CR_WUCKSEL 0x00000007U
<> 144:ef7eb2e8f9f7 5621 #define RTC_CR_WUCKSEL_0 0x00000001U
<> 144:ef7eb2e8f9f7 5622 #define RTC_CR_WUCKSEL_1 0x00000002U
<> 144:ef7eb2e8f9f7 5623 #define RTC_CR_WUCKSEL_2 0x00000004U
<> 144:ef7eb2e8f9f7 5624
<> 144:ef7eb2e8f9f7 5625 /******************** Bits definition for RTC_ISR register ******************/
<> 144:ef7eb2e8f9f7 5626 #define RTC_ISR_TAMP1F 0x00002000U
<> 144:ef7eb2e8f9f7 5627 #define RTC_ISR_TSOVF 0x00001000U
<> 144:ef7eb2e8f9f7 5628 #define RTC_ISR_TSF 0x00000800U
<> 144:ef7eb2e8f9f7 5629 #define RTC_ISR_WUTF 0x00000400U
<> 144:ef7eb2e8f9f7 5630 #define RTC_ISR_ALRBF 0x00000200U
<> 144:ef7eb2e8f9f7 5631 #define RTC_ISR_ALRAF 0x00000100U
<> 144:ef7eb2e8f9f7 5632 #define RTC_ISR_INIT 0x00000080U
<> 144:ef7eb2e8f9f7 5633 #define RTC_ISR_INITF 0x00000040U
<> 144:ef7eb2e8f9f7 5634 #define RTC_ISR_RSF 0x00000020U
<> 144:ef7eb2e8f9f7 5635 #define RTC_ISR_INITS 0x00000010U
<> 144:ef7eb2e8f9f7 5636 #define RTC_ISR_WUTWF 0x00000004U
<> 144:ef7eb2e8f9f7 5637 #define RTC_ISR_ALRBWF 0x00000002U
<> 144:ef7eb2e8f9f7 5638 #define RTC_ISR_ALRAWF 0x00000001U
<> 144:ef7eb2e8f9f7 5639
<> 144:ef7eb2e8f9f7 5640 /******************** Bits definition for RTC_PRER register *****************/
<> 144:ef7eb2e8f9f7 5641 #define RTC_PRER_PREDIV_A 0x007F0000U
<> 144:ef7eb2e8f9f7 5642 #define RTC_PRER_PREDIV_S 0x00001FFFU
<> 144:ef7eb2e8f9f7 5643
<> 144:ef7eb2e8f9f7 5644 /******************** Bits definition for RTC_WUTR register *****************/
<> 144:ef7eb2e8f9f7 5645 #define RTC_WUTR_WUT 0x0000FFFFU
<> 144:ef7eb2e8f9f7 5646
<> 144:ef7eb2e8f9f7 5647 /******************** Bits definition for RTC_CALIBR register ***************/
<> 144:ef7eb2e8f9f7 5648 #define RTC_CALIBR_DCS 0x00000080U
<> 144:ef7eb2e8f9f7 5649 #define RTC_CALIBR_DC 0x0000001FU
<> 144:ef7eb2e8f9f7 5650
<> 144:ef7eb2e8f9f7 5651 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 144:ef7eb2e8f9f7 5652 #define RTC_ALRMAR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 5653 #define RTC_ALRMAR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 5654 #define RTC_ALRMAR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 5655 #define RTC_ALRMAR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 5656 #define RTC_ALRMAR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 5657 #define RTC_ALRMAR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 5658 #define RTC_ALRMAR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 5659 #define RTC_ALRMAR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 5660 #define RTC_ALRMAR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 5661 #define RTC_ALRMAR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 5662 #define RTC_ALRMAR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 5663 #define RTC_ALRMAR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 5664 #define RTC_ALRMAR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 5665 #define RTC_ALRMAR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 5666 #define RTC_ALRMAR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 5667 #define RTC_ALRMAR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 5668 #define RTC_ALRMAR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 5669 #define RTC_ALRMAR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 5670 #define RTC_ALRMAR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 5671 #define RTC_ALRMAR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 5672 #define RTC_ALRMAR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 5673 #define RTC_ALRMAR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 5674 #define RTC_ALRMAR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 5675 #define RTC_ALRMAR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 5676 #define RTC_ALRMAR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 5677 #define RTC_ALRMAR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 5678 #define RTC_ALRMAR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 5679 #define RTC_ALRMAR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 5680 #define RTC_ALRMAR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 5681 #define RTC_ALRMAR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 5682 #define RTC_ALRMAR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 5683 #define RTC_ALRMAR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 5684 #define RTC_ALRMAR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 5685 #define RTC_ALRMAR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 5686 #define RTC_ALRMAR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 5687 #define RTC_ALRMAR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 5688 #define RTC_ALRMAR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 5689 #define RTC_ALRMAR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 5690 #define RTC_ALRMAR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 5691 #define RTC_ALRMAR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 5692
<> 144:ef7eb2e8f9f7 5693 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 144:ef7eb2e8f9f7 5694 #define RTC_ALRMBR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 5695 #define RTC_ALRMBR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 5696 #define RTC_ALRMBR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 5697 #define RTC_ALRMBR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 5698 #define RTC_ALRMBR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 5699 #define RTC_ALRMBR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 5700 #define RTC_ALRMBR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 5701 #define RTC_ALRMBR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 5702 #define RTC_ALRMBR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 5703 #define RTC_ALRMBR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 5704 #define RTC_ALRMBR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 5705 #define RTC_ALRMBR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 5706 #define RTC_ALRMBR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 5707 #define RTC_ALRMBR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 5708 #define RTC_ALRMBR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 5709 #define RTC_ALRMBR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 5710 #define RTC_ALRMBR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 5711 #define RTC_ALRMBR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 5712 #define RTC_ALRMBR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 5713 #define RTC_ALRMBR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 5714 #define RTC_ALRMBR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 5715 #define RTC_ALRMBR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 5716 #define RTC_ALRMBR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 5717 #define RTC_ALRMBR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 5718 #define RTC_ALRMBR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 5719 #define RTC_ALRMBR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 5720 #define RTC_ALRMBR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 5721 #define RTC_ALRMBR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 5722 #define RTC_ALRMBR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 5723 #define RTC_ALRMBR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 5724 #define RTC_ALRMBR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 5725 #define RTC_ALRMBR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 5726 #define RTC_ALRMBR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 5727 #define RTC_ALRMBR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 5728 #define RTC_ALRMBR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 5729 #define RTC_ALRMBR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 5730 #define RTC_ALRMBR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 5731 #define RTC_ALRMBR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 5732 #define RTC_ALRMBR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 5733 #define RTC_ALRMBR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 5734
<> 144:ef7eb2e8f9f7 5735 /******************** Bits definition for RTC_WPR register ******************/
<> 144:ef7eb2e8f9f7 5736 #define RTC_WPR_KEY 0x000000FFU
<> 144:ef7eb2e8f9f7 5737
<> 144:ef7eb2e8f9f7 5738 /******************** Bits definition for RTC_TSTR register *****************/
<> 144:ef7eb2e8f9f7 5739 #define RTC_TSTR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 5740 #define RTC_TSTR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 5741 #define RTC_TSTR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 5742 #define RTC_TSTR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 5743 #define RTC_TSTR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 5744 #define RTC_TSTR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 5745 #define RTC_TSTR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 5746 #define RTC_TSTR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 5747 #define RTC_TSTR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 5748 #define RTC_TSTR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 5749 #define RTC_TSTR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 5750 #define RTC_TSTR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 5751 #define RTC_TSTR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 5752 #define RTC_TSTR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 5753 #define RTC_TSTR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 5754 #define RTC_TSTR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 5755 #define RTC_TSTR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 5756 #define RTC_TSTR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 5757 #define RTC_TSTR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 5758 #define RTC_TSTR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 5759 #define RTC_TSTR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 5760 #define RTC_TSTR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 5761 #define RTC_TSTR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 5762 #define RTC_TSTR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 5763 #define RTC_TSTR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 5764 #define RTC_TSTR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 5765 #define RTC_TSTR_SU_3 0x00000008U
<> 144:ef7eb2e8f9f7 5766
<> 144:ef7eb2e8f9f7 5767 /******************** Bits definition for RTC_TSDR register *****************/
<> 144:ef7eb2e8f9f7 5768 #define RTC_TSDR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 5769 #define RTC_TSDR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 5770 #define RTC_TSDR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 5771 #define RTC_TSDR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 5772 #define RTC_TSDR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 5773 #define RTC_TSDR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 5774 #define RTC_TSDR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 5775 #define RTC_TSDR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 5776 #define RTC_TSDR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 5777 #define RTC_TSDR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 5778 #define RTC_TSDR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 5779 #define RTC_TSDR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 5780 #define RTC_TSDR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 5781 #define RTC_TSDR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 5782 #define RTC_TSDR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 5783 #define RTC_TSDR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 5784 #define RTC_TSDR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 5785 #define RTC_TSDR_DU_3 0x00000008U
<> 144:ef7eb2e8f9f7 5786
<> 144:ef7eb2e8f9f7 5787 /******************** Bits definition for RTC_TAFCR register ****************/
<> 144:ef7eb2e8f9f7 5788 #define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
<> 144:ef7eb2e8f9f7 5789 #define RTC_TAFCR_TSINSEL 0x00020000U
<> 144:ef7eb2e8f9f7 5790 #define RTC_TAFCR_TAMPINSEL 0x00010000U
<> 144:ef7eb2e8f9f7 5791 #define RTC_TAFCR_TAMPIE 0x00000004U
<> 144:ef7eb2e8f9f7 5792 #define RTC_TAFCR_TAMP1TRG 0x00000002U
<> 144:ef7eb2e8f9f7 5793 #define RTC_TAFCR_TAMP1E 0x00000001U
<> 144:ef7eb2e8f9f7 5794
<> 144:ef7eb2e8f9f7 5795 /******************** Bits definition for RTC_BKP0R register ****************/
<> 144:ef7eb2e8f9f7 5796 #define RTC_BKP0R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5797
<> 144:ef7eb2e8f9f7 5798 /******************** Bits definition for RTC_BKP1R register ****************/
<> 144:ef7eb2e8f9f7 5799 #define RTC_BKP1R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5800
<> 144:ef7eb2e8f9f7 5801 /******************** Bits definition for RTC_BKP2R register ****************/
<> 144:ef7eb2e8f9f7 5802 #define RTC_BKP2R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5803
<> 144:ef7eb2e8f9f7 5804 /******************** Bits definition for RTC_BKP3R register ****************/
<> 144:ef7eb2e8f9f7 5805 #define RTC_BKP3R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5806
<> 144:ef7eb2e8f9f7 5807 /******************** Bits definition for RTC_BKP4R register ****************/
<> 144:ef7eb2e8f9f7 5808 #define RTC_BKP4R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5809
<> 144:ef7eb2e8f9f7 5810 /******************** Bits definition for RTC_BKP5R register ****************/
<> 144:ef7eb2e8f9f7 5811 #define RTC_BKP5R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5812
<> 144:ef7eb2e8f9f7 5813 /******************** Bits definition for RTC_BKP6R register ****************/
<> 144:ef7eb2e8f9f7 5814 #define RTC_BKP6R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5815
<> 144:ef7eb2e8f9f7 5816 /******************** Bits definition for RTC_BKP7R register ****************/
<> 144:ef7eb2e8f9f7 5817 #define RTC_BKP7R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5818
<> 144:ef7eb2e8f9f7 5819 /******************** Bits definition for RTC_BKP8R register ****************/
<> 144:ef7eb2e8f9f7 5820 #define RTC_BKP8R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5821
<> 144:ef7eb2e8f9f7 5822 /******************** Bits definition for RTC_BKP9R register ****************/
<> 144:ef7eb2e8f9f7 5823 #define RTC_BKP9R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5824
<> 144:ef7eb2e8f9f7 5825 /******************** Bits definition for RTC_BKP10R register ***************/
<> 144:ef7eb2e8f9f7 5826 #define RTC_BKP10R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5827
<> 144:ef7eb2e8f9f7 5828 /******************** Bits definition for RTC_BKP11R register ***************/
<> 144:ef7eb2e8f9f7 5829 #define RTC_BKP11R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5830
<> 144:ef7eb2e8f9f7 5831 /******************** Bits definition for RTC_BKP12R register ***************/
<> 144:ef7eb2e8f9f7 5832 #define RTC_BKP12R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5833
<> 144:ef7eb2e8f9f7 5834 /******************** Bits definition for RTC_BKP13R register ***************/
<> 144:ef7eb2e8f9f7 5835 #define RTC_BKP13R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5836
<> 144:ef7eb2e8f9f7 5837 /******************** Bits definition for RTC_BKP14R register ***************/
<> 144:ef7eb2e8f9f7 5838 #define RTC_BKP14R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5839
<> 144:ef7eb2e8f9f7 5840 /******************** Bits definition for RTC_BKP15R register ***************/
<> 144:ef7eb2e8f9f7 5841 #define RTC_BKP15R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5842
<> 144:ef7eb2e8f9f7 5843 /******************** Bits definition for RTC_BKP16R register ***************/
<> 144:ef7eb2e8f9f7 5844 #define RTC_BKP16R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5845
<> 144:ef7eb2e8f9f7 5846 /******************** Bits definition for RTC_BKP17R register ***************/
<> 144:ef7eb2e8f9f7 5847 #define RTC_BKP17R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5848
<> 144:ef7eb2e8f9f7 5849 /******************** Bits definition for RTC_BKP18R register ***************/
<> 144:ef7eb2e8f9f7 5850 #define RTC_BKP18R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5851
<> 144:ef7eb2e8f9f7 5852 /******************** Bits definition for RTC_BKP19R register ***************/
<> 144:ef7eb2e8f9f7 5853 #define RTC_BKP19R 0xFFFFFFFFU
<> 144:ef7eb2e8f9f7 5854
<> 144:ef7eb2e8f9f7 5855
<> 144:ef7eb2e8f9f7 5856
<> 144:ef7eb2e8f9f7 5857 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5858 /* */
<> 144:ef7eb2e8f9f7 5859 /* SD host Interface */
<> 144:ef7eb2e8f9f7 5860 /* */
<> 144:ef7eb2e8f9f7 5861 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5862 /****************** Bit definition for SDIO_POWER register ******************/
<> 144:ef7eb2e8f9f7 5863 #define SDIO_POWER_PWRCTRL 0x00000003U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
<> 144:ef7eb2e8f9f7 5864 #define SDIO_POWER_PWRCTRL_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5865 #define SDIO_POWER_PWRCTRL_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5866
<> 144:ef7eb2e8f9f7 5867 /****************** Bit definition for SDIO_CLKCR register ******************/
<> 144:ef7eb2e8f9f7 5868 #define SDIO_CLKCR_CLKDIV 0x000000FFU /*!<Clock divide factor */
<> 144:ef7eb2e8f9f7 5869 #define SDIO_CLKCR_CLKEN 0x00000100U /*!<Clock enable bit */
<> 144:ef7eb2e8f9f7 5870 #define SDIO_CLKCR_PWRSAV 0x00000200U /*!<Power saving configuration bit */
<> 144:ef7eb2e8f9f7 5871 #define SDIO_CLKCR_BYPASS 0x00000400U /*!<Clock divider bypass enable bit */
<> 144:ef7eb2e8f9f7 5872
<> 144:ef7eb2e8f9f7 5873 #define SDIO_CLKCR_WIDBUS 0x00001800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
<> 144:ef7eb2e8f9f7 5874 #define SDIO_CLKCR_WIDBUS_0 0x00000800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5875 #define SDIO_CLKCR_WIDBUS_1 0x00001000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5876
<> 144:ef7eb2e8f9f7 5877 #define SDIO_CLKCR_NEGEDGE 0x00002000U /*!<SDIO_CK dephasing selection bit */
<> 144:ef7eb2e8f9f7 5878 #define SDIO_CLKCR_HWFC_EN 0x00004000U /*!<HW Flow Control enable */
<> 144:ef7eb2e8f9f7 5879
<> 144:ef7eb2e8f9f7 5880 /******************* Bit definition for SDIO_ARG register *******************/
<> 144:ef7eb2e8f9f7 5881 #define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
<> 144:ef7eb2e8f9f7 5882
<> 144:ef7eb2e8f9f7 5883 /******************* Bit definition for SDIO_CMD register *******************/
<> 144:ef7eb2e8f9f7 5884 #define SDIO_CMD_CMDINDEX 0x0000003FU /*!<Command Index */
<> 144:ef7eb2e8f9f7 5885
<> 144:ef7eb2e8f9f7 5886 #define SDIO_CMD_WAITRESP 0x000000C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
<> 144:ef7eb2e8f9f7 5887 #define SDIO_CMD_WAITRESP_0 0x00000040U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5888 #define SDIO_CMD_WAITRESP_1 0x00000080U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5889
<> 144:ef7eb2e8f9f7 5890 #define SDIO_CMD_WAITINT 0x00000100U /*!<CPSM Waits for Interrupt Request */
<> 144:ef7eb2e8f9f7 5891 #define SDIO_CMD_WAITPEND 0x00000200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
<> 144:ef7eb2e8f9f7 5892 #define SDIO_CMD_CPSMEN 0x00000400U /*!<Command path state machine (CPSM) Enable bit */
<> 144:ef7eb2e8f9f7 5893 #define SDIO_CMD_SDIOSUSPEND 0x00000800U /*!<SD I/O suspend command */
<> 144:ef7eb2e8f9f7 5894 #define SDIO_CMD_ENCMDCOMPL 0x00001000U /*!<Enable CMD completion */
<> 144:ef7eb2e8f9f7 5895 #define SDIO_CMD_NIEN 0x00002000U /*!<Not Interrupt Enable */
<> 144:ef7eb2e8f9f7 5896 #define SDIO_CMD_CEATACMD 0x00004000U /*!<CE-ATA command */
<> 144:ef7eb2e8f9f7 5897
<> 144:ef7eb2e8f9f7 5898 /***************** Bit definition for SDIO_RESPCMD register *****************/
<> 144:ef7eb2e8f9f7 5899 #define SDIO_RESPCMD_RESPCMD 0x0000003FU /*!<Response command index */
<> 144:ef7eb2e8f9f7 5900
<> 144:ef7eb2e8f9f7 5901 /****************** Bit definition for SDIO_RESP0 register ******************/
<> 144:ef7eb2e8f9f7 5902 #define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 5903
<> 144:ef7eb2e8f9f7 5904 /****************** Bit definition for SDIO_RESP1 register ******************/
<> 144:ef7eb2e8f9f7 5905 #define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 5906
<> 144:ef7eb2e8f9f7 5907 /****************** Bit definition for SDIO_RESP2 register ******************/
<> 144:ef7eb2e8f9f7 5908 #define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 5909
<> 144:ef7eb2e8f9f7 5910 /****************** Bit definition for SDIO_RESP3 register ******************/
<> 144:ef7eb2e8f9f7 5911 #define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 5912
<> 144:ef7eb2e8f9f7 5913 /****************** Bit definition for SDIO_RESP4 register ******************/
<> 144:ef7eb2e8f9f7 5914 #define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
<> 144:ef7eb2e8f9f7 5915
<> 144:ef7eb2e8f9f7 5916 /****************** Bit definition for SDIO_DTIMER register *****************/
<> 144:ef7eb2e8f9f7 5917 #define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
<> 144:ef7eb2e8f9f7 5918
<> 144:ef7eb2e8f9f7 5919 /****************** Bit definition for SDIO_DLEN register *******************/
<> 144:ef7eb2e8f9f7 5920 #define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
<> 144:ef7eb2e8f9f7 5921
<> 144:ef7eb2e8f9f7 5922 /****************** Bit definition for SDIO_DCTRL register ******************/
<> 144:ef7eb2e8f9f7 5923 #define SDIO_DCTRL_DTEN 0x00000001U /*!<Data transfer enabled bit */
<> 144:ef7eb2e8f9f7 5924 #define SDIO_DCTRL_DTDIR 0x00000002U /*!<Data transfer direction selection */
<> 144:ef7eb2e8f9f7 5925 #define SDIO_DCTRL_DTMODE 0x00000004U /*!<Data transfer mode selection */
<> 144:ef7eb2e8f9f7 5926 #define SDIO_DCTRL_DMAEN 0x00000008U /*!<DMA enabled bit */
<> 144:ef7eb2e8f9f7 5927
<> 144:ef7eb2e8f9f7 5928 #define SDIO_DCTRL_DBLOCKSIZE 0x000000F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
<> 144:ef7eb2e8f9f7 5929 #define SDIO_DCTRL_DBLOCKSIZE_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5930 #define SDIO_DCTRL_DBLOCKSIZE_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5931 #define SDIO_DCTRL_DBLOCKSIZE_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 5932 #define SDIO_DCTRL_DBLOCKSIZE_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 5933
<> 144:ef7eb2e8f9f7 5934 #define SDIO_DCTRL_RWSTART 0x00000100U /*!<Read wait start */
<> 144:ef7eb2e8f9f7 5935 #define SDIO_DCTRL_RWSTOP 0x00000200U /*!<Read wait stop */
<> 144:ef7eb2e8f9f7 5936 #define SDIO_DCTRL_RWMOD 0x00000400U /*!<Read wait mode */
<> 144:ef7eb2e8f9f7 5937 #define SDIO_DCTRL_SDIOEN 0x00000800U /*!<SD I/O enable functions */
<> 144:ef7eb2e8f9f7 5938
<> 144:ef7eb2e8f9f7 5939 /****************** Bit definition for SDIO_DCOUNT register *****************/
<> 144:ef7eb2e8f9f7 5940 #define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
<> 144:ef7eb2e8f9f7 5941
<> 144:ef7eb2e8f9f7 5942 /****************** Bit definition for SDIO_STA register ********************/
<> 144:ef7eb2e8f9f7 5943 #define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
<> 144:ef7eb2e8f9f7 5944 #define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
<> 144:ef7eb2e8f9f7 5945 #define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
<> 144:ef7eb2e8f9f7 5946 #define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
<> 144:ef7eb2e8f9f7 5947 #define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
<> 144:ef7eb2e8f9f7 5948 #define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
<> 144:ef7eb2e8f9f7 5949 #define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
<> 144:ef7eb2e8f9f7 5950 #define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
<> 144:ef7eb2e8f9f7 5951 #define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
<> 144:ef7eb2e8f9f7 5952 #define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
<> 144:ef7eb2e8f9f7 5953 #define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
<> 144:ef7eb2e8f9f7 5954 #define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
<> 144:ef7eb2e8f9f7 5955 #define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
<> 144:ef7eb2e8f9f7 5956 #define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
<> 144:ef7eb2e8f9f7 5957 #define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
<> 144:ef7eb2e8f9f7 5958 #define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
<> 144:ef7eb2e8f9f7 5959 #define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
<> 144:ef7eb2e8f9f7 5960 #define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
<> 144:ef7eb2e8f9f7 5961 #define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
<> 144:ef7eb2e8f9f7 5962 #define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
<> 144:ef7eb2e8f9f7 5963 #define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
<> 144:ef7eb2e8f9f7 5964 #define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
<> 144:ef7eb2e8f9f7 5965 #define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
<> 144:ef7eb2e8f9f7 5966 #define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
<> 144:ef7eb2e8f9f7 5967
<> 144:ef7eb2e8f9f7 5968 /******************* Bit definition for SDIO_ICR register *******************/
<> 144:ef7eb2e8f9f7 5969 #define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
<> 144:ef7eb2e8f9f7 5970 #define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
<> 144:ef7eb2e8f9f7 5971 #define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
<> 144:ef7eb2e8f9f7 5972 #define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
<> 144:ef7eb2e8f9f7 5973 #define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
<> 144:ef7eb2e8f9f7 5974 #define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
<> 144:ef7eb2e8f9f7 5975 #define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
<> 144:ef7eb2e8f9f7 5976 #define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
<> 144:ef7eb2e8f9f7 5977 #define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
<> 144:ef7eb2e8f9f7 5978 #define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
<> 144:ef7eb2e8f9f7 5979 #define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
<> 144:ef7eb2e8f9f7 5980 #define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
<> 144:ef7eb2e8f9f7 5981 #define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
<> 144:ef7eb2e8f9f7 5982
<> 144:ef7eb2e8f9f7 5983 /****************** Bit definition for SDIO_MASK register *******************/
<> 144:ef7eb2e8f9f7 5984 #define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
<> 144:ef7eb2e8f9f7 5985 #define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
<> 144:ef7eb2e8f9f7 5986 #define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
<> 144:ef7eb2e8f9f7 5987 #define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
<> 144:ef7eb2e8f9f7 5988 #define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 5989 #define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 5990 #define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
<> 144:ef7eb2e8f9f7 5991 #define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
<> 144:ef7eb2e8f9f7 5992 #define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
<> 144:ef7eb2e8f9f7 5993 #define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 5994 #define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
<> 144:ef7eb2e8f9f7 5995 #define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
<> 144:ef7eb2e8f9f7 5996 #define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
<> 144:ef7eb2e8f9f7 5997 #define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
<> 144:ef7eb2e8f9f7 5998 #define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 5999 #define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
<> 144:ef7eb2e8f9f7 6000 #define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
<> 144:ef7eb2e8f9f7 6001 #define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
<> 144:ef7eb2e8f9f7 6002 #define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 6003 #define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 6004 #define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
<> 144:ef7eb2e8f9f7 6005 #define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
<> 144:ef7eb2e8f9f7 6006 #define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
<> 144:ef7eb2e8f9f7 6007 #define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
<> 144:ef7eb2e8f9f7 6008
<> 144:ef7eb2e8f9f7 6009 /***************** Bit definition for SDIO_FIFOCNT register *****************/
<> 144:ef7eb2e8f9f7 6010 #define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
<> 144:ef7eb2e8f9f7 6011
<> 144:ef7eb2e8f9f7 6012 /****************** Bit definition for SDIO_FIFO register *******************/
<> 144:ef7eb2e8f9f7 6013 #define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
<> 144:ef7eb2e8f9f7 6014
<> 144:ef7eb2e8f9f7 6015 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6016 /* */
<> 144:ef7eb2e8f9f7 6017 /* Serial Peripheral Interface */
<> 144:ef7eb2e8f9f7 6018 /* */
<> 144:ef7eb2e8f9f7 6019 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6020 /******************* Bit definition for SPI_CR1 register ********************/
<> 144:ef7eb2e8f9f7 6021 #define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
<> 144:ef7eb2e8f9f7 6022 #define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
<> 144:ef7eb2e8f9f7 6023 #define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
<> 144:ef7eb2e8f9f7 6024
<> 144:ef7eb2e8f9f7 6025 #define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
<> 144:ef7eb2e8f9f7 6026 #define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6027 #define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6028 #define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6029
<> 144:ef7eb2e8f9f7 6030 #define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
<> 144:ef7eb2e8f9f7 6031 #define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
<> 144:ef7eb2e8f9f7 6032 #define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
<> 144:ef7eb2e8f9f7 6033 #define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
<> 144:ef7eb2e8f9f7 6034 #define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
<> 144:ef7eb2e8f9f7 6035 #define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
<> 144:ef7eb2e8f9f7 6036 #define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
<> 144:ef7eb2e8f9f7 6037 #define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
<> 144:ef7eb2e8f9f7 6038 #define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
<> 144:ef7eb2e8f9f7 6039 #define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
<> 144:ef7eb2e8f9f7 6040
<> 144:ef7eb2e8f9f7 6041 /******************* Bit definition for SPI_CR2 register ********************/
<> 144:ef7eb2e8f9f7 6042 #define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 6043 #define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 6044 #define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
<> 144:ef7eb2e8f9f7 6045 #define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
<> 144:ef7eb2e8f9f7 6046 #define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 6047 #define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 6048 #define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 6049
<> 144:ef7eb2e8f9f7 6050 /******************** Bit definition for SPI_SR register ********************/
<> 144:ef7eb2e8f9f7 6051 #define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
<> 144:ef7eb2e8f9f7 6052 #define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
<> 144:ef7eb2e8f9f7 6053 #define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
<> 144:ef7eb2e8f9f7 6054 #define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
<> 144:ef7eb2e8f9f7 6055 #define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
<> 144:ef7eb2e8f9f7 6056 #define SPI_SR_MODF 0x00000020U /*!<Mode fault */
<> 144:ef7eb2e8f9f7 6057 #define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
<> 144:ef7eb2e8f9f7 6058 #define SPI_SR_BSY 0x00000080U /*!<Busy flag */
<> 144:ef7eb2e8f9f7 6059 #define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
<> 144:ef7eb2e8f9f7 6060
<> 144:ef7eb2e8f9f7 6061 /******************** Bit definition for SPI_DR register ********************/
<> 144:ef7eb2e8f9f7 6062 #define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
<> 144:ef7eb2e8f9f7 6063
<> 144:ef7eb2e8f9f7 6064 /******************* Bit definition for SPI_CRCPR register ******************/
<> 144:ef7eb2e8f9f7 6065 #define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
<> 144:ef7eb2e8f9f7 6066
<> 144:ef7eb2e8f9f7 6067 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 144:ef7eb2e8f9f7 6068 #define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
<> 144:ef7eb2e8f9f7 6069
<> 144:ef7eb2e8f9f7 6070 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 144:ef7eb2e8f9f7 6071 #define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
<> 144:ef7eb2e8f9f7 6072
<> 144:ef7eb2e8f9f7 6073 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 144:ef7eb2e8f9f7 6074 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
<> 144:ef7eb2e8f9f7 6075
<> 144:ef7eb2e8f9f7 6076 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 144:ef7eb2e8f9f7 6077 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6078 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6079
<> 144:ef7eb2e8f9f7 6080 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
<> 144:ef7eb2e8f9f7 6081
<> 144:ef7eb2e8f9f7 6082 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 144:ef7eb2e8f9f7 6083 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6084 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6085
<> 144:ef7eb2e8f9f7 6086 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
<> 144:ef7eb2e8f9f7 6087
<> 144:ef7eb2e8f9f7 6088 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 144:ef7eb2e8f9f7 6089 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6090 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6091
<> 144:ef7eb2e8f9f7 6092 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
<> 144:ef7eb2e8f9f7 6093 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
<> 144:ef7eb2e8f9f7 6094
<> 144:ef7eb2e8f9f7 6095 /****************** Bit definition for SPI_I2SPR register *******************/
<> 144:ef7eb2e8f9f7 6096 #define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
<> 144:ef7eb2e8f9f7 6097 #define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
<> 144:ef7eb2e8f9f7 6098 #define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
<> 144:ef7eb2e8f9f7 6099
<> 144:ef7eb2e8f9f7 6100 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6101 /* */
<> 144:ef7eb2e8f9f7 6102 /* SYSCFG */
<> 144:ef7eb2e8f9f7 6103 /* */
<> 144:ef7eb2e8f9f7 6104 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6105 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 144:ef7eb2e8f9f7 6106 #define SYSCFG_MEMRMP_MEM_MODE 0x00000003U /*!<SYSCFG_Memory Remap Config */
<> 144:ef7eb2e8f9f7 6107 #define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
<> 144:ef7eb2e8f9f7 6108 #define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
<> 144:ef7eb2e8f9f7 6109
<> 144:ef7eb2e8f9f7 6110 /****************** Bit definition for SYSCFG_PMC register ******************/
<> 144:ef7eb2e8f9f7 6111 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
<> 144:ef7eb2e8f9f7 6112
<> 144:ef7eb2e8f9f7 6113 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 144:ef7eb2e8f9f7 6114 #define SYSCFG_EXTICR1_EXTI0 0x0000000FU /*!<EXTI 0 configuration */
<> 144:ef7eb2e8f9f7 6115 #define SYSCFG_EXTICR1_EXTI1 0x000000F0U /*!<EXTI 1 configuration */
<> 144:ef7eb2e8f9f7 6116 #define SYSCFG_EXTICR1_EXTI2 0x00000F00U /*!<EXTI 2 configuration */
<> 144:ef7eb2e8f9f7 6117 #define SYSCFG_EXTICR1_EXTI3 0x0000F000U /*!<EXTI 3 configuration */
<> 144:ef7eb2e8f9f7 6118 /**
<> 144:ef7eb2e8f9f7 6119 * @brief EXTI0 configuration
<> 144:ef7eb2e8f9f7 6120 */
<> 144:ef7eb2e8f9f7 6121 #define SYSCFG_EXTICR1_EXTI0_PA 0x00000000U /*!<PA[0] pin */
<> 144:ef7eb2e8f9f7 6122 #define SYSCFG_EXTICR1_EXTI0_PB 0x00000001U /*!<PB[0] pin */
<> 144:ef7eb2e8f9f7 6123 #define SYSCFG_EXTICR1_EXTI0_PC 0x00000002U /*!<PC[0] pin */
<> 144:ef7eb2e8f9f7 6124 #define SYSCFG_EXTICR1_EXTI0_PD 0x00000003U /*!<PD[0] pin */
<> 144:ef7eb2e8f9f7 6125 #define SYSCFG_EXTICR1_EXTI0_PE 0x00000004U /*!<PE[0] pin */
<> 144:ef7eb2e8f9f7 6126 #define SYSCFG_EXTICR1_EXTI0_PF 0x00000005U /*!<PF[0] pin */
<> 144:ef7eb2e8f9f7 6127 #define SYSCFG_EXTICR1_EXTI0_PG 0x00000006U /*!<PG[0] pin */
<> 144:ef7eb2e8f9f7 6128 #define SYSCFG_EXTICR1_EXTI0_PH 0x00000007U /*!<PH[0] pin */
<> 144:ef7eb2e8f9f7 6129 #define SYSCFG_EXTICR1_EXTI0_PI 0x00000008U /*!<PI[0] pin */
<> 144:ef7eb2e8f9f7 6130 /**
<> 144:ef7eb2e8f9f7 6131 * @brief EXTI1 configuration
<> 144:ef7eb2e8f9f7 6132 */
<> 144:ef7eb2e8f9f7 6133 #define SYSCFG_EXTICR1_EXTI1_PA 0x00000000U /*!<PA[1] pin */
<> 144:ef7eb2e8f9f7 6134 #define SYSCFG_EXTICR1_EXTI1_PB 0x00000010U /*!<PB[1] pin */
<> 144:ef7eb2e8f9f7 6135 #define SYSCFG_EXTICR1_EXTI1_PC 0x00000020U /*!<PC[1] pin */
<> 144:ef7eb2e8f9f7 6136 #define SYSCFG_EXTICR1_EXTI1_PD 0x00000030U /*!<PD[1] pin */
<> 144:ef7eb2e8f9f7 6137 #define SYSCFG_EXTICR1_EXTI1_PE 0x00000040U /*!<PE[1] pin */
<> 144:ef7eb2e8f9f7 6138 #define SYSCFG_EXTICR1_EXTI1_PF 0x00000050) /*!<PF[1] pin */
<> 144:ef7eb2e8f9f7 6139 #define SYSCFG_EXTICR1_EXTI1_PG 0x00000060U /*!<PG[1] pin */
<> 144:ef7eb2e8f9f7 6140 #define SYSCFG_EXTICR1_EXTI1_PH 0x00000070U /*!<PH[1] pin */
<> 144:ef7eb2e8f9f7 6141 #define SYSCFG_EXTICR1_EXTI1_PI 0x00000080U /*!<PI[1] pin */
<> 144:ef7eb2e8f9f7 6142 /**
<> 144:ef7eb2e8f9f7 6143 * @brief EXTI2 configuration
<> 144:ef7eb2e8f9f7 6144 */
<> 144:ef7eb2e8f9f7 6145 #define SYSCFG_EXTICR1_EXTI2_PA 0x00000000U /*!<PA[2] pin */
<> 144:ef7eb2e8f9f7 6146 #define SYSCFG_EXTICR1_EXTI2_PB 0x00000100U /*!<PB[2] pin */
<> 144:ef7eb2e8f9f7 6147 #define SYSCFG_EXTICR1_EXTI2_PC 0x00000200U /*!<PC[2] pin */
<> 144:ef7eb2e8f9f7 6148 #define SYSCFG_EXTICR1_EXTI2_PD 0x00000300U /*!<PD[2] pin */
<> 144:ef7eb2e8f9f7 6149 #define SYSCFG_EXTICR1_EXTI2_PE 0x00000400U /*!<PE[2] pin */
<> 144:ef7eb2e8f9f7 6150 #define SYSCFG_EXTICR1_EXTI2_PF 0x00000500) /*!<PF[2] pin */
<> 144:ef7eb2e8f9f7 6151 #define SYSCFG_EXTICR1_EXTI2_PG 0x00000600) /*!<PG[2] pin */
<> 144:ef7eb2e8f9f7 6152 #define SYSCFG_EXTICR1_EXTI2_PH 0x00000700U /*!<PH[2] pin */
<> 144:ef7eb2e8f9f7 6153 #define SYSCFG_EXTICR1_EXTI2_PI 0x00000800U /*!<PI[2] pin */
<> 144:ef7eb2e8f9f7 6154 /**
<> 144:ef7eb2e8f9f7 6155 * @brief EXTI3 configuration
<> 144:ef7eb2e8f9f7 6156 */
<> 144:ef7eb2e8f9f7 6157 #define SYSCFG_EXTICR1_EXTI3_PA 0x00000000U /*!<PA[3] pin */
<> 144:ef7eb2e8f9f7 6158 #define SYSCFG_EXTICR1_EXTI3_PB 0x00001000U /*!<PB[3] pin */
<> 144:ef7eb2e8f9f7 6159 #define SYSCFG_EXTICR1_EXTI3_PC 0x00002000U /*!<PC[3] pin */
<> 144:ef7eb2e8f9f7 6160 #define SYSCFG_EXTICR1_EXTI3_PD 0x00003000U /*!<PD[3] pin */
<> 144:ef7eb2e8f9f7 6161 #define SYSCFG_EXTICR1_EXTI3_PE 0x00004000U /*!<PE[3] pin */
<> 144:ef7eb2e8f9f7 6162 #define SYSCFG_EXTICR1_EXTI3_PF 0x00005000) /*!<PF[3] pin */
<> 144:ef7eb2e8f9f7 6163 #define SYSCFG_EXTICR1_EXTI3_PG 0x00006000U /*!<PG[3] pin */
<> 144:ef7eb2e8f9f7 6164 #define SYSCFG_EXTICR1_EXTI3_PH 0x00007000U /*!<PH[3] pin */
<> 144:ef7eb2e8f9f7 6165 #define SYSCFG_EXTICR1_EXTI3_PI 0x00008000U /*!<PI[3] pin */
<> 144:ef7eb2e8f9f7 6166
<> 144:ef7eb2e8f9f7 6167 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 144:ef7eb2e8f9f7 6168 #define SYSCFG_EXTICR2_EXTI4 0x0000000FU /*!<EXTI 4 configuration */
<> 144:ef7eb2e8f9f7 6169 #define SYSCFG_EXTICR2_EXTI5 0x000000F0U /*!<EXTI 5 configuration */
<> 144:ef7eb2e8f9f7 6170 #define SYSCFG_EXTICR2_EXTI6 0x00000F00U /*!<EXTI 6 configuration */
<> 144:ef7eb2e8f9f7 6171 #define SYSCFG_EXTICR2_EXTI7 0x0000F000U /*!<EXTI 7 configuration */
<> 144:ef7eb2e8f9f7 6172 /**
<> 144:ef7eb2e8f9f7 6173 * @brief EXTI4 configuration
<> 144:ef7eb2e8f9f7 6174 */
<> 144:ef7eb2e8f9f7 6175 #define SYSCFG_EXTICR2_EXTI4_PA 0x00000000U /*!<PA[4] pin */
<> 144:ef7eb2e8f9f7 6176 #define SYSCFG_EXTICR2_EXTI4_PB 0x00000001U /*!<PB[4] pin */
<> 144:ef7eb2e8f9f7 6177 #define SYSCFG_EXTICR2_EXTI4_PC 0x00000002U /*!<PC[4] pin */
<> 144:ef7eb2e8f9f7 6178 #define SYSCFG_EXTICR2_EXTI4_PD 0x00000003U /*!<PD[4] pin */
<> 144:ef7eb2e8f9f7 6179 #define SYSCFG_EXTICR2_EXTI4_PE 0x00000004U /*!<PE[4] pin */
<> 144:ef7eb2e8f9f7 6180 #define SYSCFG_EXTICR2_EXTI4_PF 0x00000005U /*!<PF[4] pin */
<> 144:ef7eb2e8f9f7 6181 #define SYSCFG_EXTICR2_EXTI4_PG 0x00000006U /*!<PG[4] pin */
<> 144:ef7eb2e8f9f7 6182 #define SYSCFG_EXTICR2_EXTI4_PH 0x00000007U /*!<PH[4] pin */
<> 144:ef7eb2e8f9f7 6183 #define SYSCFG_EXTICR2_EXTI4_PI 0x00000008U /*!<PI[4] pin */
<> 144:ef7eb2e8f9f7 6184 /**
<> 144:ef7eb2e8f9f7 6185 * @brief EXTI5 configuration
<> 144:ef7eb2e8f9f7 6186 */
<> 144:ef7eb2e8f9f7 6187 #define SYSCFG_EXTICR2_EXTI5_PA 0x00000000U /*!<PA[5] pin */
<> 144:ef7eb2e8f9f7 6188 #define SYSCFG_EXTICR2_EXTI5_PB 0x00000010U /*!<PB[5] pin */
<> 144:ef7eb2e8f9f7 6189 #define SYSCFG_EXTICR2_EXTI5_PC 0x00000020U /*!<PC[5] pin */
<> 144:ef7eb2e8f9f7 6190 #define SYSCFG_EXTICR2_EXTI5_PD 0x00000030U /*!<PD[5] pin */
<> 144:ef7eb2e8f9f7 6191 #define SYSCFG_EXTICR2_EXTI5_PE 0x00000040U /*!<PE[5] pin */
<> 144:ef7eb2e8f9f7 6192 #define SYSCFG_EXTICR2_EXTI5_PF 0x00000050) /*!<PF[5] pin */
<> 144:ef7eb2e8f9f7 6193 #define SYSCFG_EXTICR2_EXTI5_PG 0x00000060U /*!<PG[5] pin */
<> 144:ef7eb2e8f9f7 6194 #define SYSCFG_EXTICR2_EXTI5_PH 0x00000070U /*!<PH[5] pin */
<> 144:ef7eb2e8f9f7 6195 #define SYSCFG_EXTICR2_EXTI5_PI 0x00000080U /*!<PI[5] pin */
<> 144:ef7eb2e8f9f7 6196 /**
<> 144:ef7eb2e8f9f7 6197 * @brief EXTI6 configuration
<> 144:ef7eb2e8f9f7 6198 */
<> 144:ef7eb2e8f9f7 6199 #define SYSCFG_EXTICR2_EXTI6_PA 0x00000000U /*!<PA[6] pin */
<> 144:ef7eb2e8f9f7 6200 #define SYSCFG_EXTICR2_EXTI6_PB 0x00000100U /*!<PB[6] pin */
<> 144:ef7eb2e8f9f7 6201 #define SYSCFG_EXTICR2_EXTI6_PC 0x00000200U /*!<PC[6] pin */
<> 144:ef7eb2e8f9f7 6202 #define SYSCFG_EXTICR2_EXTI6_PD 0x00000300U /*!<PD[6] pin */
<> 144:ef7eb2e8f9f7 6203 #define SYSCFG_EXTICR2_EXTI6_PE 0x00000400U /*!<PE[6] pin */
<> 144:ef7eb2e8f9f7 6204 #define SYSCFG_EXTICR2_EXTI6_PF 0x00000500) /*!<PF[6] pin */
<> 144:ef7eb2e8f9f7 6205 #define SYSCFG_EXTICR2_EXTI6_PG 0x00000600) /*!<PG[6] pin */
<> 144:ef7eb2e8f9f7 6206 #define SYSCFG_EXTICR2_EXTI6_PH 0x00000700U /*!<PH[6] pin */
<> 144:ef7eb2e8f9f7 6207 #define SYSCFG_EXTICR2_EXTI6_PI 0x00000800U /*!<PI[6] pin */
<> 144:ef7eb2e8f9f7 6208 /**
<> 144:ef7eb2e8f9f7 6209 * @brief EXTI7 configuration
<> 144:ef7eb2e8f9f7 6210 */
<> 144:ef7eb2e8f9f7 6211 #define SYSCFG_EXTICR2_EXTI7_PA 0x00000000U /*!<PA[7] pin */
<> 144:ef7eb2e8f9f7 6212 #define SYSCFG_EXTICR2_EXTI7_PB 0x00001000U /*!<PB[7] pin */
<> 144:ef7eb2e8f9f7 6213 #define SYSCFG_EXTICR2_EXTI7_PC 0x00002000U /*!<PC[7] pin */
<> 144:ef7eb2e8f9f7 6214 #define SYSCFG_EXTICR2_EXTI7_PD 0x00003000U /*!<PD[7] pin */
<> 144:ef7eb2e8f9f7 6215 #define SYSCFG_EXTICR2_EXTI7_PE 0x00004000U /*!<PE[7] pin */
<> 144:ef7eb2e8f9f7 6216 #define SYSCFG_EXTICR2_EXTI7_PF 0x00005000) /*!<PF[7] pin */
<> 144:ef7eb2e8f9f7 6217 #define SYSCFG_EXTICR2_EXTI7_PG 0x00006000U /*!<PG[7] pin */
<> 144:ef7eb2e8f9f7 6218 #define SYSCFG_EXTICR2_EXTI7_PH 0x00007000U /*!<PH[7] pin */
<> 144:ef7eb2e8f9f7 6219 #define SYSCFG_EXTICR2_EXTI7_PI 0x00008000U /*!<PI[7] pin */
<> 144:ef7eb2e8f9f7 6220
<> 144:ef7eb2e8f9f7 6221 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 144:ef7eb2e8f9f7 6222 #define SYSCFG_EXTICR3_EXTI8 0x0000000FU /*!<EXTI 8 configuration */
<> 144:ef7eb2e8f9f7 6223 #define SYSCFG_EXTICR3_EXTI9 0x000000F0U /*!<EXTI 9 configuration */
<> 144:ef7eb2e8f9f7 6224 #define SYSCFG_EXTICR3_EXTI10 0x00000F00U /*!<EXTI 10 configuration */
<> 144:ef7eb2e8f9f7 6225 #define SYSCFG_EXTICR3_EXTI11 0x0000F000U /*!<EXTI 11 configuration */
<> 144:ef7eb2e8f9f7 6226
<> 144:ef7eb2e8f9f7 6227 /**
<> 144:ef7eb2e8f9f7 6228 * @brief EXTI8 configuration
<> 144:ef7eb2e8f9f7 6229 */
<> 144:ef7eb2e8f9f7 6230 #define SYSCFG_EXTICR3_EXTI8_PA 0x00000000U /*!<PA[8] pin */
<> 144:ef7eb2e8f9f7 6231 #define SYSCFG_EXTICR3_EXTI8_PB 0x00000001U /*!<PB[8] pin */
<> 144:ef7eb2e8f9f7 6232 #define SYSCFG_EXTICR3_EXTI8_PC 0x00000002U /*!<PC[8] pin */
<> 144:ef7eb2e8f9f7 6233 #define SYSCFG_EXTICR3_EXTI8_PD 0x00000003U /*!<PD[8] pin */
<> 144:ef7eb2e8f9f7 6234 #define SYSCFG_EXTICR3_EXTI8_PE 0x00000004U /*!<PE[8] pin */
<> 144:ef7eb2e8f9f7 6235 #define SYSCFG_EXTICR3_EXTI8_PF 0x00000005U /*!<PF[8] pin */
<> 144:ef7eb2e8f9f7 6236 #define SYSCFG_EXTICR3_EXTI8_PG 0x00000006U /*!<PG[8] pin */
<> 144:ef7eb2e8f9f7 6237 #define SYSCFG_EXTICR3_EXTI8_PH 0x00000007U /*!<PH[8] pin */
<> 144:ef7eb2e8f9f7 6238 #define SYSCFG_EXTICR3_EXTI8_PI 0x00000008U /*!<PI[8] pin */
<> 144:ef7eb2e8f9f7 6239 /**
<> 144:ef7eb2e8f9f7 6240 * @brief EXTI9 configuration
<> 144:ef7eb2e8f9f7 6241 */
<> 144:ef7eb2e8f9f7 6242 #define SYSCFG_EXTICR3_EXTI9_PA 0x00000000U /*!<PA[9] pin */
<> 144:ef7eb2e8f9f7 6243 #define SYSCFG_EXTICR3_EXTI9_PB 0x00000010U /*!<PB[9] pin */
<> 144:ef7eb2e8f9f7 6244 #define SYSCFG_EXTICR3_EXTI9_PC 0x00000020U /*!<PC[9] pin */
<> 144:ef7eb2e8f9f7 6245 #define SYSCFG_EXTICR3_EXTI9_PD 0x00000030U /*!<PD[9] pin */
<> 144:ef7eb2e8f9f7 6246 #define SYSCFG_EXTICR3_EXTI9_PE 0x00000040U /*!<PE[9] pin */
<> 144:ef7eb2e8f9f7 6247 #define SYSCFG_EXTICR3_EXTI9_PF 0x00000050) /*!<PF[9] pin */
<> 144:ef7eb2e8f9f7 6248 #define SYSCFG_EXTICR3_EXTI9_PG 0x00000060U /*!<PG[9] pin */
<> 144:ef7eb2e8f9f7 6249 #define SYSCFG_EXTICR3_EXTI9_PH 0x00000070U /*!<PH[9] pin */
<> 144:ef7eb2e8f9f7 6250 #define SYSCFG_EXTICR3_EXTI9_PI 0x00000080U /*!<PI[9] pin */
<> 144:ef7eb2e8f9f7 6251 /**
<> 144:ef7eb2e8f9f7 6252 * @brief EXTI10 configuration
<> 144:ef7eb2e8f9f7 6253 */
<> 144:ef7eb2e8f9f7 6254 #define SYSCFG_EXTICR3_EXTI10_PA 0x00000000U /*!<PA[10] pin */
<> 144:ef7eb2e8f9f7 6255 #define SYSCFG_EXTICR3_EXTI10_PB 0x00000100U /*!<PB[10] pin */
<> 144:ef7eb2e8f9f7 6256 #define SYSCFG_EXTICR3_EXTI10_PC 0x00000200U /*!<PC[10] pin */
<> 144:ef7eb2e8f9f7 6257 #define SYSCFG_EXTICR3_EXTI10_PD 0x00000300U /*!<PD[10] pin */
<> 144:ef7eb2e8f9f7 6258 #define SYSCFG_EXTICR3_EXTI10_PE 0x00000400U /*!<PE[10] pin */
<> 144:ef7eb2e8f9f7 6259 #define SYSCFG_EXTICR3_EXTI10_PF 0x00000500) /*!<PF[10] pin */
<> 144:ef7eb2e8f9f7 6260 #define SYSCFG_EXTICR3_EXTI10_PG 0x00000600) /*!<PG[10] pin */
<> 144:ef7eb2e8f9f7 6261 #define SYSCFG_EXTICR3_EXTI10_PH 0x00000700U /*!<PH[10] pin */
<> 144:ef7eb2e8f9f7 6262 #define SYSCFG_EXTICR3_EXTI10_PI 0x00000800U /*!<PI[10] pin */
<> 144:ef7eb2e8f9f7 6263 /**
<> 144:ef7eb2e8f9f7 6264 * @brief EXTI11 configuration
<> 144:ef7eb2e8f9f7 6265 */
<> 144:ef7eb2e8f9f7 6266 #define SYSCFG_EXTICR3_EXTI11_PA 0x00000000U /*!<PA[11] pin */
<> 144:ef7eb2e8f9f7 6267 #define SYSCFG_EXTICR3_EXTI11_PB 0x00001000U /*!<PB[11] pin */
<> 144:ef7eb2e8f9f7 6268 #define SYSCFG_EXTICR3_EXTI11_PC 0x00002000U /*!<PC[11] pin */
<> 144:ef7eb2e8f9f7 6269 #define SYSCFG_EXTICR3_EXTI11_PD 0x00003000U /*!<PD[11] pin */
<> 144:ef7eb2e8f9f7 6270 #define SYSCFG_EXTICR3_EXTI11_PE 0x00004000U /*!<PE[11] pin */
<> 144:ef7eb2e8f9f7 6271 #define SYSCFG_EXTICR3_EXTI11_PF 0x00005000) /*!<PF[11] pin */
<> 144:ef7eb2e8f9f7 6272 #define SYSCFG_EXTICR3_EXTI11_PG 0x00006000U /*!<PG[11] pin */
<> 144:ef7eb2e8f9f7 6273 #define SYSCFG_EXTICR3_EXTI11_PH 0x00007000U /*!<PH[11] pin */
<> 144:ef7eb2e8f9f7 6274 #define SYSCFG_EXTICR3_EXTI11_PI 0x00008000U /*!<PI[11] pin */
<> 144:ef7eb2e8f9f7 6275
<> 144:ef7eb2e8f9f7 6276 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 144:ef7eb2e8f9f7 6277 #define SYSCFG_EXTICR4_EXTI12 0x0000000FU /*!<EXTI 12 configuration */
<> 144:ef7eb2e8f9f7 6278 #define SYSCFG_EXTICR4_EXTI13 0x000000F0U /*!<EXTI 13 configuration */
<> 144:ef7eb2e8f9f7 6279 #define SYSCFG_EXTICR4_EXTI14 0x00000F00U /*!<EXTI 14 configuration */
<> 144:ef7eb2e8f9f7 6280 #define SYSCFG_EXTICR4_EXTI15 0x0000F000U /*!<EXTI 15 configuration */
<> 144:ef7eb2e8f9f7 6281 /**
<> 144:ef7eb2e8f9f7 6282 * @brief EXTI12 configuration
<> 144:ef7eb2e8f9f7 6283 */
<> 144:ef7eb2e8f9f7 6284 #define SYSCFG_EXTICR4_EXTI12_PA 0x00000000U /*!<PA[12] pin */
<> 144:ef7eb2e8f9f7 6285 #define SYSCFG_EXTICR4_EXTI12_PB 0x00000001U /*!<PB[12] pin */
<> 144:ef7eb2e8f9f7 6286 #define SYSCFG_EXTICR4_EXTI12_PC 0x00000002U /*!<PC[12] pin */
<> 144:ef7eb2e8f9f7 6287 #define SYSCFG_EXTICR4_EXTI12_PD 0x00000003U /*!<PD[12] pin */
<> 144:ef7eb2e8f9f7 6288 #define SYSCFG_EXTICR4_EXTI12_PE 0x00000004U /*!<PE[12] pin */
<> 144:ef7eb2e8f9f7 6289 #define SYSCFG_EXTICR4_EXTI12_PF 0x00000005U /*!<PF[12] pin */
<> 144:ef7eb2e8f9f7 6290 #define SYSCFG_EXTICR4_EXTI12_PG 0x00000006U /*!<PG[12] pin */
<> 144:ef7eb2e8f9f7 6291 #define SYSCFG_EXTICR3_EXTI12_PH 0x00000007U /*!<PH[12] pin */
<> 144:ef7eb2e8f9f7 6292 /**
<> 144:ef7eb2e8f9f7 6293 * @brief EXTI13 configuration
<> 144:ef7eb2e8f9f7 6294 */
<> 144:ef7eb2e8f9f7 6295 #define SYSCFG_EXTICR4_EXTI13_PA 0x00000000U /*!<PA[13] pin */
<> 144:ef7eb2e8f9f7 6296 #define SYSCFG_EXTICR4_EXTI13_PB 0x00000010U /*!<PB[13] pin */
<> 144:ef7eb2e8f9f7 6297 #define SYSCFG_EXTICR4_EXTI13_PC 0x00000020U /*!<PC[13] pin */
<> 144:ef7eb2e8f9f7 6298 #define SYSCFG_EXTICR4_EXTI13_PD 0x00000030U /*!<PD[13] pin */
<> 144:ef7eb2e8f9f7 6299 #define SYSCFG_EXTICR4_EXTI13_PE 0x00000040U /*!<PE[13] pin */
<> 144:ef7eb2e8f9f7 6300 #define SYSCFG_EXTICR4_EXTI13_PF 0x00000050) /*!<PF[13] pin */
<> 144:ef7eb2e8f9f7 6301 #define SYSCFG_EXTICR4_EXTI13_PG 0x00000060U /*!<PG[13] pin */
<> 144:ef7eb2e8f9f7 6302 #define SYSCFG_EXTICR3_EXTI13_PH 0x00000070U /*!<PH[13] pin */
<> 144:ef7eb2e8f9f7 6303 /**
<> 144:ef7eb2e8f9f7 6304 * @brief EXTI14 configuration
<> 144:ef7eb2e8f9f7 6305 */
<> 144:ef7eb2e8f9f7 6306 #define SYSCFG_EXTICR4_EXTI14_PA 0x00000000U /*!<PA[14] pin */
<> 144:ef7eb2e8f9f7 6307 #define SYSCFG_EXTICR4_EXTI14_PB 0x00000100U /*!<PB[14] pin */
<> 144:ef7eb2e8f9f7 6308 #define SYSCFG_EXTICR4_EXTI14_PC 0x00000200U /*!<PC[14] pin */
<> 144:ef7eb2e8f9f7 6309 #define SYSCFG_EXTICR4_EXTI14_PD 0x00000300U /*!<PD[14] pin */
<> 144:ef7eb2e8f9f7 6310 #define SYSCFG_EXTICR4_EXTI14_PE 0x00000400U /*!<PE[14] pin */
<> 144:ef7eb2e8f9f7 6311 #define SYSCFG_EXTICR4_EXTI14_PF 0x00000500) /*!<PF[14] pin */
<> 144:ef7eb2e8f9f7 6312 #define SYSCFG_EXTICR4_EXTI14_PG 0x00000600) /*!<PG[14] pin */
<> 144:ef7eb2e8f9f7 6313 #define SYSCFG_EXTICR3_EXTI14_PH 0x00000700U /*!<PH[14] pin */
<> 144:ef7eb2e8f9f7 6314 /**
<> 144:ef7eb2e8f9f7 6315 * @brief EXTI15 configuration
<> 144:ef7eb2e8f9f7 6316 */
<> 144:ef7eb2e8f9f7 6317 #define SYSCFG_EXTICR4_EXTI15_PA 0x00000000U /*!<PA[15] pin */
<> 144:ef7eb2e8f9f7 6318 #define SYSCFG_EXTICR4_EXTI15_PB 0x00001000U /*!<PB[15] pin */
<> 144:ef7eb2e8f9f7 6319 #define SYSCFG_EXTICR4_EXTI15_PC 0x00002000U /*!<PC[15] pin */
<> 144:ef7eb2e8f9f7 6320 #define SYSCFG_EXTICR4_EXTI15_PD 0x00003000U /*!<PD[15] pin */
<> 144:ef7eb2e8f9f7 6321 #define SYSCFG_EXTICR4_EXTI15_PE 0x00004000U /*!<PE[15] pin */
<> 144:ef7eb2e8f9f7 6322 #define SYSCFG_EXTICR4_EXTI15_PF 0x00005000) /*!<PF[15] pin */
<> 144:ef7eb2e8f9f7 6323 #define SYSCFG_EXTICR4_EXTI15_PG 0x00006000U /*!<PG[15] pin */
<> 144:ef7eb2e8f9f7 6324 #define SYSCFG_EXTICR3_EXTI15_PH 0x00007000U /*!<PH[15] pin */
<> 144:ef7eb2e8f9f7 6325
<> 144:ef7eb2e8f9f7 6326 /****************** Bit definition for SYSCFG_CMPCR register ****************/
<> 144:ef7eb2e8f9f7 6327 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
<> 144:ef7eb2e8f9f7 6328 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
<> 144:ef7eb2e8f9f7 6329
<> 144:ef7eb2e8f9f7 6330 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6331 /* */
<> 144:ef7eb2e8f9f7 6332 /* TIM */
<> 144:ef7eb2e8f9f7 6333 /* */
<> 144:ef7eb2e8f9f7 6334 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6335 /******************* Bit definition for TIM_CR1 register ********************/
<> 144:ef7eb2e8f9f7 6336 #define TIM_CR1_CEN 0x00000001U /*!<Counter enable */
<> 144:ef7eb2e8f9f7 6337 #define TIM_CR1_UDIS 0x00000002U /*!<Update disable */
<> 144:ef7eb2e8f9f7 6338 #define TIM_CR1_URS 0x00000004U /*!<Update request source */
<> 144:ef7eb2e8f9f7 6339 #define TIM_CR1_OPM 0x00000008U /*!<One pulse mode */
<> 144:ef7eb2e8f9f7 6340 #define TIM_CR1_DIR 0x00000010U /*!<Direction */
<> 144:ef7eb2e8f9f7 6341
<> 144:ef7eb2e8f9f7 6342 #define TIM_CR1_CMS 0x00000060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 144:ef7eb2e8f9f7 6343 #define TIM_CR1_CMS_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6344 #define TIM_CR1_CMS_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6345
<> 144:ef7eb2e8f9f7 6346 #define TIM_CR1_ARPE 0x00000080U /*!<Auto-reload preload enable */
<> 144:ef7eb2e8f9f7 6347
<> 144:ef7eb2e8f9f7 6348 #define TIM_CR1_CKD 0x00000300U /*!<CKD[1:0] bits (clock division) */
<> 144:ef7eb2e8f9f7 6349 #define TIM_CR1_CKD_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6350 #define TIM_CR1_CKD_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6351
<> 144:ef7eb2e8f9f7 6352 /******************* Bit definition for TIM_CR2 register ********************/
<> 144:ef7eb2e8f9f7 6353 #define TIM_CR2_CCPC 0x00000001U /*!<Capture/Compare Preloaded Control */
<> 144:ef7eb2e8f9f7 6354 #define TIM_CR2_CCUS 0x00000004U /*!<Capture/Compare Control Update Selection */
<> 144:ef7eb2e8f9f7 6355 #define TIM_CR2_CCDS 0x00000008U /*!<Capture/Compare DMA Selection */
<> 144:ef7eb2e8f9f7 6356
<> 144:ef7eb2e8f9f7 6357 #define TIM_CR2_MMS 0x00000070U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 144:ef7eb2e8f9f7 6358 #define TIM_CR2_MMS_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6359 #define TIM_CR2_MMS_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6360 #define TIM_CR2_MMS_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6361
<> 144:ef7eb2e8f9f7 6362 #define TIM_CR2_TI1S 0x00000080U /*!<TI1 Selection */
<> 144:ef7eb2e8f9f7 6363 #define TIM_CR2_OIS1 0x00000100U /*!<Output Idle state 1 (OC1 output) */
<> 144:ef7eb2e8f9f7 6364 #define TIM_CR2_OIS1N 0x00000200U /*!<Output Idle state 1 (OC1N output) */
<> 144:ef7eb2e8f9f7 6365 #define TIM_CR2_OIS2 0x00000400U /*!<Output Idle state 2 (OC2 output) */
<> 144:ef7eb2e8f9f7 6366 #define TIM_CR2_OIS2N 0x00000800U /*!<Output Idle state 2 (OC2N output) */
<> 144:ef7eb2e8f9f7 6367 #define TIM_CR2_OIS3 0x00001000U /*!<Output Idle state 3 (OC3 output) */
<> 144:ef7eb2e8f9f7 6368 #define TIM_CR2_OIS3N 0x00002000U /*!<Output Idle state 3 (OC3N output) */
<> 144:ef7eb2e8f9f7 6369 #define TIM_CR2_OIS4 0x00004000U /*!<Output Idle state 4 (OC4 output) */
<> 144:ef7eb2e8f9f7 6370
<> 144:ef7eb2e8f9f7 6371 /******************* Bit definition for TIM_SMCR register *******************/
<> 144:ef7eb2e8f9f7 6372 #define TIM_SMCR_SMS 0x00000007U /*!<SMS[2:0] bits (Slave mode selection) */
<> 144:ef7eb2e8f9f7 6373 #define TIM_SMCR_SMS_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6374 #define TIM_SMCR_SMS_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6375 #define TIM_SMCR_SMS_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6376
<> 144:ef7eb2e8f9f7 6377 #define TIM_SMCR_TS 0x00000070U /*!<TS[2:0] bits (Trigger selection) */
<> 144:ef7eb2e8f9f7 6378 #define TIM_SMCR_TS_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6379 #define TIM_SMCR_TS_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6380 #define TIM_SMCR_TS_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6381
<> 144:ef7eb2e8f9f7 6382 #define TIM_SMCR_MSM 0x00000080U /*!<Master/slave mode */
<> 144:ef7eb2e8f9f7 6383
<> 144:ef7eb2e8f9f7 6384 #define TIM_SMCR_ETF 0x00000F00U /*!<ETF[3:0] bits (External trigger filter) */
<> 144:ef7eb2e8f9f7 6385 #define TIM_SMCR_ETF_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6386 #define TIM_SMCR_ETF_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6387 #define TIM_SMCR_ETF_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6388 #define TIM_SMCR_ETF_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6389
<> 144:ef7eb2e8f9f7 6390 #define TIM_SMCR_ETPS 0x00003000U /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 144:ef7eb2e8f9f7 6391 #define TIM_SMCR_ETPS_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6392 #define TIM_SMCR_ETPS_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6393
<> 144:ef7eb2e8f9f7 6394 #define TIM_SMCR_ECE 0x00004000U /*!<External clock enable */
<> 144:ef7eb2e8f9f7 6395 #define TIM_SMCR_ETP 0x00008000U /*!<External trigger polarity */
<> 144:ef7eb2e8f9f7 6396
<> 144:ef7eb2e8f9f7 6397 /******************* Bit definition for TIM_DIER register *******************/
<> 144:ef7eb2e8f9f7 6398 #define TIM_DIER_UIE 0x00000001U /*!<Update interrupt enable */
<> 144:ef7eb2e8f9f7 6399 #define TIM_DIER_CC1IE 0x00000002U /*!<Capture/Compare 1 interrupt enable */
<> 144:ef7eb2e8f9f7 6400 #define TIM_DIER_CC2IE 0x00000004U /*!<Capture/Compare 2 interrupt enable */
<> 144:ef7eb2e8f9f7 6401 #define TIM_DIER_CC3IE 0x00000008U /*!<Capture/Compare 3 interrupt enable */
<> 144:ef7eb2e8f9f7 6402 #define TIM_DIER_CC4IE 0x00000010U /*!<Capture/Compare 4 interrupt enable */
<> 144:ef7eb2e8f9f7 6403 #define TIM_DIER_COMIE 0x00000020U /*!<COM interrupt enable */
<> 144:ef7eb2e8f9f7 6404 #define TIM_DIER_TIE 0x00000040U /*!<Trigger interrupt enable */
<> 144:ef7eb2e8f9f7 6405 #define TIM_DIER_BIE 0x00000080U /*!<Break interrupt enable */
<> 144:ef7eb2e8f9f7 6406 #define TIM_DIER_UDE 0x00000100U /*!<Update DMA request enable */
<> 144:ef7eb2e8f9f7 6407 #define TIM_DIER_CC1DE 0x00000200U /*!<Capture/Compare 1 DMA request enable */
<> 144:ef7eb2e8f9f7 6408 #define TIM_DIER_CC2DE 0x00000400U /*!<Capture/Compare 2 DMA request enable */
<> 144:ef7eb2e8f9f7 6409 #define TIM_DIER_CC3DE 0x00000800U /*!<Capture/Compare 3 DMA request enable */
<> 144:ef7eb2e8f9f7 6410 #define TIM_DIER_CC4DE 0x00001000U /*!<Capture/Compare 4 DMA request enable */
<> 144:ef7eb2e8f9f7 6411 #define TIM_DIER_COMDE 0x00002000U /*!<COM DMA request enable */
<> 144:ef7eb2e8f9f7 6412 #define TIM_DIER_TDE 0x00004000U /*!<Trigger DMA request enable */
<> 144:ef7eb2e8f9f7 6413
<> 144:ef7eb2e8f9f7 6414 /******************** Bit definition for TIM_SR register ********************/
<> 144:ef7eb2e8f9f7 6415 #define TIM_SR_UIF 0x00000001U /*!<Update interrupt Flag */
<> 144:ef7eb2e8f9f7 6416 #define TIM_SR_CC1IF 0x00000002U /*!<Capture/Compare 1 interrupt Flag */
<> 144:ef7eb2e8f9f7 6417 #define TIM_SR_CC2IF 0x00000004U /*!<Capture/Compare 2 interrupt Flag */
<> 144:ef7eb2e8f9f7 6418 #define TIM_SR_CC3IF 0x00000008U /*!<Capture/Compare 3 interrupt Flag */
<> 144:ef7eb2e8f9f7 6419 #define TIM_SR_CC4IF 0x00000010U /*!<Capture/Compare 4 interrupt Flag */
<> 144:ef7eb2e8f9f7 6420 #define TIM_SR_COMIF 0x00000020U /*!<COM interrupt Flag */
<> 144:ef7eb2e8f9f7 6421 #define TIM_SR_TIF 0x00000040U /*!<Trigger interrupt Flag */
<> 144:ef7eb2e8f9f7 6422 #define TIM_SR_BIF 0x00000080U /*!<Break interrupt Flag */
<> 144:ef7eb2e8f9f7 6423 #define TIM_SR_CC1OF 0x00000200U /*!<Capture/Compare 1 Overcapture Flag */
<> 144:ef7eb2e8f9f7 6424 #define TIM_SR_CC2OF 0x00000400U /*!<Capture/Compare 2 Overcapture Flag */
<> 144:ef7eb2e8f9f7 6425 #define TIM_SR_CC3OF 0x00000800U /*!<Capture/Compare 3 Overcapture Flag */
<> 144:ef7eb2e8f9f7 6426 #define TIM_SR_CC4OF 0x00001000U /*!<Capture/Compare 4 Overcapture Flag */
<> 144:ef7eb2e8f9f7 6427
<> 144:ef7eb2e8f9f7 6428 /******************* Bit definition for TIM_EGR register ********************/
<> 144:ef7eb2e8f9f7 6429 #define TIM_EGR_UG 0x00000001U /*!<Update Generation */
<> 144:ef7eb2e8f9f7 6430 #define TIM_EGR_CC1G 0x00000002U /*!<Capture/Compare 1 Generation */
<> 144:ef7eb2e8f9f7 6431 #define TIM_EGR_CC2G 0x00000004U /*!<Capture/Compare 2 Generation */
<> 144:ef7eb2e8f9f7 6432 #define TIM_EGR_CC3G 0x00000008U /*!<Capture/Compare 3 Generation */
<> 144:ef7eb2e8f9f7 6433 #define TIM_EGR_CC4G 0x00000010U /*!<Capture/Compare 4 Generation */
<> 144:ef7eb2e8f9f7 6434 #define TIM_EGR_COMG 0x00000020U /*!<Capture/Compare Control Update Generation */
<> 144:ef7eb2e8f9f7 6435 #define TIM_EGR_TG 0x00000040U /*!<Trigger Generation */
<> 144:ef7eb2e8f9f7 6436 #define TIM_EGR_BG 0x00000080U /*!<Break Generation */
<> 144:ef7eb2e8f9f7 6437
<> 144:ef7eb2e8f9f7 6438 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 144:ef7eb2e8f9f7 6439 #define TIM_CCMR1_CC1S 0x00000003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 144:ef7eb2e8f9f7 6440 #define TIM_CCMR1_CC1S_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6441 #define TIM_CCMR1_CC1S_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6442
<> 144:ef7eb2e8f9f7 6443 #define TIM_CCMR1_OC1FE 0x00000004U /*!<Output Compare 1 Fast enable */
<> 144:ef7eb2e8f9f7 6444 #define TIM_CCMR1_OC1PE 0x00000008U /*!<Output Compare 1 Preload enable */
<> 144:ef7eb2e8f9f7 6445
<> 144:ef7eb2e8f9f7 6446 #define TIM_CCMR1_OC1M 0x00000070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 144:ef7eb2e8f9f7 6447 #define TIM_CCMR1_OC1M_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6448 #define TIM_CCMR1_OC1M_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6449 #define TIM_CCMR1_OC1M_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6450
<> 144:ef7eb2e8f9f7 6451 #define TIM_CCMR1_OC1CE 0x00000080U /*!<Output Compare 1Clear Enable */
<> 144:ef7eb2e8f9f7 6452
<> 144:ef7eb2e8f9f7 6453 #define TIM_CCMR1_CC2S 0x00000300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 144:ef7eb2e8f9f7 6454 #define TIM_CCMR1_CC2S_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6455 #define TIM_CCMR1_CC2S_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6456
<> 144:ef7eb2e8f9f7 6457 #define TIM_CCMR1_OC2FE 0x00000400U /*!<Output Compare 2 Fast enable */
<> 144:ef7eb2e8f9f7 6458 #define TIM_CCMR1_OC2PE 0x00000800U /*!<Output Compare 2 Preload enable */
<> 144:ef7eb2e8f9f7 6459
<> 144:ef7eb2e8f9f7 6460 #define TIM_CCMR1_OC2M 0x00007000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 144:ef7eb2e8f9f7 6461 #define TIM_CCMR1_OC2M_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6462 #define TIM_CCMR1_OC2M_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6463 #define TIM_CCMR1_OC2M_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6464
<> 144:ef7eb2e8f9f7 6465 #define TIM_CCMR1_OC2CE 0x00008000U /*!<Output Compare 2 Clear Enable */
<> 144:ef7eb2e8f9f7 6466
<> 144:ef7eb2e8f9f7 6467 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 6468
<> 144:ef7eb2e8f9f7 6469 #define TIM_CCMR1_IC1PSC 0x0000000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 144:ef7eb2e8f9f7 6470 #define TIM_CCMR1_IC1PSC_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6471 #define TIM_CCMR1_IC1PSC_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6472
<> 144:ef7eb2e8f9f7 6473 #define TIM_CCMR1_IC1F 0x000000F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 144:ef7eb2e8f9f7 6474 #define TIM_CCMR1_IC1F_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6475 #define TIM_CCMR1_IC1F_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6476 #define TIM_CCMR1_IC1F_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6477 #define TIM_CCMR1_IC1F_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6478
<> 144:ef7eb2e8f9f7 6479 #define TIM_CCMR1_IC2PSC 0x00000C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 144:ef7eb2e8f9f7 6480 #define TIM_CCMR1_IC2PSC_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6481 #define TIM_CCMR1_IC2PSC_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6482
<> 144:ef7eb2e8f9f7 6483 #define TIM_CCMR1_IC2F 0x0000F000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 144:ef7eb2e8f9f7 6484 #define TIM_CCMR1_IC2F_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6485 #define TIM_CCMR1_IC2F_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6486 #define TIM_CCMR1_IC2F_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6487 #define TIM_CCMR1_IC2F_3 0x00008000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6488
<> 144:ef7eb2e8f9f7 6489 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 144:ef7eb2e8f9f7 6490 #define TIM_CCMR2_CC3S 0x00000003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 144:ef7eb2e8f9f7 6491 #define TIM_CCMR2_CC3S_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6492 #define TIM_CCMR2_CC3S_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6493
<> 144:ef7eb2e8f9f7 6494 #define TIM_CCMR2_OC3FE 0x00000004U /*!<Output Compare 3 Fast enable */
<> 144:ef7eb2e8f9f7 6495 #define TIM_CCMR2_OC3PE 0x00000008U /*!<Output Compare 3 Preload enable */
<> 144:ef7eb2e8f9f7 6496
<> 144:ef7eb2e8f9f7 6497 #define TIM_CCMR2_OC3M 0x00000070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 144:ef7eb2e8f9f7 6498 #define TIM_CCMR2_OC3M_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6499 #define TIM_CCMR2_OC3M_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6500 #define TIM_CCMR2_OC3M_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6501
<> 144:ef7eb2e8f9f7 6502 #define TIM_CCMR2_OC3CE 0x00000080U /*!<Output Compare 3 Clear Enable */
<> 144:ef7eb2e8f9f7 6503
<> 144:ef7eb2e8f9f7 6504 #define TIM_CCMR2_CC4S 0x00000300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 144:ef7eb2e8f9f7 6505 #define TIM_CCMR2_CC4S_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6506 #define TIM_CCMR2_CC4S_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6507
<> 144:ef7eb2e8f9f7 6508 #define TIM_CCMR2_OC4FE 0x00000400U /*!<Output Compare 4 Fast enable */
<> 144:ef7eb2e8f9f7 6509 #define TIM_CCMR2_OC4PE 0x00000800U /*!<Output Compare 4 Preload enable */
<> 144:ef7eb2e8f9f7 6510
<> 144:ef7eb2e8f9f7 6511 #define TIM_CCMR2_OC4M 0x00007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 144:ef7eb2e8f9f7 6512 #define TIM_CCMR2_OC4M_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6513 #define TIM_CCMR2_OC4M_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6514 #define TIM_CCMR2_OC4M_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6515
<> 144:ef7eb2e8f9f7 6516 #define TIM_CCMR2_OC4CE 0x00008000U /*!<Output Compare 4 Clear Enable */
<> 144:ef7eb2e8f9f7 6517
<> 144:ef7eb2e8f9f7 6518 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 6519
<> 144:ef7eb2e8f9f7 6520 #define TIM_CCMR2_IC3PSC 0x0000000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 144:ef7eb2e8f9f7 6521 #define TIM_CCMR2_IC3PSC_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6522 #define TIM_CCMR2_IC3PSC_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6523
<> 144:ef7eb2e8f9f7 6524 #define TIM_CCMR2_IC3F 0x000000F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 144:ef7eb2e8f9f7 6525 #define TIM_CCMR2_IC3F_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6526 #define TIM_CCMR2_IC3F_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6527 #define TIM_CCMR2_IC3F_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6528 #define TIM_CCMR2_IC3F_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6529
<> 144:ef7eb2e8f9f7 6530 #define TIM_CCMR2_IC4PSC 0x00000C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 144:ef7eb2e8f9f7 6531 #define TIM_CCMR2_IC4PSC_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6532 #define TIM_CCMR2_IC4PSC_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6533
<> 144:ef7eb2e8f9f7 6534 #define TIM_CCMR2_IC4F 0x0000F000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 144:ef7eb2e8f9f7 6535 #define TIM_CCMR2_IC4F_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6536 #define TIM_CCMR2_IC4F_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6537 #define TIM_CCMR2_IC4F_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6538 #define TIM_CCMR2_IC4F_3 0x00008000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6539
<> 144:ef7eb2e8f9f7 6540 /******************* Bit definition for TIM_CCER register *******************/
<> 144:ef7eb2e8f9f7 6541 #define TIM_CCER_CC1E 0x00000001U /*!<Capture/Compare 1 output enable */
<> 144:ef7eb2e8f9f7 6542 #define TIM_CCER_CC1P 0x00000002U /*!<Capture/Compare 1 output Polarity */
<> 144:ef7eb2e8f9f7 6543 #define TIM_CCER_CC1NE 0x00000004U /*!<Capture/Compare 1 Complementary output enable */
<> 144:ef7eb2e8f9f7 6544 #define TIM_CCER_CC1NP 0x00000008U /*!<Capture/Compare 1 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 6545 #define TIM_CCER_CC2E 0x00000010U /*!<Capture/Compare 2 output enable */
<> 144:ef7eb2e8f9f7 6546 #define TIM_CCER_CC2P 0x00000020U /*!<Capture/Compare 2 output Polarity */
<> 144:ef7eb2e8f9f7 6547 #define TIM_CCER_CC2NE 0x00000040U /*!<Capture/Compare 2 Complementary output enable */
<> 144:ef7eb2e8f9f7 6548 #define TIM_CCER_CC2NP 0x00000080U /*!<Capture/Compare 2 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 6549 #define TIM_CCER_CC3E 0x00000100U /*!<Capture/Compare 3 output enable */
<> 144:ef7eb2e8f9f7 6550 #define TIM_CCER_CC3P 0x00000200U /*!<Capture/Compare 3 output Polarity */
<> 144:ef7eb2e8f9f7 6551 #define TIM_CCER_CC3NE 0x00000400U /*!<Capture/Compare 3 Complementary output enable */
<> 144:ef7eb2e8f9f7 6552 #define TIM_CCER_CC3NP 0x00000800U /*!<Capture/Compare 3 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 6553 #define TIM_CCER_CC4E 0x00001000U /*!<Capture/Compare 4 output enable */
<> 144:ef7eb2e8f9f7 6554 #define TIM_CCER_CC4P 0x00002000U /*!<Capture/Compare 4 output Polarity */
<> 144:ef7eb2e8f9f7 6555 #define TIM_CCER_CC4NP 0x00008000U /*!<Capture/Compare 4 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 6556
<> 144:ef7eb2e8f9f7 6557 /******************* Bit definition for TIM_CNT register ********************/
<> 144:ef7eb2e8f9f7 6558 #define TIM_CNT_CNT 0x0000FFFFU /*!<Counter Value */
<> 144:ef7eb2e8f9f7 6559
<> 144:ef7eb2e8f9f7 6560 /******************* Bit definition for TIM_PSC register ********************/
<> 144:ef7eb2e8f9f7 6561 #define TIM_PSC_PSC 0x0000FFFFU /*!<Prescaler Value */
<> 144:ef7eb2e8f9f7 6562
<> 144:ef7eb2e8f9f7 6563 /******************* Bit definition for TIM_ARR register ********************/
<> 144:ef7eb2e8f9f7 6564 #define TIM_ARR_ARR 0x0000FFFFU /*!<actual auto-reload Value */
<> 144:ef7eb2e8f9f7 6565
<> 144:ef7eb2e8f9f7 6566 /******************* Bit definition for TIM_RCR register ********************/
<> 144:ef7eb2e8f9f7 6567 #define TIM_RCR_REP 0x000000FF /*!<Repetition Counter Value */
<> 144:ef7eb2e8f9f7 6568
<> 144:ef7eb2e8f9f7 6569 /******************* Bit definition for TIM_CCR1 register *******************/
<> 144:ef7eb2e8f9f7 6570 #define TIM_CCR1_CCR1 0x0000FFFFU /*!<Capture/Compare 1 Value */
<> 144:ef7eb2e8f9f7 6571
<> 144:ef7eb2e8f9f7 6572 /******************* Bit definition for TIM_CCR2 register *******************/
<> 144:ef7eb2e8f9f7 6573 #define TIM_CCR2_CCR2 0x0000FFFFU /*!<Capture/Compare 2 Value */
<> 144:ef7eb2e8f9f7 6574
<> 144:ef7eb2e8f9f7 6575 /******************* Bit definition for TIM_CCR3 register *******************/
<> 144:ef7eb2e8f9f7 6576 #define TIM_CCR3_CCR3 0x0000FFFFU /*!<Capture/Compare 3 Value */
<> 144:ef7eb2e8f9f7 6577
<> 144:ef7eb2e8f9f7 6578 /******************* Bit definition for TIM_CCR4 register *******************/
<> 144:ef7eb2e8f9f7 6579 #define TIM_CCR4_CCR4 0x0000FFFFU /*!<Capture/Compare 4 Value */
<> 144:ef7eb2e8f9f7 6580
<> 144:ef7eb2e8f9f7 6581 /******************* Bit definition for TIM_BDTR register *******************/
<> 144:ef7eb2e8f9f7 6582 #define TIM_BDTR_DTG 0x000000FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 144:ef7eb2e8f9f7 6583 #define TIM_BDTR_DTG_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6584 #define TIM_BDTR_DTG_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6585 #define TIM_BDTR_DTG_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6586 #define TIM_BDTR_DTG_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6587 #define TIM_BDTR_DTG_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6588 #define TIM_BDTR_DTG_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 6589 #define TIM_BDTR_DTG_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 6590 #define TIM_BDTR_DTG_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 6591
<> 144:ef7eb2e8f9f7 6592 #define TIM_BDTR_LOCK 0x00000300U /*!<LOCK[1:0] bits (Lock Configuration) */
<> 144:ef7eb2e8f9f7 6593 #define TIM_BDTR_LOCK_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6594 #define TIM_BDTR_LOCK_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6595
<> 144:ef7eb2e8f9f7 6596 #define TIM_BDTR_OSSI 0x00000400U /*!<Off-State Selection for Idle mode */
<> 144:ef7eb2e8f9f7 6597 #define TIM_BDTR_OSSR 0x00000800U /*!<Off-State Selection for Run mode */
<> 144:ef7eb2e8f9f7 6598 #define TIM_BDTR_BKE 0x00001000U /*!<Break enable */
<> 144:ef7eb2e8f9f7 6599 #define TIM_BDTR_BKP 0x00002000U /*!<Break Polarity */
<> 144:ef7eb2e8f9f7 6600 #define TIM_BDTR_AOE 0x00004000U /*!<Automatic Output enable */
<> 144:ef7eb2e8f9f7 6601 #define TIM_BDTR_MOE 0x00008000U /*!<Main Output enable */
<> 144:ef7eb2e8f9f7 6602
<> 144:ef7eb2e8f9f7 6603 /******************* Bit definition for TIM_DCR register ********************/
<> 144:ef7eb2e8f9f7 6604 #define TIM_DCR_DBA 0x0000001FU /*!<DBA[4:0] bits (DMA Base Address) */
<> 144:ef7eb2e8f9f7 6605 #define TIM_DCR_DBA_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6606 #define TIM_DCR_DBA_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6607 #define TIM_DCR_DBA_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6608 #define TIM_DCR_DBA_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6609 #define TIM_DCR_DBA_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6610
<> 144:ef7eb2e8f9f7 6611 #define TIM_DCR_DBL 0x00001F00U /*!<DBL[4:0] bits (DMA Burst Length) */
<> 144:ef7eb2e8f9f7 6612 #define TIM_DCR_DBL_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6613 #define TIM_DCR_DBL_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6614 #define TIM_DCR_DBL_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6615 #define TIM_DCR_DBL_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6616 #define TIM_DCR_DBL_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6617
<> 144:ef7eb2e8f9f7 6618 /******************* Bit definition for TIM_DMAR register *******************/
<> 144:ef7eb2e8f9f7 6619 #define TIM_DMAR_DMAB 0x0000FFFFU /*!<DMA register for burst accesses */
<> 144:ef7eb2e8f9f7 6620
<> 144:ef7eb2e8f9f7 6621 /******************* Bit definition for TIM_OR register *********************/
<> 144:ef7eb2e8f9f7 6622 #define TIM_OR_TI4_RMP 0x000000C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
<> 144:ef7eb2e8f9f7 6623 #define TIM_OR_TI4_RMP_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6624 #define TIM_OR_TI4_RMP_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6625 #define TIM_OR_ITR1_RMP 0x00000C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
<> 144:ef7eb2e8f9f7 6626 #define TIM_OR_ITR1_RMP_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6627 #define TIM_OR_ITR1_RMP_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6628
<> 144:ef7eb2e8f9f7 6629
<> 144:ef7eb2e8f9f7 6630 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6631 /* */
<> 144:ef7eb2e8f9f7 6632 /* Universal Synchronous Asynchronous Receiver Transmitter */
<> 144:ef7eb2e8f9f7 6633 /* */
<> 144:ef7eb2e8f9f7 6634 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6635 /******************* Bit definition for USART_SR register *******************/
<> 144:ef7eb2e8f9f7 6636 #define USART_SR_PE 0x00000001U /*!<Parity Error */
<> 144:ef7eb2e8f9f7 6637 #define USART_SR_FE 0x00000002U /*!<Framing Error */
<> 144:ef7eb2e8f9f7 6638 #define USART_SR_NE 0x00000004U /*!<Noise Error Flag */
<> 144:ef7eb2e8f9f7 6639 #define USART_SR_ORE 0x00000008U /*!<OverRun Error */
<> 144:ef7eb2e8f9f7 6640 #define USART_SR_IDLE 0x00000010U /*!<IDLE line detected */
<> 144:ef7eb2e8f9f7 6641 #define USART_SR_RXNE 0x00000020U /*!<Read Data Register Not Empty */
<> 144:ef7eb2e8f9f7 6642 #define USART_SR_TC 0x00000040U /*!<Transmission Complete */
<> 144:ef7eb2e8f9f7 6643 #define USART_SR_TXE 0x00000080U /*!<Transmit Data Register Empty */
<> 144:ef7eb2e8f9f7 6644 #define USART_SR_LBD 0x00000100U /*!<LIN Break Detection Flag */
<> 144:ef7eb2e8f9f7 6645 #define USART_SR_CTS 0x00000200U /*!<CTS Flag */
<> 144:ef7eb2e8f9f7 6646
<> 144:ef7eb2e8f9f7 6647 /******************* Bit definition for USART_DR register *******************/
<> 144:ef7eb2e8f9f7 6648 #define USART_DR_DR 0x000001FFU /*!<Data value */
<> 144:ef7eb2e8f9f7 6649
<> 144:ef7eb2e8f9f7 6650 /****************** Bit definition for USART_BRR register *******************/
<> 144:ef7eb2e8f9f7 6651 #define USART_BRR_DIV_Fraction 0x0000000FU /*!<Fraction of USARTDIV */
<> 144:ef7eb2e8f9f7 6652 #define USART_BRR_DIV_Mantissa 0x0000FFF0U /*!<Mantissa of USARTDIV */
<> 144:ef7eb2e8f9f7 6653
<> 144:ef7eb2e8f9f7 6654 /****************** Bit definition for USART_CR1 register *******************/
<> 144:ef7eb2e8f9f7 6655 #define USART_CR1_SBK 0x00000001U /*!<Send Break */
<> 144:ef7eb2e8f9f7 6656 #define USART_CR1_RWU 0x00000002U /*!<Receiver wakeup */
<> 144:ef7eb2e8f9f7 6657 #define USART_CR1_RE 0x00000004U /*!<Receiver Enable */
<> 144:ef7eb2e8f9f7 6658 #define USART_CR1_TE 0x00000008U /*!<Transmitter Enable */
<> 144:ef7eb2e8f9f7 6659 #define USART_CR1_IDLEIE 0x00000010U /*!<IDLE Interrupt Enable */
<> 144:ef7eb2e8f9f7 6660 #define USART_CR1_RXNEIE 0x00000020U /*!<RXNE Interrupt Enable */
<> 144:ef7eb2e8f9f7 6661 #define USART_CR1_TCIE 0x00000040U /*!<Transmission Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 6662 #define USART_CR1_TXEIE 0x00000080U /*!<PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 6663 #define USART_CR1_PEIE 0x00000100U /*!<PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 6664 #define USART_CR1_PS 0x00000200U /*!<Parity Selection */
<> 144:ef7eb2e8f9f7 6665 #define USART_CR1_PCE 0x00000400U /*!<Parity Control Enable */
<> 144:ef7eb2e8f9f7 6666 #define USART_CR1_WAKE 0x00000800U /*!<Wakeup method */
<> 144:ef7eb2e8f9f7 6667 #define USART_CR1_M 0x00001000U /*!<Word length */
<> 144:ef7eb2e8f9f7 6668 #define USART_CR1_UE 0x00002000U /*!<USART Enable */
<> 144:ef7eb2e8f9f7 6669 #define USART_CR1_OVER8 0x00008000U /*!<USART Oversampling by 8 enable */
<> 144:ef7eb2e8f9f7 6670
<> 144:ef7eb2e8f9f7 6671 /****************** Bit definition for USART_CR2 register *******************/
<> 144:ef7eb2e8f9f7 6672 #define USART_CR2_ADD 0x0000000FU /*!<Address of the USART node */
<> 144:ef7eb2e8f9f7 6673 #define USART_CR2_LBDL 0x00000020U /*!<LIN Break Detection Length */
<> 144:ef7eb2e8f9f7 6674 #define USART_CR2_LBDIE 0x00000040U /*!<LIN Break Detection Interrupt Enable */
<> 144:ef7eb2e8f9f7 6675 #define USART_CR2_LBCL 0x00000100U /*!<Last Bit Clock pulse */
<> 144:ef7eb2e8f9f7 6676 #define USART_CR2_CPHA 0x00000200U /*!<Clock Phase */
<> 144:ef7eb2e8f9f7 6677 #define USART_CR2_CPOL 0x00000400U /*!<Clock Polarity */
<> 144:ef7eb2e8f9f7 6678 #define USART_CR2_CLKEN 0x00000800U /*!<Clock Enable */
<> 144:ef7eb2e8f9f7 6679
<> 144:ef7eb2e8f9f7 6680 #define USART_CR2_STOP 0x00003000U /*!<STOP[1:0] bits (STOP bits) */
<> 144:ef7eb2e8f9f7 6681 #define USART_CR2_STOP_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6682 #define USART_CR2_STOP_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6683
<> 144:ef7eb2e8f9f7 6684 #define USART_CR2_LINEN 0x00004000U /*!<LIN mode enable */
<> 144:ef7eb2e8f9f7 6685
<> 144:ef7eb2e8f9f7 6686 /****************** Bit definition for USART_CR3 register *******************/
<> 144:ef7eb2e8f9f7 6687 #define USART_CR3_EIE 0x00000001U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 6688 #define USART_CR3_IREN 0x00000002U /*!<IrDA mode Enable */
<> 144:ef7eb2e8f9f7 6689 #define USART_CR3_IRLP 0x00000004U /*!<IrDA Low-Power */
<> 144:ef7eb2e8f9f7 6690 #define USART_CR3_HDSEL 0x00000008U /*!<Half-Duplex Selection */
<> 144:ef7eb2e8f9f7 6691 #define USART_CR3_NACK 0x00000010U /*!<Smartcard NACK enable */
<> 144:ef7eb2e8f9f7 6692 #define USART_CR3_SCEN 0x00000020U /*!<Smartcard mode enable */
<> 144:ef7eb2e8f9f7 6693 #define USART_CR3_DMAR 0x00000040U /*!<DMA Enable Receiver */
<> 144:ef7eb2e8f9f7 6694 #define USART_CR3_DMAT 0x00000080U /*!<DMA Enable Transmitter */
<> 144:ef7eb2e8f9f7 6695 #define USART_CR3_RTSE 0x00000100U /*!<RTS Enable */
<> 144:ef7eb2e8f9f7 6696 #define USART_CR3_CTSE 0x00000200U /*!<CTS Enable */
<> 144:ef7eb2e8f9f7 6697 #define USART_CR3_CTSIE 0x00000400U /*!<CTS Interrupt Enable */
<> 144:ef7eb2e8f9f7 6698 #define USART_CR3_ONEBIT 0x00000800U /*!<USART One bit method enable */
<> 144:ef7eb2e8f9f7 6699
<> 144:ef7eb2e8f9f7 6700 /****************** Bit definition for USART_GTPR register ******************/
<> 144:ef7eb2e8f9f7 6701 #define USART_GTPR_PSC 0x000000FFU /*!<PSC[7:0] bits (Prescaler value) */
<> 144:ef7eb2e8f9f7 6702 #define USART_GTPR_PSC_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6703 #define USART_GTPR_PSC_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6704 #define USART_GTPR_PSC_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6705 #define USART_GTPR_PSC_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6706 #define USART_GTPR_PSC_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6707 #define USART_GTPR_PSC_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 6708 #define USART_GTPR_PSC_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 6709 #define USART_GTPR_PSC_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 6710
<> 144:ef7eb2e8f9f7 6711 #define USART_GTPR_GT 0x0000FF00U /*!<Guard time value */
<> 144:ef7eb2e8f9f7 6712
<> 144:ef7eb2e8f9f7 6713 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6714 /* */
<> 144:ef7eb2e8f9f7 6715 /* Window WATCHDOG */
<> 144:ef7eb2e8f9f7 6716 /* */
<> 144:ef7eb2e8f9f7 6717 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6718 /******************* Bit definition for WWDG_CR register ********************/
<> 144:ef7eb2e8f9f7 6719 #define WWDG_CR_T 0x0000007FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 144:ef7eb2e8f9f7 6720 #define WWDG_CR_T_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6721 #define WWDG_CR_T_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6722 #define WWDG_CR_T_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6723 #define WWDG_CR_T_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6724 #define WWDG_CR_T_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6725 #define WWDG_CR_T_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 6726 #define WWDG_CR_T_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 6727
<> 144:ef7eb2e8f9f7 6728 /* Legacy defines */
<> 144:ef7eb2e8f9f7 6729 #define WWDG_CR_T0 WWDG_CR_T_0
<> 144:ef7eb2e8f9f7 6730 #define WWDG_CR_T1 WWDG_CR_T_1
<> 144:ef7eb2e8f9f7 6731 #define WWDG_CR_T2 WWDG_CR_T_2
<> 144:ef7eb2e8f9f7 6732 #define WWDG_CR_T3 WWDG_CR_T_3
<> 144:ef7eb2e8f9f7 6733 #define WWDG_CR_T4 WWDG_CR_T_4
<> 144:ef7eb2e8f9f7 6734 #define WWDG_CR_T5 WWDG_CR_T_5
<> 144:ef7eb2e8f9f7 6735 #define WWDG_CR_T6 WWDG_CR_T_6
<> 144:ef7eb2e8f9f7 6736 #define WWDG_CR_WDGA 0x00000080U /*!<Activation bit */
<> 144:ef7eb2e8f9f7 6737
<> 144:ef7eb2e8f9f7 6738 /******************* Bit definition for WWDG_CFR register *******************/
<> 144:ef7eb2e8f9f7 6739 #define WWDG_CFR_W 0x0000007FU /*!<W[6:0] bits (7-bit window value) */
<> 144:ef7eb2e8f9f7 6740 #define WWDG_CFR_W_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6741 #define WWDG_CFR_W_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6742 #define WWDG_CFR_W_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6743 #define WWDG_CFR_W_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6744 #define WWDG_CFR_W_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6745 #define WWDG_CFR_W_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 6746 #define WWDG_CFR_W_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 6747
<> 144:ef7eb2e8f9f7 6748 /* Legacy defines */
<> 144:ef7eb2e8f9f7 6749 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 144:ef7eb2e8f9f7 6750 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 144:ef7eb2e8f9f7 6751 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 144:ef7eb2e8f9f7 6752 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 144:ef7eb2e8f9f7 6753 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 144:ef7eb2e8f9f7 6754 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 144:ef7eb2e8f9f7 6755 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 144:ef7eb2e8f9f7 6756
<> 144:ef7eb2e8f9f7 6757 #define WWDG_CFR_WDGTB 0x00000180U /*!<WDGTB[1:0] bits (Timer Base) */
<> 144:ef7eb2e8f9f7 6758 #define WWDG_CFR_WDGTB_0 0x00000080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6759 #define WWDG_CFR_WDGTB_1 0x00000100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6760
<> 144:ef7eb2e8f9f7 6761 /* Legacy defines */
<> 144:ef7eb2e8f9f7 6762 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 144:ef7eb2e8f9f7 6763 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 144:ef7eb2e8f9f7 6764
<> 144:ef7eb2e8f9f7 6765 #define WWDG_CFR_EWI 0x00000200U /*!<Early Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 6766
<> 144:ef7eb2e8f9f7 6767 /******************* Bit definition for WWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 6768 #define WWDG_SR_EWIF 0x00000001U /*!<Early Wakeup Interrupt Flag */
<> 144:ef7eb2e8f9f7 6769
<> 144:ef7eb2e8f9f7 6770 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6771 /* */
<> 144:ef7eb2e8f9f7 6772 /* DBG */
<> 144:ef7eb2e8f9f7 6773 /* */
<> 144:ef7eb2e8f9f7 6774 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6775 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 144:ef7eb2e8f9f7 6776 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
<> 144:ef7eb2e8f9f7 6777 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
<> 144:ef7eb2e8f9f7 6778
<> 144:ef7eb2e8f9f7 6779 /******************** Bit definition for DBGMCU_CR register *****************/
<> 144:ef7eb2e8f9f7 6780 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
<> 144:ef7eb2e8f9f7 6781 #define DBGMCU_CR_DBG_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 6782 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
<> 144:ef7eb2e8f9f7 6783 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
<> 144:ef7eb2e8f9f7 6784
<> 144:ef7eb2e8f9f7 6785 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
<> 144:ef7eb2e8f9f7 6786 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6787 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6788
<> 144:ef7eb2e8f9f7 6789 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 144:ef7eb2e8f9f7 6790 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
<> 144:ef7eb2e8f9f7 6791 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 6792 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
<> 144:ef7eb2e8f9f7 6793 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
<> 144:ef7eb2e8f9f7 6794 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
<> 144:ef7eb2e8f9f7 6795 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
<> 144:ef7eb2e8f9f7 6796 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
<> 144:ef7eb2e8f9f7 6797 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
<> 144:ef7eb2e8f9f7 6798 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
<> 144:ef7eb2e8f9f7 6799 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
<> 144:ef7eb2e8f9f7 6800 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
<> 144:ef7eb2e8f9f7 6801 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
<> 144:ef7eb2e8f9f7 6802 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
<> 144:ef7eb2e8f9f7 6803 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
<> 144:ef7eb2e8f9f7 6804 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
<> 144:ef7eb2e8f9f7 6805 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
<> 144:ef7eb2e8f9f7 6806 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
<> 144:ef7eb2e8f9f7 6807 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 6808 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
<> 144:ef7eb2e8f9f7 6809
<> 144:ef7eb2e8f9f7 6810 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 144:ef7eb2e8f9f7 6811 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
<> 144:ef7eb2e8f9f7 6812 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 6813 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
<> 144:ef7eb2e8f9f7 6814 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
<> 144:ef7eb2e8f9f7 6815 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
<> 144:ef7eb2e8f9f7 6816
<> 144:ef7eb2e8f9f7 6817 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6818 /* */
<> 144:ef7eb2e8f9f7 6819 /* Ethernet MAC Registers bits definitions */
<> 144:ef7eb2e8f9f7 6820 /* */
<> 144:ef7eb2e8f9f7 6821 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6822 /* Bit definition for Ethernet MAC Control Register register */
<> 144:ef7eb2e8f9f7 6823 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
<> 144:ef7eb2e8f9f7 6824 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
<> 144:ef7eb2e8f9f7 6825 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
<> 144:ef7eb2e8f9f7 6826 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
<> 144:ef7eb2e8f9f7 6827 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
<> 144:ef7eb2e8f9f7 6828 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
<> 144:ef7eb2e8f9f7 6829 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
<> 144:ef7eb2e8f9f7 6830 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
<> 144:ef7eb2e8f9f7 6831 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
<> 144:ef7eb2e8f9f7 6832 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
<> 144:ef7eb2e8f9f7 6833 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
<> 144:ef7eb2e8f9f7 6834 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
<> 144:ef7eb2e8f9f7 6835 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
<> 144:ef7eb2e8f9f7 6836 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
<> 144:ef7eb2e8f9f7 6837 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
<> 144:ef7eb2e8f9f7 6838 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
<> 144:ef7eb2e8f9f7 6839 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
<> 144:ef7eb2e8f9f7 6840 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
<> 144:ef7eb2e8f9f7 6841 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
<> 144:ef7eb2e8f9f7 6842 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
<> 144:ef7eb2e8f9f7 6843 a transmission attempt during retries after a collision: 0 =< r <2^k */
<> 144:ef7eb2e8f9f7 6844 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
<> 144:ef7eb2e8f9f7 6845 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
<> 144:ef7eb2e8f9f7 6846 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
<> 144:ef7eb2e8f9f7 6847 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
<> 144:ef7eb2e8f9f7 6848 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
<> 144:ef7eb2e8f9f7 6849 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
<> 144:ef7eb2e8f9f7 6850 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
<> 144:ef7eb2e8f9f7 6851
<> 144:ef7eb2e8f9f7 6852 /* Bit definition for Ethernet MAC Frame Filter Register */
<> 144:ef7eb2e8f9f7 6853 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
<> 144:ef7eb2e8f9f7 6854 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
<> 144:ef7eb2e8f9f7 6855 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
<> 144:ef7eb2e8f9f7 6856 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
<> 144:ef7eb2e8f9f7 6857 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
<> 144:ef7eb2e8f9f7 6858 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
<> 144:ef7eb2e8f9f7 6859 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
<> 144:ef7eb2e8f9f7 6860 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
<> 144:ef7eb2e8f9f7 6861 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
<> 144:ef7eb2e8f9f7 6862 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
<> 144:ef7eb2e8f9f7 6863 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
<> 144:ef7eb2e8f9f7 6864 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
<> 144:ef7eb2e8f9f7 6865 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
<> 144:ef7eb2e8f9f7 6866 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
<> 144:ef7eb2e8f9f7 6867
<> 144:ef7eb2e8f9f7 6868 /* Bit definition for Ethernet MAC Hash Table High Register */
<> 144:ef7eb2e8f9f7 6869 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
<> 144:ef7eb2e8f9f7 6870
<> 144:ef7eb2e8f9f7 6871 /* Bit definition for Ethernet MAC Hash Table Low Register */
<> 144:ef7eb2e8f9f7 6872 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
<> 144:ef7eb2e8f9f7 6873
<> 144:ef7eb2e8f9f7 6874 /* Bit definition for Ethernet MAC MII Address Register */
<> 144:ef7eb2e8f9f7 6875 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
<> 144:ef7eb2e8f9f7 6876 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
<> 144:ef7eb2e8f9f7 6877 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
<> 144:ef7eb2e8f9f7 6878 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
<> 144:ef7eb2e8f9f7 6879 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-120 MHz; MDC clock= HCLK/62 */
<> 144:ef7eb2e8f9f7 6880 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
<> 144:ef7eb2e8f9f7 6881 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/42 */
<> 144:ef7eb2e8f9f7 6882 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
<> 144:ef7eb2e8f9f7 6883 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
<> 144:ef7eb2e8f9f7 6884
<> 144:ef7eb2e8f9f7 6885 /* Bit definition for Ethernet MAC MII Data Register */
<> 144:ef7eb2e8f9f7 6886 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
<> 144:ef7eb2e8f9f7 6887
<> 144:ef7eb2e8f9f7 6888 /* Bit definition for Ethernet MAC Flow Control Register */
<> 144:ef7eb2e8f9f7 6889 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
<> 144:ef7eb2e8f9f7 6890 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
<> 144:ef7eb2e8f9f7 6891 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
<> 144:ef7eb2e8f9f7 6892 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
<> 144:ef7eb2e8f9f7 6893 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
<> 144:ef7eb2e8f9f7 6894 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
<> 144:ef7eb2e8f9f7 6895 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
<> 144:ef7eb2e8f9f7 6896 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
<> 144:ef7eb2e8f9f7 6897 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
<> 144:ef7eb2e8f9f7 6898 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
<> 144:ef7eb2e8f9f7 6899 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
<> 144:ef7eb2e8f9f7 6900
<> 144:ef7eb2e8f9f7 6901 /* Bit definition for Ethernet MAC VLAN Tag Register */
<> 144:ef7eb2e8f9f7 6902 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
<> 144:ef7eb2e8f9f7 6903 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
<> 144:ef7eb2e8f9f7 6904
<> 144:ef7eb2e8f9f7 6905 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
<> 144:ef7eb2e8f9f7 6906 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
<> 144:ef7eb2e8f9f7 6907 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
<> 144:ef7eb2e8f9f7 6908 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
<> 144:ef7eb2e8f9f7 6909 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
<> 144:ef7eb2e8f9f7 6910 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
<> 144:ef7eb2e8f9f7 6911 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
<> 144:ef7eb2e8f9f7 6912 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
<> 144:ef7eb2e8f9f7 6913 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
<> 144:ef7eb2e8f9f7 6914 RSVD - Filter1 Command - RSVD - Filter0 Command
<> 144:ef7eb2e8f9f7 6915 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
<> 144:ef7eb2e8f9f7 6916 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
<> 144:ef7eb2e8f9f7 6917 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
<> 144:ef7eb2e8f9f7 6918
<> 144:ef7eb2e8f9f7 6919 /* Bit definition for Ethernet MAC PMT Control and Status Register */
<> 144:ef7eb2e8f9f7 6920 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
<> 144:ef7eb2e8f9f7 6921 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
<> 144:ef7eb2e8f9f7 6922 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
<> 144:ef7eb2e8f9f7 6923 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
<> 144:ef7eb2e8f9f7 6924 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
<> 144:ef7eb2e8f9f7 6925 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
<> 144:ef7eb2e8f9f7 6926 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
<> 144:ef7eb2e8f9f7 6927
<> 144:ef7eb2e8f9f7 6928 /* Bit definition for Ethernet MAC Status Register */
<> 144:ef7eb2e8f9f7 6929 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
<> 144:ef7eb2e8f9f7 6930 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
<> 144:ef7eb2e8f9f7 6931 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
<> 144:ef7eb2e8f9f7 6932 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
<> 144:ef7eb2e8f9f7 6933 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
<> 144:ef7eb2e8f9f7 6934
<> 144:ef7eb2e8f9f7 6935 /* Bit definition for Ethernet MAC Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 6936 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
<> 144:ef7eb2e8f9f7 6937 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
<> 144:ef7eb2e8f9f7 6938
<> 144:ef7eb2e8f9f7 6939 /* Bit definition for Ethernet MAC Address0 High Register */
<> 144:ef7eb2e8f9f7 6940 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
<> 144:ef7eb2e8f9f7 6941
<> 144:ef7eb2e8f9f7 6942 /* Bit definition for Ethernet MAC Address0 Low Register */
<> 144:ef7eb2e8f9f7 6943 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
<> 144:ef7eb2e8f9f7 6944
<> 144:ef7eb2e8f9f7 6945 /* Bit definition for Ethernet MAC Address1 High Register */
<> 144:ef7eb2e8f9f7 6946 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
<> 144:ef7eb2e8f9f7 6947 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
<> 144:ef7eb2e8f9f7 6948 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
<> 144:ef7eb2e8f9f7 6949 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 6950 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 6951 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 6952 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 6953 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 6954 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
<> 144:ef7eb2e8f9f7 6955 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
<> 144:ef7eb2e8f9f7 6956
<> 144:ef7eb2e8f9f7 6957 /* Bit definition for Ethernet MAC Address1 Low Register */
<> 144:ef7eb2e8f9f7 6958 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
<> 144:ef7eb2e8f9f7 6959
<> 144:ef7eb2e8f9f7 6960 /* Bit definition for Ethernet MAC Address2 High Register */
<> 144:ef7eb2e8f9f7 6961 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
<> 144:ef7eb2e8f9f7 6962 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
<> 144:ef7eb2e8f9f7 6963 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
<> 144:ef7eb2e8f9f7 6964 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 6965 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 6966 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 6967 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 6968 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 6969 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 144:ef7eb2e8f9f7 6970 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
<> 144:ef7eb2e8f9f7 6971
<> 144:ef7eb2e8f9f7 6972 /* Bit definition for Ethernet MAC Address2 Low Register */
<> 144:ef7eb2e8f9f7 6973 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
<> 144:ef7eb2e8f9f7 6974
<> 144:ef7eb2e8f9f7 6975 /* Bit definition for Ethernet MAC Address3 High Register */
<> 144:ef7eb2e8f9f7 6976 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
<> 144:ef7eb2e8f9f7 6977 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
<> 144:ef7eb2e8f9f7 6978 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
<> 144:ef7eb2e8f9f7 6979 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 6980 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 6981 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 6982 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 6983 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 6984 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 144:ef7eb2e8f9f7 6985 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
<> 144:ef7eb2e8f9f7 6986
<> 144:ef7eb2e8f9f7 6987 /* Bit definition for Ethernet MAC Address3 Low Register */
<> 144:ef7eb2e8f9f7 6988 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
<> 144:ef7eb2e8f9f7 6989
<> 144:ef7eb2e8f9f7 6990 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6991 /* Ethernet MMC Registers bits definition */
<> 144:ef7eb2e8f9f7 6992 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6993
<> 144:ef7eb2e8f9f7 6994 /* Bit definition for Ethernet MMC Control Register */
<> 144:ef7eb2e8f9f7 6995 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
<> 144:ef7eb2e8f9f7 6996 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
<> 144:ef7eb2e8f9f7 6997 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
<> 144:ef7eb2e8f9f7 6998 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
<> 144:ef7eb2e8f9f7 6999 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
<> 144:ef7eb2e8f9f7 7000 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
<> 144:ef7eb2e8f9f7 7001
<> 144:ef7eb2e8f9f7 7002 /* Bit definition for Ethernet MMC Receive Interrupt Register */
<> 144:ef7eb2e8f9f7 7003 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7004 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7005 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7006
<> 144:ef7eb2e8f9f7 7007 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
<> 144:ef7eb2e8f9f7 7008 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7009 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7010 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7011
<> 144:ef7eb2e8f9f7 7012 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 7013 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7014 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when Rx alignment error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7015 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7016
<> 144:ef7eb2e8f9f7 7017 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 7018 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7019 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7020 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 7021
<> 144:ef7eb2e8f9f7 7022 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
<> 144:ef7eb2e8f9f7 7023 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
<> 144:ef7eb2e8f9f7 7024
<> 144:ef7eb2e8f9f7 7025 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
<> 144:ef7eb2e8f9f7 7026 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
<> 144:ef7eb2e8f9f7 7027
<> 144:ef7eb2e8f9f7 7028 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
<> 144:ef7eb2e8f9f7 7029 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
<> 144:ef7eb2e8f9f7 7030
<> 144:ef7eb2e8f9f7 7031 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
<> 144:ef7eb2e8f9f7 7032 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
<> 144:ef7eb2e8f9f7 7033
<> 144:ef7eb2e8f9f7 7034 /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
<> 144:ef7eb2e8f9f7 7035 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
<> 144:ef7eb2e8f9f7 7036
<> 144:ef7eb2e8f9f7 7037 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
<> 144:ef7eb2e8f9f7 7038 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
<> 144:ef7eb2e8f9f7 7039
<> 144:ef7eb2e8f9f7 7040 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7041 /* Ethernet PTP Registers bits definition */
<> 144:ef7eb2e8f9f7 7042 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7043
<> 144:ef7eb2e8f9f7 7044 /* Bit definition for Ethernet PTP Time Stamp Control Register */
<> 144:ef7eb2e8f9f7 7045 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
<> 144:ef7eb2e8f9f7 7046 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
<> 144:ef7eb2e8f9f7 7047 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
<> 144:ef7eb2e8f9f7 7048 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
<> 144:ef7eb2e8f9f7 7049 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
<> 144:ef7eb2e8f9f7 7050 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
<> 144:ef7eb2e8f9f7 7051 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
<> 144:ef7eb2e8f9f7 7052 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
<> 144:ef7eb2e8f9f7 7053 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
<> 144:ef7eb2e8f9f7 7054
<> 144:ef7eb2e8f9f7 7055 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
<> 144:ef7eb2e8f9f7 7056 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
<> 144:ef7eb2e8f9f7 7057 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
<> 144:ef7eb2e8f9f7 7058 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
<> 144:ef7eb2e8f9f7 7059 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
<> 144:ef7eb2e8f9f7 7060 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
<> 144:ef7eb2e8f9f7 7061
<> 144:ef7eb2e8f9f7 7062 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
<> 144:ef7eb2e8f9f7 7063 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
<> 144:ef7eb2e8f9f7 7064
<> 144:ef7eb2e8f9f7 7065 /* Bit definition for Ethernet PTP Time Stamp High Register */
<> 144:ef7eb2e8f9f7 7066 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
<> 144:ef7eb2e8f9f7 7067
<> 144:ef7eb2e8f9f7 7068 /* Bit definition for Ethernet PTP Time Stamp Low Register */
<> 144:ef7eb2e8f9f7 7069 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
<> 144:ef7eb2e8f9f7 7070 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
<> 144:ef7eb2e8f9f7 7071
<> 144:ef7eb2e8f9f7 7072 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
<> 144:ef7eb2e8f9f7 7073 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
<> 144:ef7eb2e8f9f7 7074
<> 144:ef7eb2e8f9f7 7075 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
<> 144:ef7eb2e8f9f7 7076 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
<> 144:ef7eb2e8f9f7 7077 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
<> 144:ef7eb2e8f9f7 7078
<> 144:ef7eb2e8f9f7 7079 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
<> 144:ef7eb2e8f9f7 7080 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
<> 144:ef7eb2e8f9f7 7081
<> 144:ef7eb2e8f9f7 7082 /* Bit definition for Ethernet PTP Target Time High Register */
<> 144:ef7eb2e8f9f7 7083 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
<> 144:ef7eb2e8f9f7 7084
<> 144:ef7eb2e8f9f7 7085 /* Bit definition for Ethernet PTP Target Time Low Register */
<> 144:ef7eb2e8f9f7 7086 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
<> 144:ef7eb2e8f9f7 7087
<> 144:ef7eb2e8f9f7 7088 /* Bit definition for Ethernet PTP Time Stamp Status Register */
<> 144:ef7eb2e8f9f7 7089 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
<> 144:ef7eb2e8f9f7 7090 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
<> 144:ef7eb2e8f9f7 7091
<> 144:ef7eb2e8f9f7 7092 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7093 /* Ethernet DMA Registers bits definition */
<> 144:ef7eb2e8f9f7 7094 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7095
<> 144:ef7eb2e8f9f7 7096 /* Bit definition for Ethernet DMA Bus Mode Register */
<> 144:ef7eb2e8f9f7 7097 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
<> 144:ef7eb2e8f9f7 7098 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
<> 144:ef7eb2e8f9f7 7099 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
<> 144:ef7eb2e8f9f7 7100 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
<> 144:ef7eb2e8f9f7 7101 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
<> 144:ef7eb2e8f9f7 7102 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
<> 144:ef7eb2e8f9f7 7103 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 7104 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 7105 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 7106 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 7107 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 7108 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 7109 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 7110 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 7111 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
<> 144:ef7eb2e8f9f7 7112 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
<> 144:ef7eb2e8f9f7 7113 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
<> 144:ef7eb2e8f9f7 7114 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 7115 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 7116 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 7117 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 7118 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 7119 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
<> 144:ef7eb2e8f9f7 7120 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
<> 144:ef7eb2e8f9f7 7121 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
<> 144:ef7eb2e8f9f7 7122 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 7123 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 7124 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 7125 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 7126 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 7127 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 7128 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 7129 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 7130 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
<> 144:ef7eb2e8f9f7 7131 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
<> 144:ef7eb2e8f9f7 7132 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
<> 144:ef7eb2e8f9f7 7133 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
<> 144:ef7eb2e8f9f7 7134 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
<> 144:ef7eb2e8f9f7 7135 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
<> 144:ef7eb2e8f9f7 7136
<> 144:ef7eb2e8f9f7 7137 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
<> 144:ef7eb2e8f9f7 7138 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
<> 144:ef7eb2e8f9f7 7139
<> 144:ef7eb2e8f9f7 7140 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
<> 144:ef7eb2e8f9f7 7141 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
<> 144:ef7eb2e8f9f7 7142
<> 144:ef7eb2e8f9f7 7143 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
<> 144:ef7eb2e8f9f7 7144 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
<> 144:ef7eb2e8f9f7 7145
<> 144:ef7eb2e8f9f7 7146 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
<> 144:ef7eb2e8f9f7 7147 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
<> 144:ef7eb2e8f9f7 7148
<> 144:ef7eb2e8f9f7 7149 /* Bit definition for Ethernet DMA Status Register */
<> 144:ef7eb2e8f9f7 7150 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
<> 144:ef7eb2e8f9f7 7151 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
<> 144:ef7eb2e8f9f7 7152 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
<> 144:ef7eb2e8f9f7 7153 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
<> 144:ef7eb2e8f9f7 7154 /* combination with EBS[2:0] for GetFlagStatus function */
<> 144:ef7eb2e8f9f7 7155 #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
<> 144:ef7eb2e8f9f7 7156 #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
<> 144:ef7eb2e8f9f7 7157 #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
<> 144:ef7eb2e8f9f7 7158 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
<> 144:ef7eb2e8f9f7 7159 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
<> 144:ef7eb2e8f9f7 7160 #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
<> 144:ef7eb2e8f9f7 7161 #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
<> 144:ef7eb2e8f9f7 7162 #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
<> 144:ef7eb2e8f9f7 7163 #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailable */
<> 144:ef7eb2e8f9f7 7164 #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
<> 144:ef7eb2e8f9f7 7165 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
<> 144:ef7eb2e8f9f7 7166 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
<> 144:ef7eb2e8f9f7 7167 #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
<> 144:ef7eb2e8f9f7 7168 #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
<> 144:ef7eb2e8f9f7 7169 #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
<> 144:ef7eb2e8f9f7 7170 #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
<> 144:ef7eb2e8f9f7 7171 #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the receive frame into host memory */
<> 144:ef7eb2e8f9f7 7172 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
<> 144:ef7eb2e8f9f7 7173 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
<> 144:ef7eb2e8f9f7 7174 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
<> 144:ef7eb2e8f9f7 7175 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
<> 144:ef7eb2e8f9f7 7176 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
<> 144:ef7eb2e8f9f7 7177 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
<> 144:ef7eb2e8f9f7 7178 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
<> 144:ef7eb2e8f9f7 7179 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
<> 144:ef7eb2e8f9f7 7180 #define ETH_DMASR_RS 0x00000040U /* Receive status */
<> 144:ef7eb2e8f9f7 7181 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
<> 144:ef7eb2e8f9f7 7182 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
<> 144:ef7eb2e8f9f7 7183 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
<> 144:ef7eb2e8f9f7 7184 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
<> 144:ef7eb2e8f9f7 7185 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
<> 144:ef7eb2e8f9f7 7186 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
<> 144:ef7eb2e8f9f7 7187
<> 144:ef7eb2e8f9f7 7188 /* Bit definition for Ethernet DMA Operation Mode Register */
<> 144:ef7eb2e8f9f7 7189 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
<> 144:ef7eb2e8f9f7 7190 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
<> 144:ef7eb2e8f9f7 7191 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
<> 144:ef7eb2e8f9f7 7192 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
<> 144:ef7eb2e8f9f7 7193 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
<> 144:ef7eb2e8f9f7 7194 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
<> 144:ef7eb2e8f9f7 7195 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 7196 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 7197 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
<> 144:ef7eb2e8f9f7 7198 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
<> 144:ef7eb2e8f9f7 7199 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
<> 144:ef7eb2e8f9f7 7200 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 7201 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
<> 144:ef7eb2e8f9f7 7202 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
<> 144:ef7eb2e8f9f7 7203 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
<> 144:ef7eb2e8f9f7 7204 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
<> 144:ef7eb2e8f9f7 7205 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
<> 144:ef7eb2e8f9f7 7206 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
<> 144:ef7eb2e8f9f7 7207 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 7208 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 7209 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
<> 144:ef7eb2e8f9f7 7210 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 7211 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
<> 144:ef7eb2e8f9f7 7212 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
<> 144:ef7eb2e8f9f7 7213
<> 144:ef7eb2e8f9f7 7214 /* Bit definition for Ethernet DMA Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 7215 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
<> 144:ef7eb2e8f9f7 7216 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
<> 144:ef7eb2e8f9f7 7217 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
<> 144:ef7eb2e8f9f7 7218 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
<> 144:ef7eb2e8f9f7 7219 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
<> 144:ef7eb2e8f9f7 7220 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
<> 144:ef7eb2e8f9f7 7221 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
<> 144:ef7eb2e8f9f7 7222 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
<> 144:ef7eb2e8f9f7 7223 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
<> 144:ef7eb2e8f9f7 7224 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
<> 144:ef7eb2e8f9f7 7225 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
<> 144:ef7eb2e8f9f7 7226 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
<> 144:ef7eb2e8f9f7 7227 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
<> 144:ef7eb2e8f9f7 7228 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
<> 144:ef7eb2e8f9f7 7229 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
<> 144:ef7eb2e8f9f7 7230
<> 144:ef7eb2e8f9f7 7231 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
<> 144:ef7eb2e8f9f7 7232 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
<> 144:ef7eb2e8f9f7 7233 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
<> 144:ef7eb2e8f9f7 7234 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
<> 144:ef7eb2e8f9f7 7235 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
<> 144:ef7eb2e8f9f7 7236
<> 144:ef7eb2e8f9f7 7237 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
<> 144:ef7eb2e8f9f7 7238 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
<> 144:ef7eb2e8f9f7 7239
<> 144:ef7eb2e8f9f7 7240 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
<> 144:ef7eb2e8f9f7 7241 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
<> 144:ef7eb2e8f9f7 7242
<> 144:ef7eb2e8f9f7 7243 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
<> 144:ef7eb2e8f9f7 7244 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
<> 144:ef7eb2e8f9f7 7245
<> 144:ef7eb2e8f9f7 7246 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
<> 144:ef7eb2e8f9f7 7247 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
<> 144:ef7eb2e8f9f7 7248
<> 144:ef7eb2e8f9f7 7249 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7250 /* */
<> 144:ef7eb2e8f9f7 7251 /* USB_OTG */
<> 144:ef7eb2e8f9f7 7252 /* */
<> 144:ef7eb2e8f9f7 7253 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7254 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
<> 144:ef7eb2e8f9f7 7255 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
<> 144:ef7eb2e8f9f7 7256 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
<> 144:ef7eb2e8f9f7 7257 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
<> 144:ef7eb2e8f9f7 7258 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
<> 144:ef7eb2e8f9f7 7259 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
<> 144:ef7eb2e8f9f7 7260 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
<> 144:ef7eb2e8f9f7 7261 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
<> 144:ef7eb2e8f9f7 7262 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
<> 144:ef7eb2e8f9f7 7263 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
<> 144:ef7eb2e8f9f7 7264 #define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
<> 144:ef7eb2e8f9f7 7265
<> 144:ef7eb2e8f9f7 7266 /******************** Bit definition forUSB_OTG_HCFG register ********************/
<> 144:ef7eb2e8f9f7 7267
<> 144:ef7eb2e8f9f7 7268 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
<> 144:ef7eb2e8f9f7 7269 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7270 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7271 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
<> 144:ef7eb2e8f9f7 7272
<> 144:ef7eb2e8f9f7 7273 /******************** Bit definition forUSB_OTG_DCFG register ********************/
<> 144:ef7eb2e8f9f7 7274
<> 144:ef7eb2e8f9f7 7275 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
<> 144:ef7eb2e8f9f7 7276 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7277 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7278 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
<> 144:ef7eb2e8f9f7 7279
<> 144:ef7eb2e8f9f7 7280 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
<> 144:ef7eb2e8f9f7 7281 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7282 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7283 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7284 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7285 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7286 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7287 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7288
<> 144:ef7eb2e8f9f7 7289 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
<> 144:ef7eb2e8f9f7 7290 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7291 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7292
<> 144:ef7eb2e8f9f7 7293 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
<> 144:ef7eb2e8f9f7 7294 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7295 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7296
<> 144:ef7eb2e8f9f7 7297 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
<> 144:ef7eb2e8f9f7 7298 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
<> 144:ef7eb2e8f9f7 7299 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
<> 144:ef7eb2e8f9f7 7300 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
<> 144:ef7eb2e8f9f7 7301
<> 144:ef7eb2e8f9f7 7302 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
<> 144:ef7eb2e8f9f7 7303 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
<> 144:ef7eb2e8f9f7 7304 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
<> 144:ef7eb2e8f9f7 7305 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
<> 144:ef7eb2e8f9f7 7306 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
<> 144:ef7eb2e8f9f7 7307 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
<> 144:ef7eb2e8f9f7 7308 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
<> 144:ef7eb2e8f9f7 7309
<> 144:ef7eb2e8f9f7 7310 /******************** Bit definition forUSB_OTG_DCTL register ********************/
<> 144:ef7eb2e8f9f7 7311 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
<> 144:ef7eb2e8f9f7 7312 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
<> 144:ef7eb2e8f9f7 7313 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
<> 144:ef7eb2e8f9f7 7314 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
<> 144:ef7eb2e8f9f7 7315
<> 144:ef7eb2e8f9f7 7316 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
<> 144:ef7eb2e8f9f7 7317 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7318 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7319 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7320 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
<> 144:ef7eb2e8f9f7 7321 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
<> 144:ef7eb2e8f9f7 7322 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
<> 144:ef7eb2e8f9f7 7323 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
<> 144:ef7eb2e8f9f7 7324 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
<> 144:ef7eb2e8f9f7 7325
<> 144:ef7eb2e8f9f7 7326 /******************** Bit definition forUSB_OTG_HFIR register ********************/
<> 144:ef7eb2e8f9f7 7327 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
<> 144:ef7eb2e8f9f7 7328
<> 144:ef7eb2e8f9f7 7329 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
<> 144:ef7eb2e8f9f7 7330 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
<> 144:ef7eb2e8f9f7 7331 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
<> 144:ef7eb2e8f9f7 7332
<> 144:ef7eb2e8f9f7 7333 /******************** Bit definition forUSB_OTG_DSTS register ********************/
<> 144:ef7eb2e8f9f7 7334 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
<> 144:ef7eb2e8f9f7 7335
<> 144:ef7eb2e8f9f7 7336 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
<> 144:ef7eb2e8f9f7 7337 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7338 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7339 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
<> 144:ef7eb2e8f9f7 7340 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
<> 144:ef7eb2e8f9f7 7341
<> 144:ef7eb2e8f9f7 7342 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
<> 144:ef7eb2e8f9f7 7343 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
<> 144:ef7eb2e8f9f7 7344
<> 144:ef7eb2e8f9f7 7345 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
<> 144:ef7eb2e8f9f7 7346 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7347 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7348 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7349 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7350 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
<> 144:ef7eb2e8f9f7 7351 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
<> 144:ef7eb2e8f9f7 7352 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
<> 144:ef7eb2e8f9f7 7353
<> 144:ef7eb2e8f9f7 7354 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
<> 144:ef7eb2e8f9f7 7355
<> 144:ef7eb2e8f9f7 7356 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
<> 144:ef7eb2e8f9f7 7357 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7358 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7359 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7360 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
<> 144:ef7eb2e8f9f7 7361 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
<> 144:ef7eb2e8f9f7 7362 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
<> 144:ef7eb2e8f9f7 7363
<> 144:ef7eb2e8f9f7 7364 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
<> 144:ef7eb2e8f9f7 7365 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7366 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7367 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7368 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7369 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
<> 144:ef7eb2e8f9f7 7370 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
<> 144:ef7eb2e8f9f7 7371 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
<> 144:ef7eb2e8f9f7 7372 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
<> 144:ef7eb2e8f9f7 7373 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
<> 144:ef7eb2e8f9f7 7374 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
<> 144:ef7eb2e8f9f7 7375 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
<> 144:ef7eb2e8f9f7 7376 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
<> 144:ef7eb2e8f9f7 7377 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
<> 144:ef7eb2e8f9f7 7378 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
<> 144:ef7eb2e8f9f7 7379 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
<> 144:ef7eb2e8f9f7 7380 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
<> 144:ef7eb2e8f9f7 7381 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
<> 144:ef7eb2e8f9f7 7382
<> 144:ef7eb2e8f9f7 7383 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
<> 144:ef7eb2e8f9f7 7384 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
<> 144:ef7eb2e8f9f7 7385 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
<> 144:ef7eb2e8f9f7 7386 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
<> 144:ef7eb2e8f9f7 7387 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
<> 144:ef7eb2e8f9f7 7388 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
<> 144:ef7eb2e8f9f7 7389
<> 144:ef7eb2e8f9f7 7390 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
<> 144:ef7eb2e8f9f7 7391 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7392 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7393 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7394 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7395 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7396 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
<> 144:ef7eb2e8f9f7 7397 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
<> 144:ef7eb2e8f9f7 7398
<> 144:ef7eb2e8f9f7 7399 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
<> 144:ef7eb2e8f9f7 7400 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 7401 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 7402 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 144:ef7eb2e8f9f7 7403 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 7404 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 7405 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 7406 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 144:ef7eb2e8f9f7 7407 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 7408
<> 144:ef7eb2e8f9f7 7409 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
<> 144:ef7eb2e8f9f7 7410 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
<> 144:ef7eb2e8f9f7 7411
<> 144:ef7eb2e8f9f7 7412 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
<> 144:ef7eb2e8f9f7 7413 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7414 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7415 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7416 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7417 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7418 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7419 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7420 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 7421
<> 144:ef7eb2e8f9f7 7422 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
<> 144:ef7eb2e8f9f7 7423 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7424 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7425 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7426 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7427 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7428 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7429 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7430 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 7431
<> 144:ef7eb2e8f9f7 7432 /******************** Bit definition forUSB_OTG_HAINT register ********************/
<> 144:ef7eb2e8f9f7 7433 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
<> 144:ef7eb2e8f9f7 7434
<> 144:ef7eb2e8f9f7 7435 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
<> 144:ef7eb2e8f9f7 7436 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 7437 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 7438 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
<> 144:ef7eb2e8f9f7 7439 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
<> 144:ef7eb2e8f9f7 7440 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
<> 144:ef7eb2e8f9f7 7441 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
<> 144:ef7eb2e8f9f7 7442 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 7443
<> 144:ef7eb2e8f9f7 7444 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
<> 144:ef7eb2e8f9f7 7445 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
<> 144:ef7eb2e8f9f7 7446 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
<> 144:ef7eb2e8f9f7 7447 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
<> 144:ef7eb2e8f9f7 7448 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
<> 144:ef7eb2e8f9f7 7449 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
<> 144:ef7eb2e8f9f7 7450 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
<> 144:ef7eb2e8f9f7 7451 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
<> 144:ef7eb2e8f9f7 7452 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
<> 144:ef7eb2e8f9f7 7453 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
<> 144:ef7eb2e8f9f7 7454 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
<> 144:ef7eb2e8f9f7 7455 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
<> 144:ef7eb2e8f9f7 7456 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
<> 144:ef7eb2e8f9f7 7457 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
<> 144:ef7eb2e8f9f7 7458 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
<> 144:ef7eb2e8f9f7 7459 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
<> 144:ef7eb2e8f9f7 7460 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
<> 144:ef7eb2e8f9f7 7461 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
<> 144:ef7eb2e8f9f7 7462 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
<> 144:ef7eb2e8f9f7 7463 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
<> 144:ef7eb2e8f9f7 7464 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
<> 144:ef7eb2e8f9f7 7465 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
<> 144:ef7eb2e8f9f7 7466 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
<> 144:ef7eb2e8f9f7 7467 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
<> 144:ef7eb2e8f9f7 7468 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
<> 144:ef7eb2e8f9f7 7469 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
<> 144:ef7eb2e8f9f7 7470 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
<> 144:ef7eb2e8f9f7 7471
<> 144:ef7eb2e8f9f7 7472 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
<> 144:ef7eb2e8f9f7 7473 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
<> 144:ef7eb2e8f9f7 7474 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
<> 144:ef7eb2e8f9f7 7475 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
<> 144:ef7eb2e8f9f7 7476 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
<> 144:ef7eb2e8f9f7 7477 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 7478 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
<> 144:ef7eb2e8f9f7 7479 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
<> 144:ef7eb2e8f9f7 7480 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
<> 144:ef7eb2e8f9f7 7481 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
<> 144:ef7eb2e8f9f7 7482 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
<> 144:ef7eb2e8f9f7 7483 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
<> 144:ef7eb2e8f9f7 7484 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
<> 144:ef7eb2e8f9f7 7485 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
<> 144:ef7eb2e8f9f7 7486 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
<> 144:ef7eb2e8f9f7 7487 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
<> 144:ef7eb2e8f9f7 7488 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
<> 144:ef7eb2e8f9f7 7489 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
<> 144:ef7eb2e8f9f7 7490 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
<> 144:ef7eb2e8f9f7 7491 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
<> 144:ef7eb2e8f9f7 7492 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
<> 144:ef7eb2e8f9f7 7493 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
<> 144:ef7eb2e8f9f7 7494 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 7495 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
<> 144:ef7eb2e8f9f7 7496 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
<> 144:ef7eb2e8f9f7 7497 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
<> 144:ef7eb2e8f9f7 7498 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
<> 144:ef7eb2e8f9f7 7499
<> 144:ef7eb2e8f9f7 7500 /******************** Bit definition forUSB_OTG_DAINT register ********************/
<> 144:ef7eb2e8f9f7 7501 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
<> 144:ef7eb2e8f9f7 7502 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
<> 144:ef7eb2e8f9f7 7503
<> 144:ef7eb2e8f9f7 7504 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
<> 144:ef7eb2e8f9f7 7505 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
<> 144:ef7eb2e8f9f7 7506
<> 144:ef7eb2e8f9f7 7507 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
<> 144:ef7eb2e8f9f7 7508 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 7509 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 7510 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 7511 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 7512
<> 144:ef7eb2e8f9f7 7513 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
<> 144:ef7eb2e8f9f7 7514 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 7515 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 7516
<> 144:ef7eb2e8f9f7 7517 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 7518
<> 144:ef7eb2e8f9f7 7519 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 144:ef7eb2e8f9f7 7520 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7521 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7522 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7523 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7524 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 144:ef7eb2e8f9f7 7525
<> 144:ef7eb2e8f9f7 7526 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 7527 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7528 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7529
<> 144:ef7eb2e8f9f7 7530 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 144:ef7eb2e8f9f7 7531 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7532 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7533 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7534 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7535
<> 144:ef7eb2e8f9f7 7536 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 7537 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7538 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7539 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7540 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7541
<> 144:ef7eb2e8f9f7 7542 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 144:ef7eb2e8f9f7 7543 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7544 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7545 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7546 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7547
<> 144:ef7eb2e8f9f7 7548 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 7549
<> 144:ef7eb2e8f9f7 7550 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 144:ef7eb2e8f9f7 7551 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7552 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7553 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7554 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7555 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 144:ef7eb2e8f9f7 7556
<> 144:ef7eb2e8f9f7 7557 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 7558 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7559 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7560
<> 144:ef7eb2e8f9f7 7561 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 144:ef7eb2e8f9f7 7562 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7563 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7564 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7565 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7566
<> 144:ef7eb2e8f9f7 7567 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 7568 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7569 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7570 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7571 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7572
<> 144:ef7eb2e8f9f7 7573 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 144:ef7eb2e8f9f7 7574 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7575 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7576 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7577 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7578
<> 144:ef7eb2e8f9f7 7579 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
<> 144:ef7eb2e8f9f7 7580 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
<> 144:ef7eb2e8f9f7 7581
<> 144:ef7eb2e8f9f7 7582 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
<> 144:ef7eb2e8f9f7 7583 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
<> 144:ef7eb2e8f9f7 7584
<> 144:ef7eb2e8f9f7 7585 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 7586 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
<> 144:ef7eb2e8f9f7 7587 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
<> 144:ef7eb2e8f9f7 7588 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
<> 144:ef7eb2e8f9f7 7589 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
<> 144:ef7eb2e8f9f7 7590
<> 144:ef7eb2e8f9f7 7591 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
<> 144:ef7eb2e8f9f7 7592 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
<> 144:ef7eb2e8f9f7 7593
<> 144:ef7eb2e8f9f7 7594 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
<> 144:ef7eb2e8f9f7 7595 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
<> 144:ef7eb2e8f9f7 7596
<> 144:ef7eb2e8f9f7 7597 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
<> 144:ef7eb2e8f9f7 7598 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7599 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7600 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7601 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7602 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7603 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7604 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7605 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 7606
<> 144:ef7eb2e8f9f7 7607 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
<> 144:ef7eb2e8f9f7 7608 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7609 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7610 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7611 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7612 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7613 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7614 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7615
<> 144:ef7eb2e8f9f7 7616 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
<> 144:ef7eb2e8f9f7 7617 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
<> 144:ef7eb2e8f9f7 7618 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
<> 144:ef7eb2e8f9f7 7619
<> 144:ef7eb2e8f9f7 7620 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
<> 144:ef7eb2e8f9f7 7621 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7622 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7623 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7624 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7625 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7626 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7627 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7628 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 7629 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 7630 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
<> 144:ef7eb2e8f9f7 7631
<> 144:ef7eb2e8f9f7 7632 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
<> 144:ef7eb2e8f9f7 7633 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7634 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7635 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7636 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7637 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7638 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7639 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7640 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 7641 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 7642 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
<> 144:ef7eb2e8f9f7 7643
<> 144:ef7eb2e8f9f7 7644 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
<> 144:ef7eb2e8f9f7 7645 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
<> 144:ef7eb2e8f9f7 7646
<> 144:ef7eb2e8f9f7 7647 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
<> 144:ef7eb2e8f9f7 7648 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
<> 144:ef7eb2e8f9f7 7649 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
<> 144:ef7eb2e8f9f7 7650
<> 144:ef7eb2e8f9f7 7651 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
<> 144:ef7eb2e8f9f7 7652 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
<> 144:ef7eb2e8f9f7 7653 #define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
<> 144:ef7eb2e8f9f7 7654 #define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
<> 144:ef7eb2e8f9f7 7655 #define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
<> 144:ef7eb2e8f9f7 7656 #define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
<> 144:ef7eb2e8f9f7 7657 #define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
<> 144:ef7eb2e8f9f7 7658
<> 144:ef7eb2e8f9f7 7659 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
<> 144:ef7eb2e8f9f7 7660 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
<> 144:ef7eb2e8f9f7 7661 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
<> 144:ef7eb2e8f9f7 7662
<> 144:ef7eb2e8f9f7 7663 /******************** Bit definition forUSB_OTG_CID register ********************/
<> 144:ef7eb2e8f9f7 7664 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
<> 144:ef7eb2e8f9f7 7665
<> 144:ef7eb2e8f9f7 7666 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
<> 144:ef7eb2e8f9f7 7667 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 7668 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 7669 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 144:ef7eb2e8f9f7 7670 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 7671 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 7672 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 7673 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 144:ef7eb2e8f9f7 7674 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 7675 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 144:ef7eb2e8f9f7 7676
<> 144:ef7eb2e8f9f7 7677 /******************** Bit definition forUSB_OTG_HPRT register ********************/
<> 144:ef7eb2e8f9f7 7678 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
<> 144:ef7eb2e8f9f7 7679 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
<> 144:ef7eb2e8f9f7 7680 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
<> 144:ef7eb2e8f9f7 7681 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
<> 144:ef7eb2e8f9f7 7682 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
<> 144:ef7eb2e8f9f7 7683 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
<> 144:ef7eb2e8f9f7 7684 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
<> 144:ef7eb2e8f9f7 7685 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
<> 144:ef7eb2e8f9f7 7686 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
<> 144:ef7eb2e8f9f7 7687
<> 144:ef7eb2e8f9f7 7688 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
<> 144:ef7eb2e8f9f7 7689 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7690 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7691 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
<> 144:ef7eb2e8f9f7 7692
<> 144:ef7eb2e8f9f7 7693 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
<> 144:ef7eb2e8f9f7 7694 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7695 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7696 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7697 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7698
<> 144:ef7eb2e8f9f7 7699 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
<> 144:ef7eb2e8f9f7 7700 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7701 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7702
<> 144:ef7eb2e8f9f7 7703 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
<> 144:ef7eb2e8f9f7 7704 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 7705 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 7706 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
<> 144:ef7eb2e8f9f7 7707 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 7708 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 7709 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 7710 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
<> 144:ef7eb2e8f9f7 7711 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 7712 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
<> 144:ef7eb2e8f9f7 7713 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 144:ef7eb2e8f9f7 7714 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
<> 144:ef7eb2e8f9f7 7715
<> 144:ef7eb2e8f9f7 7716 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
<> 144:ef7eb2e8f9f7 7717 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
<> 144:ef7eb2e8f9f7 7718 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
<> 144:ef7eb2e8f9f7 7719
<> 144:ef7eb2e8f9f7 7720 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
<> 144:ef7eb2e8f9f7 7721 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 144:ef7eb2e8f9f7 7722 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 144:ef7eb2e8f9f7 7723 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
<> 144:ef7eb2e8f9f7 7724 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 144:ef7eb2e8f9f7 7725
<> 144:ef7eb2e8f9f7 7726 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 7727 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7728 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7729 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 144:ef7eb2e8f9f7 7730
<> 144:ef7eb2e8f9f7 7731 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
<> 144:ef7eb2e8f9f7 7732 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7733 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7734 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7735 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7736 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 144:ef7eb2e8f9f7 7737 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 144:ef7eb2e8f9f7 7738 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 144:ef7eb2e8f9f7 7739 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 144:ef7eb2e8f9f7 7740 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 144:ef7eb2e8f9f7 7741 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 144:ef7eb2e8f9f7 7742
<> 144:ef7eb2e8f9f7 7743 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
<> 144:ef7eb2e8f9f7 7744 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 144:ef7eb2e8f9f7 7745
<> 144:ef7eb2e8f9f7 7746 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 7747 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7748 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7749 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7750 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7751 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
<> 144:ef7eb2e8f9f7 7752 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
<> 144:ef7eb2e8f9f7 7753
<> 144:ef7eb2e8f9f7 7754 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 7755 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7756 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7757
<> 144:ef7eb2e8f9f7 7758 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
<> 144:ef7eb2e8f9f7 7759 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7760 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7761
<> 144:ef7eb2e8f9f7 7762 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
<> 144:ef7eb2e8f9f7 7763 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7764 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7765 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7766 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7767 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7768 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7769 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7770 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
<> 144:ef7eb2e8f9f7 7771 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
<> 144:ef7eb2e8f9f7 7772 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
<> 144:ef7eb2e8f9f7 7773
<> 144:ef7eb2e8f9f7 7774 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
<> 144:ef7eb2e8f9f7 7775
<> 144:ef7eb2e8f9f7 7776 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
<> 144:ef7eb2e8f9f7 7777 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7778 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7779 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7780 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7781 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7782 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7783 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7784
<> 144:ef7eb2e8f9f7 7785 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
<> 144:ef7eb2e8f9f7 7786 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7787 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7788 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7789 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7790 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7791 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7792 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7793
<> 144:ef7eb2e8f9f7 7794 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
<> 144:ef7eb2e8f9f7 7795 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7796 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7797 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
<> 144:ef7eb2e8f9f7 7798 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
<> 144:ef7eb2e8f9f7 7799
<> 144:ef7eb2e8f9f7 7800 /******************** Bit definition forUSB_OTG_HCINT register ********************/
<> 144:ef7eb2e8f9f7 7801 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
<> 144:ef7eb2e8f9f7 7802 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
<> 144:ef7eb2e8f9f7 7803 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
<> 144:ef7eb2e8f9f7 7804 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
<> 144:ef7eb2e8f9f7 7805 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
<> 144:ef7eb2e8f9f7 7806 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
<> 144:ef7eb2e8f9f7 7807 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
<> 144:ef7eb2e8f9f7 7808 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
<> 144:ef7eb2e8f9f7 7809 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
<> 144:ef7eb2e8f9f7 7810 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
<> 144:ef7eb2e8f9f7 7811 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
<> 144:ef7eb2e8f9f7 7812
<> 144:ef7eb2e8f9f7 7813 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
<> 144:ef7eb2e8f9f7 7814 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 144:ef7eb2e8f9f7 7815 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 144:ef7eb2e8f9f7 7816 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
<> 144:ef7eb2e8f9f7 7817 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
<> 144:ef7eb2e8f9f7 7818 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
<> 144:ef7eb2e8f9f7 7819 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
<> 144:ef7eb2e8f9f7 7820 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
<> 144:ef7eb2e8f9f7 7821 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
<> 144:ef7eb2e8f9f7 7822 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
<> 144:ef7eb2e8f9f7 7823 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
<> 144:ef7eb2e8f9f7 7824 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
<> 144:ef7eb2e8f9f7 7825
<> 144:ef7eb2e8f9f7 7826 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
<> 144:ef7eb2e8f9f7 7827 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
<> 144:ef7eb2e8f9f7 7828 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
<> 144:ef7eb2e8f9f7 7829 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
<> 144:ef7eb2e8f9f7 7830 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
<> 144:ef7eb2e8f9f7 7831 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
<> 144:ef7eb2e8f9f7 7832 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
<> 144:ef7eb2e8f9f7 7833 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
<> 144:ef7eb2e8f9f7 7834 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
<> 144:ef7eb2e8f9f7 7835 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
<> 144:ef7eb2e8f9f7 7836 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
<> 144:ef7eb2e8f9f7 7837 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
<> 144:ef7eb2e8f9f7 7838
<> 144:ef7eb2e8f9f7 7839 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 144:ef7eb2e8f9f7 7840
<> 144:ef7eb2e8f9f7 7841 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 7842 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 7843 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 7844 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
<> 144:ef7eb2e8f9f7 7845 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 7846 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 7847 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
<> 144:ef7eb2e8f9f7 7848 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 7849 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7850 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7851
<> 144:ef7eb2e8f9f7 7852 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
<> 144:ef7eb2e8f9f7 7853 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 144:ef7eb2e8f9f7 7854
<> 144:ef7eb2e8f9f7 7855 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
<> 144:ef7eb2e8f9f7 7856 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 144:ef7eb2e8f9f7 7857
<> 144:ef7eb2e8f9f7 7858 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
<> 144:ef7eb2e8f9f7 7859 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
<> 144:ef7eb2e8f9f7 7860
<> 144:ef7eb2e8f9f7 7861 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
<> 144:ef7eb2e8f9f7 7862 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
<> 144:ef7eb2e8f9f7 7863 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
<> 144:ef7eb2e8f9f7 7864
<> 144:ef7eb2e8f9f7 7865 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
<> 144:ef7eb2e8f9f7 7866
<> 144:ef7eb2e8f9f7 7867 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7868 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 144:ef7eb2e8f9f7 7869 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 144:ef7eb2e8f9f7 7870 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 144:ef7eb2e8f9f7 7871 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 144:ef7eb2e8f9f7 7872 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 7873 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7874 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7875 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
<> 144:ef7eb2e8f9f7 7876 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 144:ef7eb2e8f9f7 7877 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 144:ef7eb2e8f9f7 7878 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 144:ef7eb2e8f9f7 7879 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 144:ef7eb2e8f9f7 7880 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 144:ef7eb2e8f9f7 7881
<> 144:ef7eb2e8f9f7 7882 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
<> 144:ef7eb2e8f9f7 7883 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 144:ef7eb2e8f9f7 7884 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 144:ef7eb2e8f9f7 7885 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
<> 144:ef7eb2e8f9f7 7886 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
<> 144:ef7eb2e8f9f7 7887 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
<> 144:ef7eb2e8f9f7 7888 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
<> 144:ef7eb2e8f9f7 7889
<> 144:ef7eb2e8f9f7 7890 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
<> 144:ef7eb2e8f9f7 7891
<> 144:ef7eb2e8f9f7 7892 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 7893 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 7894
<> 144:ef7eb2e8f9f7 7895 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
<> 144:ef7eb2e8f9f7 7896 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7897 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7898
<> 144:ef7eb2e8f9f7 7899 /******************** Bit definition for PCGCCTL register ********************/
<> 144:ef7eb2e8f9f7 7900 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
<> 144:ef7eb2e8f9f7 7901 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7902 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7903
<> 144:ef7eb2e8f9f7 7904 /**
<> 144:ef7eb2e8f9f7 7905 * @}
<> 144:ef7eb2e8f9f7 7906 */
<> 144:ef7eb2e8f9f7 7907
<> 144:ef7eb2e8f9f7 7908 /**
<> 144:ef7eb2e8f9f7 7909 * @}
<> 144:ef7eb2e8f9f7 7910 */
<> 144:ef7eb2e8f9f7 7911
<> 144:ef7eb2e8f9f7 7912 /** @addtogroup Exported_macros
<> 144:ef7eb2e8f9f7 7913 * @{
<> 144:ef7eb2e8f9f7 7914 */
<> 144:ef7eb2e8f9f7 7915
<> 144:ef7eb2e8f9f7 7916 /******************************* ADC Instances ********************************/
<> 144:ef7eb2e8f9f7 7917 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
<> 144:ef7eb2e8f9f7 7918 ((INSTANCE) == ADC2) || \
<> 144:ef7eb2e8f9f7 7919 ((INSTANCE) == ADC3))
<> 144:ef7eb2e8f9f7 7920
<> 144:ef7eb2e8f9f7 7921 /******************************* CAN Instances ********************************/
<> 144:ef7eb2e8f9f7 7922 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
<> 144:ef7eb2e8f9f7 7923 ((INSTANCE) == CAN2))
<> 144:ef7eb2e8f9f7 7924
<> 144:ef7eb2e8f9f7 7925 /******************************* CRC Instances ********************************/
<> 144:ef7eb2e8f9f7 7926 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 144:ef7eb2e8f9f7 7927
<> 144:ef7eb2e8f9f7 7928 /******************************* DAC Instances ********************************/
<> 144:ef7eb2e8f9f7 7929 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
<> 144:ef7eb2e8f9f7 7930
<> 144:ef7eb2e8f9f7 7931 /******************************* DCMI Instances *******************************/
<> 144:ef7eb2e8f9f7 7932 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
<> 144:ef7eb2e8f9f7 7933
<> 144:ef7eb2e8f9f7 7934 /******************************** DMA Instances *******************************/
<> 144:ef7eb2e8f9f7 7935 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
<> 144:ef7eb2e8f9f7 7936 ((INSTANCE) == DMA1_Stream1) || \
<> 144:ef7eb2e8f9f7 7937 ((INSTANCE) == DMA1_Stream2) || \
<> 144:ef7eb2e8f9f7 7938 ((INSTANCE) == DMA1_Stream3) || \
<> 144:ef7eb2e8f9f7 7939 ((INSTANCE) == DMA1_Stream4) || \
<> 144:ef7eb2e8f9f7 7940 ((INSTANCE) == DMA1_Stream5) || \
<> 144:ef7eb2e8f9f7 7941 ((INSTANCE) == DMA1_Stream6) || \
<> 144:ef7eb2e8f9f7 7942 ((INSTANCE) == DMA1_Stream7) || \
<> 144:ef7eb2e8f9f7 7943 ((INSTANCE) == DMA2_Stream0) || \
<> 144:ef7eb2e8f9f7 7944 ((INSTANCE) == DMA2_Stream1) || \
<> 144:ef7eb2e8f9f7 7945 ((INSTANCE) == DMA2_Stream2) || \
<> 144:ef7eb2e8f9f7 7946 ((INSTANCE) == DMA2_Stream3) || \
<> 144:ef7eb2e8f9f7 7947 ((INSTANCE) == DMA2_Stream4) || \
<> 144:ef7eb2e8f9f7 7948 ((INSTANCE) == DMA2_Stream5) || \
<> 144:ef7eb2e8f9f7 7949 ((INSTANCE) == DMA2_Stream6) || \
<> 144:ef7eb2e8f9f7 7950 ((INSTANCE) == DMA2_Stream7))
<> 144:ef7eb2e8f9f7 7951
<> 144:ef7eb2e8f9f7 7952 /******************************* GPIO Instances *******************************/
<> 144:ef7eb2e8f9f7 7953 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 144:ef7eb2e8f9f7 7954 ((INSTANCE) == GPIOB) || \
<> 144:ef7eb2e8f9f7 7955 ((INSTANCE) == GPIOC) || \
<> 144:ef7eb2e8f9f7 7956 ((INSTANCE) == GPIOD) || \
<> 144:ef7eb2e8f9f7 7957 ((INSTANCE) == GPIOE) || \
<> 144:ef7eb2e8f9f7 7958 ((INSTANCE) == GPIOF) || \
<> 144:ef7eb2e8f9f7 7959 ((INSTANCE) == GPIOG) || \
<> 144:ef7eb2e8f9f7 7960 ((INSTANCE) == GPIOH) || \
<> 144:ef7eb2e8f9f7 7961 ((INSTANCE) == GPIOI))
<> 144:ef7eb2e8f9f7 7962
<> 144:ef7eb2e8f9f7 7963 /******************************** I2C Instances *******************************/
<> 144:ef7eb2e8f9f7 7964 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 144:ef7eb2e8f9f7 7965 ((INSTANCE) == I2C2) || \
<> 144:ef7eb2e8f9f7 7966 ((INSTANCE) == I2C3))
<> 144:ef7eb2e8f9f7 7967
<> 144:ef7eb2e8f9f7 7968 /******************************* SMBUS Instances ******************************/
<> 144:ef7eb2e8f9f7 7969 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
<> 144:ef7eb2e8f9f7 7970
<> 144:ef7eb2e8f9f7 7971 /******************************** I2S Instances *******************************/
<> 144:ef7eb2e8f9f7 7972 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
<> 144:ef7eb2e8f9f7 7973 ((INSTANCE) == SPI3))
<> 144:ef7eb2e8f9f7 7974
<> 144:ef7eb2e8f9f7 7975 /******************************* RNG Instances ********************************/
<> 144:ef7eb2e8f9f7 7976 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
<> 144:ef7eb2e8f9f7 7977
<> 144:ef7eb2e8f9f7 7978 /****************************** RTC Instances *********************************/
<> 144:ef7eb2e8f9f7 7979 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 144:ef7eb2e8f9f7 7980
<> 144:ef7eb2e8f9f7 7981 /******************************** SPI Instances *******************************/
<> 144:ef7eb2e8f9f7 7982 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
<> 144:ef7eb2e8f9f7 7983 ((INSTANCE) == SPI2) || \
<> 144:ef7eb2e8f9f7 7984 ((INSTANCE) == SPI3))
<> 144:ef7eb2e8f9f7 7985
<> 144:ef7eb2e8f9f7 7986 /****************** TIM Instances : All supported instances *******************/
<> 144:ef7eb2e8f9f7 7987 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 7988 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 7989 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 7990 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 7991 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 7992 ((INSTANCE) == TIM6) || \
<> 144:ef7eb2e8f9f7 7993 ((INSTANCE) == TIM7) || \
<> 144:ef7eb2e8f9f7 7994 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 7995 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 7996 ((INSTANCE) == TIM10) || \
<> 144:ef7eb2e8f9f7 7997 ((INSTANCE) == TIM11) || \
<> 144:ef7eb2e8f9f7 7998 ((INSTANCE) == TIM12) || \
<> 144:ef7eb2e8f9f7 7999 ((INSTANCE) == TIM13) || \
<> 144:ef7eb2e8f9f7 8000 ((INSTANCE) == TIM14))
<> 144:ef7eb2e8f9f7 8001
<> 144:ef7eb2e8f9f7 8002 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 144:ef7eb2e8f9f7 8003 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8004 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8005 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8006 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8007 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8008 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 8009 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 8010 ((INSTANCE) == TIM10) || \
<> 144:ef7eb2e8f9f7 8011 ((INSTANCE) == TIM11) || \
<> 144:ef7eb2e8f9f7 8012 ((INSTANCE) == TIM12) || \
<> 144:ef7eb2e8f9f7 8013 ((INSTANCE) == TIM13) || \
<> 144:ef7eb2e8f9f7 8014 ((INSTANCE) == TIM14))
<> 144:ef7eb2e8f9f7 8015
<> 144:ef7eb2e8f9f7 8016 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 8017 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8018 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8019 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8020 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8021 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8022 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 8023 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 8024 ((INSTANCE) == TIM12))
<> 144:ef7eb2e8f9f7 8025
<> 144:ef7eb2e8f9f7 8026 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 8027 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8028 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8029 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8030 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8031 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8032 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8033
<> 144:ef7eb2e8f9f7 8034 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 8035 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8036 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8037 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8038 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8039 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8040 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8041
<> 144:ef7eb2e8f9f7 8042 /******************** TIM Instances : Advanced-control timers *****************/
<> 144:ef7eb2e8f9f7 8043 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8044 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8045
<> 144:ef7eb2e8f9f7 8046 /******************* TIM Instances : Timer input XOR function *****************/
<> 144:ef7eb2e8f9f7 8047 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8048 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8049 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8050 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8051 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8052 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8053
<> 144:ef7eb2e8f9f7 8054 /****************** TIM Instances : DMA requests generation (UDE) *************/
<> 144:ef7eb2e8f9f7 8055 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8056 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8057 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8058 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8059 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8060 ((INSTANCE) == TIM6) || \
<> 144:ef7eb2e8f9f7 8061 ((INSTANCE) == TIM7) || \
<> 144:ef7eb2e8f9f7 8062 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8063
<> 144:ef7eb2e8f9f7 8064 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
<> 144:ef7eb2e8f9f7 8065 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8066 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8067 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8068 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8069 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8070 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8071
<> 144:ef7eb2e8f9f7 8072 /************ TIM Instances : DMA requests generation (COMDE) *****************/
<> 144:ef7eb2e8f9f7 8073 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8074 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8075 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8076 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8077 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8078 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8079
<> 144:ef7eb2e8f9f7 8080 /******************** TIM Instances : DMA burst feature ***********************/
<> 144:ef7eb2e8f9f7 8081 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8082 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8083 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8084 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8085 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8086 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8087
<> 144:ef7eb2e8f9f7 8088 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
<> 144:ef7eb2e8f9f7 8089 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8090 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8091 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8092 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8093 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8094 ((INSTANCE) == TIM6) || \
<> 144:ef7eb2e8f9f7 8095 ((INSTANCE) == TIM7) || \
<> 144:ef7eb2e8f9f7 8096 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 8097 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 8098 ((INSTANCE) == TIM12))
<> 144:ef7eb2e8f9f7 8099
<> 144:ef7eb2e8f9f7 8100 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 144:ef7eb2e8f9f7 8101 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8102 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8103 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8104 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8105 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8106 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 8107 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 8108 ((INSTANCE) == TIM12))
<> 144:ef7eb2e8f9f7 8109
<> 144:ef7eb2e8f9f7 8110 /********************** TIM Instances : 32 bit Counter ************************/
<> 144:ef7eb2e8f9f7 8111 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8112 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 8113
<> 144:ef7eb2e8f9f7 8114 /***************** TIM Instances : external trigger input available ***********/
<> 144:ef7eb2e8f9f7 8115 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 8116 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8117 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 8118 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 8119 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8120 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 8121
<> 144:ef7eb2e8f9f7 8122 /****************** TIM Instances : remapping capability **********************/
<> 144:ef7eb2e8f9f7 8123 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 8124 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 8125 ((INSTANCE) == TIM11))
<> 144:ef7eb2e8f9f7 8126
<> 144:ef7eb2e8f9f7 8127 /******************* TIM Instances : output(s) available **********************/
<> 144:ef7eb2e8f9f7 8128 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 8129 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 8130 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8131 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8132 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 8133 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 8134 || \
<> 144:ef7eb2e8f9f7 8135 (((INSTANCE) == TIM2) && \
<> 144:ef7eb2e8f9f7 8136 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8137 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8138 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 8139 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 8140 || \
<> 144:ef7eb2e8f9f7 8141 (((INSTANCE) == TIM3) && \
<> 144:ef7eb2e8f9f7 8142 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8143 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8144 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 8145 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 8146 || \
<> 144:ef7eb2e8f9f7 8147 (((INSTANCE) == TIM4) && \
<> 144:ef7eb2e8f9f7 8148 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8149 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8150 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 8151 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 8152 || \
<> 144:ef7eb2e8f9f7 8153 (((INSTANCE) == TIM5) && \
<> 144:ef7eb2e8f9f7 8154 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8155 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8156 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 8157 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 8158 || \
<> 144:ef7eb2e8f9f7 8159 (((INSTANCE) == TIM8) && \
<> 144:ef7eb2e8f9f7 8160 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8161 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8162 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 8163 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 8164 || \
<> 144:ef7eb2e8f9f7 8165 (((INSTANCE) == TIM9) && \
<> 144:ef7eb2e8f9f7 8166 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8167 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 8168 || \
<> 144:ef7eb2e8f9f7 8169 (((INSTANCE) == TIM10) && \
<> 144:ef7eb2e8f9f7 8170 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 8171 || \
<> 144:ef7eb2e8f9f7 8172 (((INSTANCE) == TIM11) && \
<> 144:ef7eb2e8f9f7 8173 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 8174 || \
<> 144:ef7eb2e8f9f7 8175 (((INSTANCE) == TIM12) && \
<> 144:ef7eb2e8f9f7 8176 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8177 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 8178 || \
<> 144:ef7eb2e8f9f7 8179 (((INSTANCE) == TIM13) && \
<> 144:ef7eb2e8f9f7 8180 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 8181 || \
<> 144:ef7eb2e8f9f7 8182 (((INSTANCE) == TIM14) && \
<> 144:ef7eb2e8f9f7 8183 (((CHANNEL) == TIM_CHANNEL_1))))
<> 144:ef7eb2e8f9f7 8184
<> 144:ef7eb2e8f9f7 8185 /************ TIM Instances : complementary output(s) available ***************/
<> 144:ef7eb2e8f9f7 8186 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 8187 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 8188 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8189 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8190 ((CHANNEL) == TIM_CHANNEL_3))) \
<> 144:ef7eb2e8f9f7 8191 || \
<> 144:ef7eb2e8f9f7 8192 (((INSTANCE) == TIM8) && \
<> 144:ef7eb2e8f9f7 8193 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 8194 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 8195 ((CHANNEL) == TIM_CHANNEL_3))))
<> 144:ef7eb2e8f9f7 8196
<> 144:ef7eb2e8f9f7 8197 /******************** USART Instances : Synchronous mode **********************/
<> 144:ef7eb2e8f9f7 8198 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 8199 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 8200 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 8201 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 8202
<> 144:ef7eb2e8f9f7 8203 /******************** UART Instances : Asynchronous mode **********************/
<> 144:ef7eb2e8f9f7 8204 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 8205 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 8206 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 8207 ((INSTANCE) == UART4) || \
<> 144:ef7eb2e8f9f7 8208 ((INSTANCE) == UART5) || \
<> 144:ef7eb2e8f9f7 8209 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 8210
<> 144:ef7eb2e8f9f7 8211 /****************** UART Instances : Hardware Flow control ********************/
<> 144:ef7eb2e8f9f7 8212 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 8213 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 8214 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 8215 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 8216
<> 144:ef7eb2e8f9f7 8217 /********************* UART Instances : Smart card mode ***********************/
<> 144:ef7eb2e8f9f7 8218 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 8219 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 8220 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 8221 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 8222
<> 144:ef7eb2e8f9f7 8223 /*********************** UART Instances : IRDA mode ***************************/
<> 144:ef7eb2e8f9f7 8224 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 8225 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 8226 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 8227 ((INSTANCE) == UART4) || \
<> 144:ef7eb2e8f9f7 8228 ((INSTANCE) == UART5) || \
<> 144:ef7eb2e8f9f7 8229 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 8230
<> 144:ef7eb2e8f9f7 8231 /*********************** PCD Instances ****************************************/
<> 144:ef7eb2e8f9f7 8232 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
<> 144:ef7eb2e8f9f7 8233 ((INSTANCE) == USB_OTG_HS))
<> 144:ef7eb2e8f9f7 8234
<> 144:ef7eb2e8f9f7 8235 /*********************** HCD Instances ****************************************/
<> 144:ef7eb2e8f9f7 8236 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
<> 144:ef7eb2e8f9f7 8237 ((INSTANCE) == USB_OTG_HS))
<> 144:ef7eb2e8f9f7 8238
<> 144:ef7eb2e8f9f7 8239 /****************************** IWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 8240 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 144:ef7eb2e8f9f7 8241
<> 144:ef7eb2e8f9f7 8242 /****************************** WWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 8243 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 144:ef7eb2e8f9f7 8244
<> 144:ef7eb2e8f9f7 8245 /****************************** SDIO Instances ********************************/
<> 144:ef7eb2e8f9f7 8246 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
<> 144:ef7eb2e8f9f7 8247
<> 144:ef7eb2e8f9f7 8248 /****************************** USB Exported Constants ************************/
<> 144:ef7eb2e8f9f7 8249 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
<> 144:ef7eb2e8f9f7 8250 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
<> 144:ef7eb2e8f9f7 8251 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
<> 144:ef7eb2e8f9f7 8252 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
<> 144:ef7eb2e8f9f7 8253
<> 144:ef7eb2e8f9f7 8254 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
<> 144:ef7eb2e8f9f7 8255 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
<> 144:ef7eb2e8f9f7 8256 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
<> 144:ef7eb2e8f9f7 8257 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
<> 144:ef7eb2e8f9f7 8258
<> 144:ef7eb2e8f9f7 8259 /**
<> 144:ef7eb2e8f9f7 8260 * @}
<> 144:ef7eb2e8f9f7 8261 */
<> 144:ef7eb2e8f9f7 8262
<> 144:ef7eb2e8f9f7 8263 /**
<> 144:ef7eb2e8f9f7 8264 * @}
<> 144:ef7eb2e8f9f7 8265 */
<> 144:ef7eb2e8f9f7 8266
<> 144:ef7eb2e8f9f7 8267 /**
<> 144:ef7eb2e8f9f7 8268 * @}
<> 144:ef7eb2e8f9f7 8269 */
<> 144:ef7eb2e8f9f7 8270
<> 144:ef7eb2e8f9f7 8271 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 8272 }
<> 144:ef7eb2e8f9f7 8273 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 8274
<> 144:ef7eb2e8f9f7 8275 #endif /* __STM32F207xx_H */
<> 144:ef7eb2e8f9f7 8276
<> 144:ef7eb2e8f9f7 8277 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 8278