mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_spi.h@144:ef7eb2e8f9f7
Child:
154:37f96f9d4de2
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_spi.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SPI HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup SPI_Exported_Types SPI Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief SPI Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref SPI_mode */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref SPI_Direction_mode */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t DataSize; /*!< Specifies the SPI data size.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref SPI_data_size */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref SPI_Clock_Polarity */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref SPI_Clock_Phase */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
<> 144:ef7eb2e8f9f7 83 hardware (NSS pin) or by software using the SSI bit.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref SPI_Slave_Select_management */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
<> 144:ef7eb2e8f9f7 87 used to configure the transmit and receive SCK clock.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 144:ef7eb2e8f9f7 89 @note The communication clock is derived from the master
<> 144:ef7eb2e8f9f7 90 clock. The slave clock does not need to be set */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref SPI_TI_mode */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref SPI_CRC_Calculation */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
<> 144:ef7eb2e8f9f7 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 }SPI_InitTypeDef;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief HAL SPI State structure definition
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 typedef enum
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 112 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
<> 144:ef7eb2e8f9f7 113 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
<> 144:ef7eb2e8f9f7 114 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 115 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 116 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
<> 144:ef7eb2e8f9f7 117 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 }HAL_SPI_StateTypeDef;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @brief SPI handle Structure definition
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 typedef struct __SPI_HandleTypeDef
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 SPI_TypeDef *Instance; /*!< SPI registers base address */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 SPI_InitTypeDef Init; /*!< SPI communication parameters */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 uint16_t TxXferSize; /*!< SPI Tx transfer size */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 uint16_t RxXferSize; /*!< SPI Rx transfer size */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 HAL_LockTypeDef Lock; /*!< SPI locking object */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 __IO uint32_t ErrorCode; /*!< SPI Error code */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 }SPI_HandleTypeDef;
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @defgroup SPI_Exported_Constants SPI Exported Constants
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /** @defgroup SPI_Error_Codes SPI Error Codes
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 #define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */
<> 144:ef7eb2e8f9f7 173 #define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */
<> 144:ef7eb2e8f9f7 174 #define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */
<> 144:ef7eb2e8f9f7 175 #define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */
<> 144:ef7eb2e8f9f7 176 #define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 177 #define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @}
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /** @defgroup SPI_mode SPI mode
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 189 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @}
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /** @defgroup SPI_Direction_mode SPI Direction mode
<> 144:ef7eb2e8f9f7 196 * @{
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 199 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
<> 144:ef7eb2e8f9f7 200 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @}
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** @defgroup SPI_data_size SPI data size
<> 144:ef7eb2e8f9f7 207 * @{
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 210 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 220 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @}
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /** @defgroup SPI_Clock_Phase SPI Clock Phase
<> 144:ef7eb2e8f9f7 227 * @{
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 230 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @}
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
<> 144:ef7eb2e8f9f7 237 * @{
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 #define SPI_NSS_SOFT SPI_CR1_SSM
<> 144:ef7eb2e8f9f7 240 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 241 #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 251 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0)
<> 144:ef7eb2e8f9f7 252 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1)
<> 144:ef7eb2e8f9f7 253 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 144:ef7eb2e8f9f7 254 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2)
<> 144:ef7eb2e8f9f7 255 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
<> 144:ef7eb2e8f9f7 256 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
<> 144:ef7eb2e8f9f7 257 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 267 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @defgroup SPI_TI_mode SPI TI mode disable
<> 144:ef7eb2e8f9f7 274 * @brief SPI TI Mode not supported for STM32F1xx family
<> 144:ef7eb2e8f9f7 275 * @{
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 287 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @}
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 #define SPI_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 297 #define SPI_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 298 #define SPI_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup SPI_Flag_definition SPI Flag definition
<> 144:ef7eb2e8f9f7 304 * @{
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 #define SPI_FLAG_RXNE SPI_SR_RXNE
<> 144:ef7eb2e8f9f7 307 #define SPI_FLAG_TXE SPI_SR_TXE
<> 144:ef7eb2e8f9f7 308 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
<> 144:ef7eb2e8f9f7 309 #define SPI_FLAG_MODF SPI_SR_MODF
<> 144:ef7eb2e8f9f7 310 #define SPI_FLAG_OVR SPI_SR_OVR
<> 144:ef7eb2e8f9f7 311 #define SPI_FLAG_BSY SPI_SR_BSY
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @}
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 323 /** @defgroup SPI_Private_Constants SPI Private Constants
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 #define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */
<> 144:ef7eb2e8f9f7 327 #define SPI_VALID_CRC_ERROR 1 /* CRC error is true */
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @}
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 334 /** @defgroup SPI_Exported_Macros SPI Exported Macros
<> 144:ef7eb2e8f9f7 335 * @{
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /** @brief Reset SPI handle state
<> 144:ef7eb2e8f9f7 339 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 340 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 341 * @retval None
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /** @brief Enable the specified SPI interrupts.
<> 144:ef7eb2e8f9f7 346 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 347 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 348 * @param __INTERRUPT__: specifies the interrupt source to enable.
<> 144:ef7eb2e8f9f7 349 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 350 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 351 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 352 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 353 * @retval None
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** @brief Disable the specified SPI interrupts.
<> 144:ef7eb2e8f9f7 358 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 359 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 360 * @param __INTERRUPT__: specifies the interrupt source to disable.
<> 144:ef7eb2e8f9f7 361 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 362 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 363 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 364 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 365 * @retval None
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 370 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 371 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 372 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
<> 144:ef7eb2e8f9f7 373 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 374 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 375 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 376 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 377 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /** @brief Check whether the specified SPI flag is set or not.
<> 144:ef7eb2e8f9f7 382 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 383 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 384 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 385 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 386 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 387 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 388 * @arg SPI_FLAG_CRCERR: CRC error flag
<> 144:ef7eb2e8f9f7 389 * @arg SPI_FLAG_MODF: Mode fault flag
<> 144:ef7eb2e8f9f7 390 * @arg SPI_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 391 * @arg SPI_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 392 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /** @brief Clear the SPI CRCERR pending flag.
<> 144:ef7eb2e8f9f7 397 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 398 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 399 * @retval None
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /** @brief Clear the SPI MODF pending flag.
<> 144:ef7eb2e8f9f7 404 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 405 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 406 * @retval None
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 409 do{ \
<> 144:ef7eb2e8f9f7 410 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 411 tmpreg = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 412 tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
<> 144:ef7eb2e8f9f7 413 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 414 }while(0)
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /** @brief Clear the SPI OVR pending flag.
<> 144:ef7eb2e8f9f7 417 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 418 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 419 * @retval None
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 422 do{ \
<> 144:ef7eb2e8f9f7 423 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 424 tmpreg = (__HANDLE__)->Instance->DR; \
<> 144:ef7eb2e8f9f7 425 tmpreg = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 426 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 427 }while(0)
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /** @brief Enables the SPI.
<> 144:ef7eb2e8f9f7 431 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 432 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 433 * @retval None
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /** @brief Disables the SPI.
<> 144:ef7eb2e8f9f7 438 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 439 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 440 * @retval None
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @}
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Private macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 450 /** @defgroup SPI_Private_Macros SPI Private Macros
<> 144:ef7eb2e8f9f7 451 * @{
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /** @brief Checks if SPI Mode parameter is in allowed range.
<> 144:ef7eb2e8f9f7 455 * @param __MODE__: specifies the SPI Mode.
<> 144:ef7eb2e8f9f7 456 * This parameter can be a value of @ref SPI_mode
<> 144:ef7eb2e8f9f7 457 * @retval None
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /** @brief Checks if SPI Direction Mode parameter is in allowed range.
<> 144:ef7eb2e8f9f7 462 * @param __MODE__: specifies the SPI Direction Mode.
<> 144:ef7eb2e8f9f7 463 * This parameter can be a value of @ref SPI_Direction_mode
<> 144:ef7eb2e8f9f7 464 * @retval None
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466 #define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
<> 144:ef7eb2e8f9f7 467 ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
<> 144:ef7eb2e8f9f7 468 ((__MODE__) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
<> 144:ef7eb2e8f9f7 471 * @param __MODE__: specifies the SPI Direction Mode.
<> 144:ef7eb2e8f9f7 472 * @retval None
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
<> 144:ef7eb2e8f9f7 475 ((__MODE__) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /** @brief Checks if SPI Direction Mode parameter is 2 lines.
<> 144:ef7eb2e8f9f7 478 * @param __MODE__: specifies the SPI Direction Mode.
<> 144:ef7eb2e8f9f7 479 * @retval None
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /** @brief Checks if SPI Data Size parameter is in allowed range.
<> 144:ef7eb2e8f9f7 484 * @param __DATASIZE__: specifies the SPI Data Size.
<> 144:ef7eb2e8f9f7 485 * This parameter can be a value of @ref SPI_data_size
<> 144:ef7eb2e8f9f7 486 * @retval None
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
<> 144:ef7eb2e8f9f7 489 ((__DATASIZE__) == SPI_DATASIZE_8BIT))
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
<> 144:ef7eb2e8f9f7 492 * @param __CPOL__: specifies the SPI serial clock steady state.
<> 144:ef7eb2e8f9f7 493 * This parameter can be a value of @ref SPI_Clock_Polarity
<> 144:ef7eb2e8f9f7 494 * @retval None
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 497 ((__CPOL__) == SPI_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /** @brief Checks if SPI Clock Phase parameter is in allowed range.
<> 144:ef7eb2e8f9f7 500 * @param __CPHA__: specifies the SPI Clock Phase.
<> 144:ef7eb2e8f9f7 501 * This parameter can be a value of @ref SPI_Clock_Phase
<> 144:ef7eb2e8f9f7 502 * @retval None
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
<> 144:ef7eb2e8f9f7 505 ((__CPHA__) == SPI_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /** @brief Checks if SPI Slave select parameter is in allowed range.
<> 144:ef7eb2e8f9f7 508 * @param __NSS__: specifies the SPI Slave Slelect management parameter.
<> 144:ef7eb2e8f9f7 509 * This parameter can be a value of @ref SPI_Slave_Select_management
<> 144:ef7eb2e8f9f7 510 * @retval None
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
<> 144:ef7eb2e8f9f7 513 ((__NSS__) == SPI_NSS_HARD_INPUT) || \
<> 144:ef7eb2e8f9f7 514 ((__NSS__) == SPI_NSS_HARD_OUTPUT))
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
<> 144:ef7eb2e8f9f7 517 * @param __PRESCALER__: specifies the SPI Baudrate prescaler.
<> 144:ef7eb2e8f9f7 518 * This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 144:ef7eb2e8f9f7 519 * @retval None
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
<> 144:ef7eb2e8f9f7 522 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
<> 144:ef7eb2e8f9f7 523 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
<> 144:ef7eb2e8f9f7 524 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
<> 144:ef7eb2e8f9f7 525 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
<> 144:ef7eb2e8f9f7 526 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
<> 144:ef7eb2e8f9f7 527 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
<> 144:ef7eb2e8f9f7 528 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
<> 144:ef7eb2e8f9f7 531 * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
<> 144:ef7eb2e8f9f7 532 * This parameter can be a value of @ref SPI_MSB_LSB_transmission
<> 144:ef7eb2e8f9f7 533 * @retval None
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
<> 144:ef7eb2e8f9f7 536 ((__BIT__) == SPI_FIRSTBIT_LSB))
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /** @brief Checks if SPI TI mode parameter is in allowed range.
<> 144:ef7eb2e8f9f7 539 * @param __MODE__: specifies the SPI TI mode.
<> 144:ef7eb2e8f9f7 540 * This parameter can be a value of @ref SPI_TI_mode
<> 144:ef7eb2e8f9f7 541 * @retval None
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543 #define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /** @brief Checks if SPI CRC calculation enabled state is in allowed range.
<> 144:ef7eb2e8f9f7 546 * @param __CALCULATION__: specifies the SPI CRC calculation enable state.
<> 144:ef7eb2e8f9f7 547 * This parameter can be a value of @ref SPI_CRC_Calculation
<> 144:ef7eb2e8f9f7 548 * @retval None
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
<> 144:ef7eb2e8f9f7 551 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
<> 144:ef7eb2e8f9f7 554 * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation.
<> 144:ef7eb2e8f9f7 555 * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
<> 144:ef7eb2e8f9f7 556 * @retval None
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF))
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /** @brief Sets the SPI transmit-only mode.
<> 144:ef7eb2e8f9f7 561 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 562 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 563 * @retval None
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /** @brief Sets the SPI receive-only mode.
<> 144:ef7eb2e8f9f7 568 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 569 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 570 * @retval None
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /** @brief Resets the CRC calculation of the SPI.
<> 144:ef7eb2e8f9f7 575 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 576 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 577 * @retval None
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
<> 144:ef7eb2e8f9f7 580 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @}
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 587 /** @addtogroup SPI_Exported_Functions
<> 144:ef7eb2e8f9f7 588 * @{
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 592 /** @addtogroup SPI_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 593 * @{
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 596 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 597 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 598 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 599 /**
<> 144:ef7eb2e8f9f7 600 * @}
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 604 /** @addtogroup SPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 605 * @{
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 608 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 609 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 610 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 611 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 612 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 613 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 614 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 615 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 616 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 617 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 618 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 621 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 622 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 623 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 624 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 625 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 626 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 627 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @}
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Peripheral State and Control functions **************************************/
<> 144:ef7eb2e8f9f7 634 /** @addtogroup SPI_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 635 * @{
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 638 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /**
<> 144:ef7eb2e8f9f7 641 * @}
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /**
<> 144:ef7eb2e8f9f7 645 * @}
<> 144:ef7eb2e8f9f7 646 */
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Private functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 650 /** @addtogroup SPI_Private_Functions
<> 144:ef7eb2e8f9f7 651 * @{
<> 144:ef7eb2e8f9f7 652 */
<> 144:ef7eb2e8f9f7 653 uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @}
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @}
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @}
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670 #endif
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 #endif /* __STM32F1xx_HAL_SPI_H */
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/