mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_sd.h@144:ef7eb2e8f9f7
Child:
154:37f96f9d4de2
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_sd.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SD HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_SD_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_SD_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 45 extern "C" {
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 49 #include "stm32f1xx_ll_sdmmc.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup SD
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @defgroup SD_Exported_Types SD Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 #define SD_InitTypeDef SDIO_InitTypeDef
<> 144:ef7eb2e8f9f7 65 #define SD_TypeDef SDIO_TypeDef
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @brief SDIO Handle Structure definition
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 typedef struct
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 SD_TypeDef *Instance; /*!< SDIO register base address */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 SD_InitTypeDef Init; /*!< SD required parameters */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 HAL_LockTypeDef Lock; /*!< SD locking object */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t CardType; /*!< SD card type */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t RCA; /*!< SD relative card address */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t CSD[4]; /*!< SD card specific data table */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t CID[4]; /*!< SD card identification number table */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 }SD_HandleTypeDef;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /**
<> 144:ef7eb2e8f9f7 101 * @brief Card Specific Data: CSD Register
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 typedef struct
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 __IO uint8_t CSDStruct; /*!< CSD structure */
<> 144:ef7eb2e8f9f7 106 __IO uint8_t SysSpecVersion; /*!< System specification version */
<> 144:ef7eb2e8f9f7 107 __IO uint8_t Reserved1; /*!< Reserved */
<> 144:ef7eb2e8f9f7 108 __IO uint8_t TAAC; /*!< Data read access time 1 */
<> 144:ef7eb2e8f9f7 109 __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
<> 144:ef7eb2e8f9f7 110 __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
<> 144:ef7eb2e8f9f7 111 __IO uint16_t CardComdClasses; /*!< Card command classes */
<> 144:ef7eb2e8f9f7 112 __IO uint8_t RdBlockLen; /*!< Max. read data block length */
<> 144:ef7eb2e8f9f7 113 __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
<> 144:ef7eb2e8f9f7 114 __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
<> 144:ef7eb2e8f9f7 115 __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
<> 144:ef7eb2e8f9f7 116 __IO uint8_t DSRImpl; /*!< DSR implemented */
<> 144:ef7eb2e8f9f7 117 __IO uint8_t Reserved2; /*!< Reserved */
<> 144:ef7eb2e8f9f7 118 __IO uint32_t DeviceSize; /*!< Device Size */
<> 144:ef7eb2e8f9f7 119 __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
<> 144:ef7eb2e8f9f7 120 __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
<> 144:ef7eb2e8f9f7 121 __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
<> 144:ef7eb2e8f9f7 122 __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
<> 144:ef7eb2e8f9f7 123 __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
<> 144:ef7eb2e8f9f7 124 __IO uint8_t EraseGrSize; /*!< Erase group size */
<> 144:ef7eb2e8f9f7 125 __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
<> 144:ef7eb2e8f9f7 126 __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
<> 144:ef7eb2e8f9f7 127 __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
<> 144:ef7eb2e8f9f7 128 __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
<> 144:ef7eb2e8f9f7 129 __IO uint8_t WrSpeedFact; /*!< Write speed factor */
<> 144:ef7eb2e8f9f7 130 __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
<> 144:ef7eb2e8f9f7 131 __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
<> 144:ef7eb2e8f9f7 132 __IO uint8_t Reserved3; /*!< Reserved */
<> 144:ef7eb2e8f9f7 133 __IO uint8_t ContentProtectAppli; /*!< Content protection application */
<> 144:ef7eb2e8f9f7 134 __IO uint8_t FileFormatGrouop; /*!< File format group */
<> 144:ef7eb2e8f9f7 135 __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
<> 144:ef7eb2e8f9f7 136 __IO uint8_t PermWrProtect; /*!< Permanent write protection */
<> 144:ef7eb2e8f9f7 137 __IO uint8_t TempWrProtect; /*!< Temporary write protection */
<> 144:ef7eb2e8f9f7 138 __IO uint8_t FileFormat; /*!< File format */
<> 144:ef7eb2e8f9f7 139 __IO uint8_t ECC; /*!< ECC code */
<> 144:ef7eb2e8f9f7 140 __IO uint8_t CSD_CRC; /*!< CSD CRC */
<> 144:ef7eb2e8f9f7 141 __IO uint8_t Reserved4; /*!< Always 1 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 }HAL_SD_CSDTypedef;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * @brief Card Identification Data: CID Register
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 typedef struct
<> 144:ef7eb2e8f9f7 149 {
<> 144:ef7eb2e8f9f7 150 __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
<> 144:ef7eb2e8f9f7 151 __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
<> 144:ef7eb2e8f9f7 152 __IO uint32_t ProdName1; /*!< Product Name part1 */
<> 144:ef7eb2e8f9f7 153 __IO uint8_t ProdName2; /*!< Product Name part2 */
<> 144:ef7eb2e8f9f7 154 __IO uint8_t ProdRev; /*!< Product Revision */
<> 144:ef7eb2e8f9f7 155 __IO uint32_t ProdSN; /*!< Product Serial Number */
<> 144:ef7eb2e8f9f7 156 __IO uint8_t Reserved1; /*!< Reserved1 */
<> 144:ef7eb2e8f9f7 157 __IO uint16_t ManufactDate; /*!< Manufacturing Date */
<> 144:ef7eb2e8f9f7 158 __IO uint8_t CID_CRC; /*!< CID CRC */
<> 144:ef7eb2e8f9f7 159 __IO uint8_t Reserved2; /*!< Always 1 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 }HAL_SD_CIDTypedef;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief SD Card Status returned by ACMD13
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 typedef struct
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
<> 144:ef7eb2e8f9f7 169 __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
<> 144:ef7eb2e8f9f7 170 __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
<> 144:ef7eb2e8f9f7 171 __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
<> 144:ef7eb2e8f9f7 172 __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
<> 144:ef7eb2e8f9f7 173 __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
<> 144:ef7eb2e8f9f7 174 __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
<> 144:ef7eb2e8f9f7 175 __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
<> 144:ef7eb2e8f9f7 176 __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
<> 144:ef7eb2e8f9f7 177 __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 }HAL_SD_CardStatusTypedef;
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @brief SD Card information structure
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184 typedef struct
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
<> 144:ef7eb2e8f9f7 187 HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
<> 144:ef7eb2e8f9f7 188 uint64_t CardCapacity; /*!< Card capacity */
<> 144:ef7eb2e8f9f7 189 uint32_t CardBlockSize; /*!< Card block size */
<> 144:ef7eb2e8f9f7 190 uint16_t RCA; /*!< SD relative card address */
<> 144:ef7eb2e8f9f7 191 uint8_t CardType; /*!< SD card type */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 }HAL_SD_CardInfoTypedef;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @brief SD Error status enumeration Structure definition
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 typedef enum
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @brief SD specific error defines
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
<> 144:ef7eb2e8f9f7 204 SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */
<> 144:ef7eb2e8f9f7 205 SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
<> 144:ef7eb2e8f9f7 206 SD_DATA_TIMEOUT = (4), /*!< Data timeout */
<> 144:ef7eb2e8f9f7 207 SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
<> 144:ef7eb2e8f9f7 208 SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
<> 144:ef7eb2e8f9f7 209 SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
<> 144:ef7eb2e8f9f7 210 SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
<> 144:ef7eb2e8f9f7 211 SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
<> 144:ef7eb2e8f9f7 212 SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
<> 144:ef7eb2e8f9f7 213 SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */
<> 144:ef7eb2e8f9f7 214 SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */
<> 144:ef7eb2e8f9f7 215 SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
<> 144:ef7eb2e8f9f7 216 SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
<> 144:ef7eb2e8f9f7 217 SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
<> 144:ef7eb2e8f9f7 218 SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
<> 144:ef7eb2e8f9f7 219 SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
<> 144:ef7eb2e8f9f7 220 SD_CC_ERROR = (18), /*!< Internal card controller error */
<> 144:ef7eb2e8f9f7 221 SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */
<> 144:ef7eb2e8f9f7 222 SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
<> 144:ef7eb2e8f9f7 223 SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
<> 144:ef7eb2e8f9f7 224 SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
<> 144:ef7eb2e8f9f7 225 SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */
<> 144:ef7eb2e8f9f7 226 SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
<> 144:ef7eb2e8f9f7 227 SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
<> 144:ef7eb2e8f9f7 228 SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
<> 144:ef7eb2e8f9f7 229 SD_INVALID_VOLTRANGE = (27),
<> 144:ef7eb2e8f9f7 230 SD_ADDR_OUT_OF_RANGE = (28),
<> 144:ef7eb2e8f9f7 231 SD_SWITCH_ERROR = (29),
<> 144:ef7eb2e8f9f7 232 SD_SDIO_DISABLED = (30),
<> 144:ef7eb2e8f9f7 233 SD_SDIO_FUNCTION_BUSY = (31),
<> 144:ef7eb2e8f9f7 234 SD_SDIO_FUNCTION_FAILED = (32),
<> 144:ef7eb2e8f9f7 235 SD_SDIO_UNKNOWN_FUNCTION = (33),
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief Standard error defines
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 SD_INTERNAL_ERROR = (34),
<> 144:ef7eb2e8f9f7 241 SD_NOT_CONFIGURED = (35),
<> 144:ef7eb2e8f9f7 242 SD_REQUEST_PENDING = (36),
<> 144:ef7eb2e8f9f7 243 SD_REQUEST_NOT_APPLICABLE = (37),
<> 144:ef7eb2e8f9f7 244 SD_INVALID_PARAMETER = (38),
<> 144:ef7eb2e8f9f7 245 SD_UNSUPPORTED_FEATURE = (39),
<> 144:ef7eb2e8f9f7 246 SD_UNSUPPORTED_HW = (40),
<> 144:ef7eb2e8f9f7 247 SD_ERROR = (41),
<> 144:ef7eb2e8f9f7 248 SD_OK = (0)
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 }HAL_SD_ErrorTypedef;
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @brief SD Transfer state enumeration structure
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 typedef enum
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 SD_TRANSFER_OK = 0, /*!< Transfer success */
<> 144:ef7eb2e8f9f7 258 SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */
<> 144:ef7eb2e8f9f7 259 SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 }HAL_SD_TransferStateTypedef;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief SD Card State enumeration structure
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 typedef enum
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
<> 144:ef7eb2e8f9f7 269 SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */
<> 144:ef7eb2e8f9f7 270 SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */
<> 144:ef7eb2e8f9f7 271 SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */
<> 144:ef7eb2e8f9f7 272 SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */
<> 144:ef7eb2e8f9f7 273 SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */
<> 144:ef7eb2e8f9f7 274 SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */
<> 144:ef7eb2e8f9f7 275 SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */
<> 144:ef7eb2e8f9f7 276 SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 }HAL_SD_CardStateTypedef;
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @brief SD Operation enumeration structure
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 typedef enum
<> 144:ef7eb2e8f9f7 284 {
<> 144:ef7eb2e8f9f7 285 SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
<> 144:ef7eb2e8f9f7 286 SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */
<> 144:ef7eb2e8f9f7 287 SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */
<> 144:ef7eb2e8f9f7 288 SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 }HAL_SD_OperationTypedef;
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @}
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 297 /** @defgroup SD_Exported_Constants SD Exported Constants
<> 144:ef7eb2e8f9f7 298 * @{
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @brief SD Commands Index
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 #define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
<> 144:ef7eb2e8f9f7 305 #define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
<> 144:ef7eb2e8f9f7 306 #define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
<> 144:ef7eb2e8f9f7 307 #define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
<> 144:ef7eb2e8f9f7 308 #define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
<> 144:ef7eb2e8f9f7 309 #define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
<> 144:ef7eb2e8f9f7 310 operating condition register (OCR) content in the response on the CMD line. */
<> 144:ef7eb2e8f9f7 311 #define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
<> 144:ef7eb2e8f9f7 312 #define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
<> 144:ef7eb2e8f9f7 313 #define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
<> 144:ef7eb2e8f9f7 314 and asks the card whether card supports voltage. */
<> 144:ef7eb2e8f9f7 315 #define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
<> 144:ef7eb2e8f9f7 316 #define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
<> 144:ef7eb2e8f9f7 317 #define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
<> 144:ef7eb2e8f9f7 318 #define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
<> 144:ef7eb2e8f9f7 319 #define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
<> 144:ef7eb2e8f9f7 320 #define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
<> 144:ef7eb2e8f9f7 321 #define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
<> 144:ef7eb2e8f9f7 322 #define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
<> 144:ef7eb2e8f9f7 323 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
<> 144:ef7eb2e8f9f7 324 for SDHS and SDXC. */
<> 144:ef7eb2e8f9f7 325 #define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
<> 144:ef7eb2e8f9f7 326 fixed 512 bytes in case of SDHC and SDXC. */
<> 144:ef7eb2e8f9f7 327 #define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
<> 144:ef7eb2e8f9f7 328 STOP_TRANSMISSION command. */
<> 144:ef7eb2e8f9f7 329 #define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
<> 144:ef7eb2e8f9f7 330 #define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
<> 144:ef7eb2e8f9f7 331 #define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
<> 144:ef7eb2e8f9f7 332 #define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
<> 144:ef7eb2e8f9f7 333 fixed 512 bytes in case of SDHC and SDXC. */
<> 144:ef7eb2e8f9f7 334 #define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
<> 144:ef7eb2e8f9f7 335 #define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
<> 144:ef7eb2e8f9f7 336 #define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
<> 144:ef7eb2e8f9f7 337 #define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
<> 144:ef7eb2e8f9f7 338 #define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
<> 144:ef7eb2e8f9f7 339 #define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
<> 144:ef7eb2e8f9f7 340 #define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
<> 144:ef7eb2e8f9f7 341 #define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
<> 144:ef7eb2e8f9f7 342 #define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
<> 144:ef7eb2e8f9f7 343 system set by switch function command (CMD6). */
<> 144:ef7eb2e8f9f7 344 #define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
<> 144:ef7eb2e8f9f7 345 Reserved for each command system set by switch function command (CMD6). */
<> 144:ef7eb2e8f9f7 346 #define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
<> 144:ef7eb2e8f9f7 347 #define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
<> 144:ef7eb2e8f9f7 348 #define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
<> 144:ef7eb2e8f9f7 349 #define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
<> 144:ef7eb2e8f9f7 350 the SET_BLOCK_LEN command. */
<> 144:ef7eb2e8f9f7 351 #define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
<> 144:ef7eb2e8f9f7 352 than a standard command. */
<> 144:ef7eb2e8f9f7 353 #define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
<> 144:ef7eb2e8f9f7 354 for general purpose/application specific commands. */
<> 144:ef7eb2e8f9f7 355 #define SD_CMD_NO_CMD ((uint8_t)64)
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief Following commands are SD Card Specific commands.
<> 144:ef7eb2e8f9f7 359 * SDIO_APP_CMD should be sent before sending these commands.
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 #define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
<> 144:ef7eb2e8f9f7 362 widths are given in SCR register. */
<> 144:ef7eb2e8f9f7 363 #define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
<> 144:ef7eb2e8f9f7 364 #define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
<> 144:ef7eb2e8f9f7 365 32bit+CRC data block. */
<> 144:ef7eb2e8f9f7 366 #define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
<> 144:ef7eb2e8f9f7 367 send its operating condition register (OCR) content in the response on the CMD line. */
<> 144:ef7eb2e8f9f7 368 #define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
<> 144:ef7eb2e8f9f7 369 #define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
<> 144:ef7eb2e8f9f7 370 #define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
<> 144:ef7eb2e8f9f7 371 #define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief Following commands are SD Card Specific security commands.
<> 144:ef7eb2e8f9f7 375 * SD_CMD_APP_CMD should be sent before sending these commands.
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 #define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 378 #define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 379 #define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 380 #define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 381 #define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 382 #define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 383 #define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 384 #define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 385 #define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 386 #define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 387 #define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @brief Supported SD Memory Cards
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 #define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 393 #define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 394 #define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 395 #define MULTIMEDIA_CARD ((uint32_t)0x00000003)
<> 144:ef7eb2e8f9f7 396 #define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 397 #define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
<> 144:ef7eb2e8f9f7 398 #define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
<> 144:ef7eb2e8f9f7 399 #define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 405 /** @defgroup SD_Exported_macros SD Exported Macros
<> 144:ef7eb2e8f9f7 406 * @brief macros to handle interrupts and specific clock configurations
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @brief Enable the SD device.
<> 144:ef7eb2e8f9f7 412 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 413 * @retval None
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define __HAL_SD_SDIO_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @brief Disable the SD device.
<> 144:ef7eb2e8f9f7 419 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 420 * @retval None
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422 #define __HAL_SD_SDIO_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @brief Enable the SDIO DMA transfer.
<> 144:ef7eb2e8f9f7 426 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 427 * @retval None
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 #define __HAL_SD_SDIO_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @brief Disable the SDIO DMA transfer.
<> 144:ef7eb2e8f9f7 433 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 434 * @retval None
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 #define __HAL_SD_SDIO_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Enable the SD device interrupt.
<> 144:ef7eb2e8f9f7 440 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 441 * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 442 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 443 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 444 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 445 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 446 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 447 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 448 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 449 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 450 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 451 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 452 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 453 * bus mode interrupt
<> 144:ef7eb2e8f9f7 454 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 455 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 456 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 457 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 458 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 459 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 460 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 461 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 462 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 463 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 464 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 465 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 466 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 467 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 144:ef7eb2e8f9f7 468 * @retval None
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470 #define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @brief Disable the SD device interrupt.
<> 144:ef7eb2e8f9f7 474 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 475 * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 476 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 477 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 478 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 479 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 480 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 481 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 482 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 483 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 484 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 485 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 486 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 487 * bus mode interrupt
<> 144:ef7eb2e8f9f7 488 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 489 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 490 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 491 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 492 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 493 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 494 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 495 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 496 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 497 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 498 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 499 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 500 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 501 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 144:ef7eb2e8f9f7 502 * @retval None
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 #define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /**
<> 144:ef7eb2e8f9f7 507 * @brief Check whether the specified SD flag is set or not.
<> 144:ef7eb2e8f9f7 508 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 509 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 510 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 511 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 512 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 513 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 514 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 515 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 516 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 517 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 518 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 519 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 520 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
<> 144:ef7eb2e8f9f7 521 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 522 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
<> 144:ef7eb2e8f9f7 523 * @arg SDIO_FLAG_TXACT: Data transmit in progress
<> 144:ef7eb2e8f9f7 524 * @arg SDIO_FLAG_RXACT: Data receive in progress
<> 144:ef7eb2e8f9f7 525 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<> 144:ef7eb2e8f9f7 526 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
<> 144:ef7eb2e8f9f7 527 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
<> 144:ef7eb2e8f9f7 528 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
<> 144:ef7eb2e8f9f7 529 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
<> 144:ef7eb2e8f9f7 530 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
<> 144:ef7eb2e8f9f7 531 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
<> 144:ef7eb2e8f9f7 532 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
<> 144:ef7eb2e8f9f7 533 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 534 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<> 144:ef7eb2e8f9f7 535 * @retval The new state of SD FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 #define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @brief Clear the SD's pending flags.
<> 144:ef7eb2e8f9f7 541 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 542 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 543 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 544 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 545 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 546 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 547 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 548 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 549 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 550 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 551 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 552 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 553 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
<> 144:ef7eb2e8f9f7 554 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 555 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 556 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<> 144:ef7eb2e8f9f7 557 * @retval None
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 #define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @brief Check whether the specified SD interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 563 * @param __HANDLE__: SD Handle
<> 144:ef7eb2e8f9f7 564 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
<> 144:ef7eb2e8f9f7 565 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 566 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 567 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 568 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 569 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 570 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 571 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 572 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 573 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 574 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 575 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 576 * bus mode interrupt
<> 144:ef7eb2e8f9f7 577 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 578 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 579 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 580 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 581 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 582 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 583 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 584 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 585 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 586 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 587 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 588 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 589 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 590 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 144:ef7eb2e8f9f7 591 * @retval The new state of SD IT (SET or RESET).
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593 #define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @brief Clear the SD's interrupt pending bits.
<> 144:ef7eb2e8f9f7 597 * @param __HANDLE__ : SD Handle
<> 144:ef7eb2e8f9f7 598 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 599 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 600 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 601 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 602 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 603 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 604 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 605 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 606 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 607 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 608 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 609 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 610 * bus mode interrupt
<> 144:ef7eb2e8f9f7 611 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 612 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
<> 144:ef7eb2e8f9f7 613 * @retval None
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 #define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @}
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 621 /** @addtogroup SD_Exported_Functions
<> 144:ef7eb2e8f9f7 622 * @{
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Initialization and de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 626 /** @addtogroup SD_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 627 * @{
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629 HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
<> 144:ef7eb2e8f9f7 630 HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 631 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 632 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 633 /**
<> 144:ef7eb2e8f9f7 634 * @}
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 638 /** @addtogroup SD_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 639 * @{
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 642 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
<> 144:ef7eb2e8f9f7 643 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
<> 144:ef7eb2e8f9f7 644 HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 647 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Callback in non blocking modes (DMA) */
<> 144:ef7eb2e8f9f7 650 void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 651 void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 652 void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 653 void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 654 void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 655 void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 658 HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
<> 144:ef7eb2e8f9f7 659 HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
<> 144:ef7eb2e8f9f7 660 HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 661 HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 662 /**
<> 144:ef7eb2e8f9f7 663 * @}
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 667 /** @addtogroup SD_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 668 * @{
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
<> 144:ef7eb2e8f9f7 671 HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
<> 144:ef7eb2e8f9f7 672 HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 673 HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 674 /**
<> 144:ef7eb2e8f9f7 675 * @}
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Peripheral State functions **************************************************/
<> 144:ef7eb2e8f9f7 679 /** @addtogroup SD_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 680 * @{
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682 HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
<> 144:ef7eb2e8f9f7 683 HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
<> 144:ef7eb2e8f9f7 684 HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
<> 144:ef7eb2e8f9f7 685 /**
<> 144:ef7eb2e8f9f7 686 * @}
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /**
<> 144:ef7eb2e8f9f7 690 * @}
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /**
<> 144:ef7eb2e8f9f7 694 * @}
<> 144:ef7eb2e8f9f7 695 */
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /**
<> 144:ef7eb2e8f9f7 698 * @}
<> 144:ef7eb2e8f9f7 699 */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 #endif
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 #endif /* __STM32F1xx_HAL_SD_H */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/