mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_i2s.c@144:ef7eb2e8f9f7
Child:
154:37f96f9d4de2
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_i2s.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.0.4
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief I2S HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ===============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The I2S HAL driver can be used as follow:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a I2S_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
<> 144:ef7eb2e8f9f7 22 (##) Enable the SPIx interface clock.
<> 144:ef7eb2e8f9f7 23 (##) I2S pins configuration:
<> 144:ef7eb2e8f9f7 24 (+++) Enable the clock for the I2S GPIOs.
<> 144:ef7eb2e8f9f7 25 (+++) Configure these I2S pins as alternate function.
<> 144:ef7eb2e8f9f7 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 27 and HAL_I2S_Receive_IT() APIs).
<> 144:ef7eb2e8f9f7 28 (+++) Configure the I2Sx interrupt priority.
<> 144:ef7eb2e8f9f7 29 (+++) Enable the NVIC I2S IRQ handle.
<> 144:ef7eb2e8f9f7 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 31 and HAL_I2S_Receive_DMA() APIs:
<> 144:ef7eb2e8f9f7 32 (+++) Declare a DMA handle structure for the Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 33 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 36 (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
<> 144:ef7eb2e8f9f7 38 DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
<> 144:ef7eb2e8f9f7 41 using HAL_I2S_Init() function.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 -@- The specific I2S interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 44 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 45 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 46 -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
<> 144:ef7eb2e8f9f7 47 For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
<> 144:ef7eb2e8f9f7 48 in order to achieve the maximum accuracy.
<> 144:ef7eb2e8f9f7 49 -@- Make sure that either:
<> 144:ef7eb2e8f9f7 50 (+@) External clock source is configured after setting correctly
<> 144:ef7eb2e8f9f7 51 the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) Three mode of operations are available within this driver :
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 56 =================================
<> 144:ef7eb2e8f9f7 57 [..]
<> 144:ef7eb2e8f9f7 58 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 59 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 62 ===================================
<> 144:ef7eb2e8f9f7 63 [..]
<> 144:ef7eb2e8f9f7 64 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 65 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 68 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 69 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 70 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 72 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 73 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 74 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 75 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 78 ==============================
<> 144:ef7eb2e8f9f7 79 [..]
<> 144:ef7eb2e8f9f7 80 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 81 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 84 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 85 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 86 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 88 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 90 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 91 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 92 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
<> 144:ef7eb2e8f9f7 93 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
<> 144:ef7eb2e8f9f7 94 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 *** I2S HAL driver macros list ***
<> 144:ef7eb2e8f9f7 97 =============================================
<> 144:ef7eb2e8f9f7 98 [..]
<> 144:ef7eb2e8f9f7 99 Below the list of most used macros in USART HAL driver.
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 102 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 103 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 104 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 105 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 [..]
<> 144:ef7eb2e8f9f7 108 (@) You can refer to the I2S HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 *** I2C Workarounds linked to Silicon Limitation ***
<> 144:ef7eb2e8f9f7 112 ====================================================
<> 144:ef7eb2e8f9f7 113 [..]
<> 144:ef7eb2e8f9f7 114 (@) Only the 16-bit mode with no data extension can be used when the I2S
<> 144:ef7eb2e8f9f7 115 is in Master and used the PCM long synchronization mode.
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 @endverbatim
<> 144:ef7eb2e8f9f7 119 ******************************************************************************
<> 144:ef7eb2e8f9f7 120 * @attention
<> 144:ef7eb2e8f9f7 121 *
<> 144:ef7eb2e8f9f7 122 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 125 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 126 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 127 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 128 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 129 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 130 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 131 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 132 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 133 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 134 *
<> 144:ef7eb2e8f9f7 135 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 136 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 137 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 138 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 139 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 140 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 141 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 142 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 143 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 145 *
<> 144:ef7eb2e8f9f7 146 ******************************************************************************
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 150 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 #ifdef HAL_I2S_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 157 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /** @defgroup I2S I2S
<> 144:ef7eb2e8f9f7 160 * @brief I2S HAL module driver
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 166 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 167 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 168 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 169 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 173 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 174 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 175 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 176 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 177 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 178 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 179 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @}
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 185 /** @defgroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 190 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 191 *
<> 144:ef7eb2e8f9f7 192 @verbatim
<> 144:ef7eb2e8f9f7 193 ===============================================================================
<> 144:ef7eb2e8f9f7 194 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 195 ===============================================================================
<> 144:ef7eb2e8f9f7 196 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 197 de-initialiaze the I2Sx peripheral in simplex mode:
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 (+) User must Implement HAL_I2S_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 200 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 (+) Call the function HAL_I2S_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 203 the selected configuration:
<> 144:ef7eb2e8f9f7 204 (++) Mode
<> 144:ef7eb2e8f9f7 205 (++) Standard
<> 144:ef7eb2e8f9f7 206 (++) Data Format
<> 144:ef7eb2e8f9f7 207 (++) MCLK Output
<> 144:ef7eb2e8f9f7 208 (++) Audio frequency
<> 144:ef7eb2e8f9f7 209 (++) Polarity
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 212 of the selected I2Sx periperal.
<> 144:ef7eb2e8f9f7 213 @endverbatim
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief Initializes the I2S according to the specified parameters
<> 144:ef7eb2e8f9f7 219 * in the I2S_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 220 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 221 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 222 * @retval HAL status
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
<> 144:ef7eb2e8f9f7 227 uint32_t tmp = 0, i2sclk = 0;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 230 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Check the I2S parameters */
<> 144:ef7eb2e8f9f7 236 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 237 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
<> 144:ef7eb2e8f9f7 238 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
<> 144:ef7eb2e8f9f7 239 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
<> 144:ef7eb2e8f9f7 240 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 241 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
<> 144:ef7eb2e8f9f7 242 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 if(hi2s->State == HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 247 hi2s->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 250 HAL_I2S_MspInit(hi2s);
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
<> 144:ef7eb2e8f9f7 256 if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 i2sodd = (uint32_t)0;
<> 144:ef7eb2e8f9f7 259 i2sdiv = (uint32_t)2;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 /* If the requested audio frequency is not the default, compute the prescaler */
<> 144:ef7eb2e8f9f7 262 else
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /* Check the frame length (For the Prescaler computing) *******************/
<> 144:ef7eb2e8f9f7 265 if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Packet length is 16 bits */
<> 144:ef7eb2e8f9f7 268 packetlength = 1;
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270 else
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 /* Packet length is 32 bits */
<> 144:ef7eb2e8f9f7 273 packetlength = 2;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 if(hi2s->Instance == SPI2)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Get the source clock value: based on SPI2 Instance */
<> 144:ef7eb2e8f9f7 279 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281 else if(hi2s->Instance == SPI3)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 /* Get the source clock value: based on SPI3 Instance */
<> 144:ef7eb2e8f9f7 284 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3);
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286 else
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Get the source clock value: based on System Clock value */
<> 144:ef7eb2e8f9f7 289 i2sclk = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 if(i2sclk == 0)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Compute the Real divider depending on the MCLK output state, with a floating point */
<> 144:ef7eb2e8f9f7 297 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 /* MCLK output is enabled */
<> 144:ef7eb2e8f9f7 300 tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302 else
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 /* MCLK output is disabled */
<> 144:ef7eb2e8f9f7 305 tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Remove the flatting point */
<> 144:ef7eb2e8f9f7 309 tmp = tmp / 10;
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Check the parity of the divider */
<> 144:ef7eb2e8f9f7 312 i2sodd = (uint32_t)(tmp & (uint32_t)1);
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Compute the i2sdiv prescaler */
<> 144:ef7eb2e8f9f7 315 i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 144:ef7eb2e8f9f7 318 i2sodd = (uint32_t) (i2sodd << 8);
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 144:ef7eb2e8f9f7 322 if((i2sdiv < 2) || (i2sdiv > 0xFF))
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Set the default values */
<> 144:ef7eb2e8f9f7 325 i2sdiv = 2;
<> 144:ef7eb2e8f9f7 326 i2sodd = 0;
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
<> 144:ef7eb2e8f9f7 330 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
<> 144:ef7eb2e8f9f7 331 /* And configure the I2S with the I2S_InitStruct values */
<> 144:ef7eb2e8f9f7 332 MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
<> 144:ef7eb2e8f9f7 333 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
<> 144:ef7eb2e8f9f7 334 SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
<> 144:ef7eb2e8f9f7 335 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\
<> 144:ef7eb2e8f9f7 336 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
<> 144:ef7eb2e8f9f7 337 hi2s->Init.Standard | hi2s->Init.DataFormat |\
<> 144:ef7eb2e8f9f7 338 hi2s->Init.CPOL));
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Write to SPIx I2SPR register the computed value */
<> 144:ef7eb2e8f9f7 341 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 344 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 return HAL_OK;
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @brief DeInitializes the I2S peripheral
<> 144:ef7eb2e8f9f7 351 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 352 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 353 * @retval HAL status
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 356 {
<> 144:ef7eb2e8f9f7 357 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 358 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 359 {
<> 144:ef7eb2e8f9f7 360 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Disable the I2S Peripheral Clock */
<> 144:ef7eb2e8f9f7 366 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 369 HAL_I2S_MspDeInit(hi2s);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 372 hi2s->State = HAL_I2S_STATE_RESET;
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Release Lock */
<> 144:ef7eb2e8f9f7 375 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 return HAL_OK;
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @brief I2S MSP Init
<> 144:ef7eb2e8f9f7 382 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 383 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 384 * @retval None
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 389 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 390 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 391 the HAL_I2S_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @brief I2S MSP DeInit
<> 144:ef7eb2e8f9f7 397 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 398 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 399 * @retval None
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 404 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 405 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 406 the HAL_I2S_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 415 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 416 *
<> 144:ef7eb2e8f9f7 417 @verbatim
<> 144:ef7eb2e8f9f7 418 ===============================================================================
<> 144:ef7eb2e8f9f7 419 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 420 ===============================================================================
<> 144:ef7eb2e8f9f7 421 [..]
<> 144:ef7eb2e8f9f7 422 This subsection provides a set of functions allowing to manage the I2S data
<> 144:ef7eb2e8f9f7 423 transfers.
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 426 (++) Blocking mode : The communication is performed in the polling mode.
<> 144:ef7eb2e8f9f7 427 The status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 428 after finishing transfer.
<> 144:ef7eb2e8f9f7 429 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 430 or DMA. These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 431 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 432 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 433 using DMA mode.
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 436 (++) HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 437 (++) HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 440 (++) HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 441 (++) HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 444 (++) HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 445 (++) HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 448 (++) HAL_I2S_TxCpltCallback()
<> 144:ef7eb2e8f9f7 449 (++) HAL_I2S_RxCpltCallback()
<> 144:ef7eb2e8f9f7 450 (++) HAL_I2S_ErrorCallback()
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 @endverbatim
<> 144:ef7eb2e8f9f7 453 * @{
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 458 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 459 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 460 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 461 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 462 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 463 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 464 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 465 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 466 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 467 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 468 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 469 * @retval HAL status
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 476 }
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /* Process Locked */
<> 144:ef7eb2e8f9f7 479 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 484 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 487 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489 else
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 492 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Set state and reset error code */
<> 144:ef7eb2e8f9f7 496 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 497 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 498 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 501 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 504 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 while(hi2s->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 /* Wait until TXE flag is set */
<> 144:ef7eb2e8f9f7 510 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 515 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Check if an underrun occurs */
<> 144:ef7eb2e8f9f7 518 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 521 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 524 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 527 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
<> 144:ef7eb2e8f9f7 528 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 }
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Wait until TXE flag is set, to confirm the end of the transcation */
<> 144:ef7eb2e8f9f7 533 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 534 {
<> 144:ef7eb2e8f9f7 535 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537 /* Check if Slave mode is selected */
<> 144:ef7eb2e8f9f7 538 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 /* Wait until Busy flag is reset */
<> 144:ef7eb2e8f9f7 541 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 549 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 return HAL_OK;
<> 144:ef7eb2e8f9f7 552 }
<> 144:ef7eb2e8f9f7 553 else
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 556 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 557 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 563 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 564 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 565 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 566 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 567 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 568 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 569 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 570 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 571 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 572 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 573 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 574 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
<> 144:ef7eb2e8f9f7 575 * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
<> 144:ef7eb2e8f9f7 576 * @retval HAL status
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Process Locked */
<> 144:ef7eb2e8f9f7 586 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 589 {
<> 144:ef7eb2e8f9f7 590 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 591 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 594 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 else
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 599 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Set state and reset error code */
<> 144:ef7eb2e8f9f7 603 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 604 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 605 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 608 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 611 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /* Receive data */
<> 144:ef7eb2e8f9f7 615 while(hi2s->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 616 {
<> 144:ef7eb2e8f9f7 617 /* Wait until RXNE flag is reset */
<> 144:ef7eb2e8f9f7 618 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 624 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Check if an overrun occurs */
<> 144:ef7eb2e8f9f7 627 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 630 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 633 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 636 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
<> 144:ef7eb2e8f9f7 637 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 644 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 return HAL_OK;
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 else
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 651 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 652 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /**
<> 144:ef7eb2e8f9f7 657 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 658 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 659 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 660 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 661 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 662 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 663 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 664 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 665 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 666 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 667 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 668 * @retval HAL status
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Process Locked */
<> 144:ef7eb2e8f9f7 678 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 681 {
<> 144:ef7eb2e8f9f7 682 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 683 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 684 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 687 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 690 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 else
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 695 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 699 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 702 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 705 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 709 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 return HAL_OK;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 else
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 716 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 717 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 723 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 724 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 725 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 726 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 727 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 728 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 729 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 730 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 731 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 732 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 733 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
<> 144:ef7eb2e8f9f7 734 * between Master and Slave otherwise the I2S interrupt should be optimized.
<> 144:ef7eb2e8f9f7 735 * @retval HAL status
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /* Process Locked */
<> 144:ef7eb2e8f9f7 745 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 748 {
<> 144:ef7eb2e8f9f7 749 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 750 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 751 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 754 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 757 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 else
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 762 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Enable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 766 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 769 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 772 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 776 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 return HAL_OK;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780 else
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 783 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 784 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /**
<> 144:ef7eb2e8f9f7 789 * @brief Transmit an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 790 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 791 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 792 * @param pData: a 16-bit pointer to the Transmit data buffer.
<> 144:ef7eb2e8f9f7 793 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 794 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 795 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 796 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 797 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 798 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 799 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 800 * @retval HAL status
<> 144:ef7eb2e8f9f7 801 */
<> 144:ef7eb2e8f9f7 802 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Process Locked */
<> 144:ef7eb2e8f9f7 810 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 815 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 816 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 819 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 822 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824 else
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 827 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /* Set the I2S Tx DMA Half transfert complete callback */
<> 144:ef7eb2e8f9f7 831 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 /* Set the I2S Tx DMA transfert complete callback */
<> 144:ef7eb2e8f9f7 834 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 837 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 840 HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 843 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 846 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /* Check if the I2S Tx request is already enabled */
<> 144:ef7eb2e8f9f7 850 if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 853 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 857 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 return HAL_OK;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861 else
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 864 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 865 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 866 }
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @brief Receive an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 871 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 872 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 873 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 874 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 875 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 876 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 877 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 878 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 879 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 880 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 881 * @retval HAL status
<> 144:ef7eb2e8f9f7 882 */
<> 144:ef7eb2e8f9f7 883 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 886 {
<> 144:ef7eb2e8f9f7 887 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Process Locked */
<> 144:ef7eb2e8f9f7 891 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 894 {
<> 144:ef7eb2e8f9f7 895 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 896 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 897 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 900 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 903 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905 else
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 908 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Set the I2S Rx DMA Half transfert complete callback */
<> 144:ef7eb2e8f9f7 913 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Set the I2S Rx DMA transfert complete callback */
<> 144:ef7eb2e8f9f7 916 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 919 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 922 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 923 {
<> 144:ef7eb2e8f9f7 924 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 925 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 926 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 930 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 933 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 936 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /* Check if the I2S Rx request is already enabled */
<> 144:ef7eb2e8f9f7 940 if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 943 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 944 }
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 947 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 return HAL_OK;
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951 else
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 954 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 955 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 956 }
<> 144:ef7eb2e8f9f7 957 }
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /**
<> 144:ef7eb2e8f9f7 960 * @brief Pauses the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 961 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 962 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 963 * @retval HAL status
<> 144:ef7eb2e8f9f7 964 */
<> 144:ef7eb2e8f9f7 965 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 /* Process Locked */
<> 144:ef7eb2e8f9f7 968 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 973 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 974 }
<> 144:ef7eb2e8f9f7 975 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 978 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 979 }
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 982 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 return HAL_OK;
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /**
<> 144:ef7eb2e8f9f7 988 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 989 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 990 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 991 * @retval HAL status
<> 144:ef7eb2e8f9f7 992 */
<> 144:ef7eb2e8f9f7 993 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 /* Process Locked */
<> 144:ef7eb2e8f9f7 996 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 /* Enable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 1001 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1002 }
<> 144:ef7eb2e8f9f7 1003 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1004 {
<> 144:ef7eb2e8f9f7 1005 /* Enable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 1006 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1007 }
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* If the I2S peripheral is still not enabled, enable it */
<> 144:ef7eb2e8f9f7 1010 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 1013 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1017 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 return HAL_OK;
<> 144:ef7eb2e8f9f7 1020 }
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /**
<> 144:ef7eb2e8f9f7 1023 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 1024 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1025 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1026 * @retval HAL status
<> 144:ef7eb2e8f9f7 1027 */
<> 144:ef7eb2e8f9f7 1028 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 /* Process Locked */
<> 144:ef7eb2e8f9f7 1031 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Disable the I2S Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 1034 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1035 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Abort the I2S DMA Channel tx */
<> 144:ef7eb2e8f9f7 1038 if(hi2s->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1039 {
<> 144:ef7eb2e8f9f7 1040 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 1041 __HAL_DMA_DISABLE(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1042 HAL_DMA_Abort(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044 /* Abort the I2S DMA Channel rx */
<> 144:ef7eb2e8f9f7 1045 if(hi2s->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1046 {
<> 144:ef7eb2e8f9f7 1047 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 1048 __HAL_DMA_DISABLE(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1049 HAL_DMA_Abort(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1050 }
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Disable I2S peripheral */
<> 144:ef7eb2e8f9f7 1053 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1058 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 return HAL_OK;
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /**
<> 144:ef7eb2e8f9f7 1064 * @brief This function handles I2S interrupt request.
<> 144:ef7eb2e8f9f7 1065 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1066 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1067 * @retval None
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 uint32_t i2ssr = hi2s->Instance->SR;
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /* I2S in mode Receiver ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1074 if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
<> 144:ef7eb2e8f9f7 1075 ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 1076 {
<> 144:ef7eb2e8f9f7 1077 I2S_Receive_IT(hi2s);
<> 144:ef7eb2e8f9f7 1078 return;
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* I2S in mode Tramitter -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1082 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 I2S_Transmit_IT(hi2s);
<> 144:ef7eb2e8f9f7 1085 return;
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /* I2S interrupt error -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1089 if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
<> 144:ef7eb2e8f9f7 1090 {
<> 144:ef7eb2e8f9f7 1091 /* I2S Overrun error interrupt occured ---------------------------------*/
<> 144:ef7eb2e8f9f7 1092 if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1095 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1098 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
<> 144:ef7eb2e8f9f7 1099 }
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /* I2S Underrun error interrupt occured --------------------------------*/
<> 144:ef7eb2e8f9f7 1102 if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1105 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1108 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1112 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1113 /* Call the Error Callback */
<> 144:ef7eb2e8f9f7 1114 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1115 }
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /**
<> 144:ef7eb2e8f9f7 1119 * @brief Tx Transfer Half completed callbacks
<> 144:ef7eb2e8f9f7 1120 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1121 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1122 * @retval None
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1127 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1128 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1129 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1130 */
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /**
<> 144:ef7eb2e8f9f7 1134 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1135 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1136 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1137 * @retval None
<> 144:ef7eb2e8f9f7 1138 */
<> 144:ef7eb2e8f9f7 1139 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1142 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1143 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1144 the HAL_I2S_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1145 */
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /**
<> 144:ef7eb2e8f9f7 1149 * @brief Rx Transfer half completed callbacks
<> 144:ef7eb2e8f9f7 1150 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1151 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1152 * @retval None
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1157 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1158 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1159 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1160 */
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /**
<> 144:ef7eb2e8f9f7 1164 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1165 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1166 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1167 * @retval None
<> 144:ef7eb2e8f9f7 1168 */
<> 144:ef7eb2e8f9f7 1169 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1170 {
<> 144:ef7eb2e8f9f7 1171 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1172 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1173 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1174 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1175 */
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /**
<> 144:ef7eb2e8f9f7 1179 * @brief I2S error callbacks
<> 144:ef7eb2e8f9f7 1180 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1181 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1182 * @retval None
<> 144:ef7eb2e8f9f7 1183 */
<> 144:ef7eb2e8f9f7 1184 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1185 {
<> 144:ef7eb2e8f9f7 1186 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1187 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1188 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1189 the HAL_I2S_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1190 */
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /**
<> 144:ef7eb2e8f9f7 1194 * @}
<> 144:ef7eb2e8f9f7 1195 */
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1198 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1199 *
<> 144:ef7eb2e8f9f7 1200 @verbatim
<> 144:ef7eb2e8f9f7 1201 ===============================================================================
<> 144:ef7eb2e8f9f7 1202 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1203 ===============================================================================
<> 144:ef7eb2e8f9f7 1204 [..]
<> 144:ef7eb2e8f9f7 1205 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1206 and the data flow.
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 @endverbatim
<> 144:ef7eb2e8f9f7 1209 * @{
<> 144:ef7eb2e8f9f7 1210 */
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /**
<> 144:ef7eb2e8f9f7 1213 * @brief Return the I2S state
<> 144:ef7eb2e8f9f7 1214 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1215 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1216 * @retval HAL state
<> 144:ef7eb2e8f9f7 1217 */
<> 144:ef7eb2e8f9f7 1218 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1219 {
<> 144:ef7eb2e8f9f7 1220 return hi2s->State;
<> 144:ef7eb2e8f9f7 1221 }
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /**
<> 144:ef7eb2e8f9f7 1224 * @brief Return the I2S error code
<> 144:ef7eb2e8f9f7 1225 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1226 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1227 * @retval I2S Error Code
<> 144:ef7eb2e8f9f7 1228 */
<> 144:ef7eb2e8f9f7 1229 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 return hi2s->ErrorCode;
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233 /**
<> 144:ef7eb2e8f9f7 1234 * @}
<> 144:ef7eb2e8f9f7 1235 */
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /**
<> 144:ef7eb2e8f9f7 1238 * @}
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1242 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 1243 * @{
<> 144:ef7eb2e8f9f7 1244 */
<> 144:ef7eb2e8f9f7 1245 /**
<> 144:ef7eb2e8f9f7 1246 * @brief DMA I2S transmit process complete callback
<> 144:ef7eb2e8f9f7 1247 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1248 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1249 * @retval None
<> 144:ef7eb2e8f9f7 1250 */
<> 144:ef7eb2e8f9f7 1251 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1252 {
<> 144:ef7eb2e8f9f7 1253 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1258 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1261 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1264 }
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /**
<> 144:ef7eb2e8f9f7 1267 * @brief DMA I2S transmit process half complete callback
<> 144:ef7eb2e8f9f7 1268 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1269 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1270 * @retval None
<> 144:ef7eb2e8f9f7 1271 */
<> 144:ef7eb2e8f9f7 1272 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1273 {
<> 144:ef7eb2e8f9f7 1274 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 HAL_I2S_TxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /**
<> 144:ef7eb2e8f9f7 1280 * @brief DMA I2S receive process complete callback
<> 144:ef7eb2e8f9f7 1281 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1282 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1283 * @retval None
<> 144:ef7eb2e8f9f7 1284 */
<> 144:ef7eb2e8f9f7 1285 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1286 {
<> 144:ef7eb2e8f9f7 1287 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 1290 {
<> 144:ef7eb2e8f9f7 1291 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1292 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1293 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1294 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1295 }
<> 144:ef7eb2e8f9f7 1296 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1297 }
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /**
<> 144:ef7eb2e8f9f7 1300 * @brief DMA I2S receive process half complete callback
<> 144:ef7eb2e8f9f7 1301 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1302 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1303 * @retval None
<> 144:ef7eb2e8f9f7 1304 */
<> 144:ef7eb2e8f9f7 1305 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1306 {
<> 144:ef7eb2e8f9f7 1307 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 HAL_I2S_RxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1310 }
<> 144:ef7eb2e8f9f7 1311
<> 144:ef7eb2e8f9f7 1312 /**
<> 144:ef7eb2e8f9f7 1313 * @brief DMA I2S communication error callback
<> 144:ef7eb2e8f9f7 1314 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1315 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1316 * @retval None
<> 144:ef7eb2e8f9f7 1317 */
<> 144:ef7eb2e8f9f7 1318 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1319 {
<> 144:ef7eb2e8f9f7 1320 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /* Disable Rx and Tx DMA Request */
<> 144:ef7eb2e8f9f7 1323 CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
<> 144:ef7eb2e8f9f7 1324 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1325 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1330 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1331 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /**
<> 144:ef7eb2e8f9f7 1335 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1336 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1337 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1338 * @retval None
<> 144:ef7eb2e8f9f7 1339 */
<> 144:ef7eb2e8f9f7 1340 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1341 {
<> 144:ef7eb2e8f9f7 1342 /* Transmit data */
<> 144:ef7eb2e8f9f7 1343 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1344 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 if(hi2s->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1347 {
<> 144:ef7eb2e8f9f7 1348 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1349 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1352 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1353 }
<> 144:ef7eb2e8f9f7 1354 }
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /**
<> 144:ef7eb2e8f9f7 1357 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1358 * @param hi2s: I2S handle
<> 144:ef7eb2e8f9f7 1359 * @retval None
<> 144:ef7eb2e8f9f7 1360 */
<> 144:ef7eb2e8f9f7 1361 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1362 {
<> 144:ef7eb2e8f9f7 1363 /* Receive data */
<> 144:ef7eb2e8f9f7 1364 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 1365 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 if(hi2s->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 1368 {
<> 144:ef7eb2e8f9f7 1369 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1370 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1373 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1374 }
<> 144:ef7eb2e8f9f7 1375 }
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /**
<> 144:ef7eb2e8f9f7 1379 * @brief This function handles I2S Communication Timeout.
<> 144:ef7eb2e8f9f7 1380 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1381 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1382 * @param Flag: Flag checked
<> 144:ef7eb2e8f9f7 1383 * @param Status: Value of the flag expected
<> 144:ef7eb2e8f9f7 1384 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 1385 * @retval HAL status
<> 144:ef7eb2e8f9f7 1386 */
<> 144:ef7eb2e8f9f7 1387 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1388 {
<> 144:ef7eb2e8f9f7 1389 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /* Get tick */
<> 144:ef7eb2e8f9f7 1392 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1395 if(Status == RESET)
<> 144:ef7eb2e8f9f7 1396 {
<> 144:ef7eb2e8f9f7 1397 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1400 {
<> 144:ef7eb2e8f9f7 1401 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1402 {
<> 144:ef7eb2e8f9f7 1403 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1404 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1407 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1410 }
<> 144:ef7eb2e8f9f7 1411 }
<> 144:ef7eb2e8f9f7 1412 }
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414 else
<> 144:ef7eb2e8f9f7 1415 {
<> 144:ef7eb2e8f9f7 1416 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1417 {
<> 144:ef7eb2e8f9f7 1418 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1419 {
<> 144:ef7eb2e8f9f7 1420 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1421 {
<> 144:ef7eb2e8f9f7 1422 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1423 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1426 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1429 }
<> 144:ef7eb2e8f9f7 1430 }
<> 144:ef7eb2e8f9f7 1431 }
<> 144:ef7eb2e8f9f7 1432 }
<> 144:ef7eb2e8f9f7 1433 return HAL_OK;
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 /**
<> 144:ef7eb2e8f9f7 1437 * @}
<> 144:ef7eb2e8f9f7 1438 */
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 /**
<> 144:ef7eb2e8f9f7 1441 * @}
<> 144:ef7eb2e8f9f7 1442 */
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1445 #endif /* HAL_I2S_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /**
<> 144:ef7eb2e8f9f7 1449 * @}
<> 144:ef7eb2e8f9f7 1450 */
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/