mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h@144:ef7eb2e8f9f7
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_rcc_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of RCC HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup RCC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup RCC_Private_Macros
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 61 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
<> 144:ef7eb2e8f9f7 62 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
<> 144:ef7eb2e8f9f7 63 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
<> 144:ef7eb2e8f9f7 64 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
<> 144:ef7eb2e8f9f7 65 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
<> 144:ef7eb2e8f9f7 66 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
<> 144:ef7eb2e8f9f7 67 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 70 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 71 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
<> 144:ef7eb2e8f9f7 72 ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
<> 144:ef7eb2e8f9f7 75 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
<> 144:ef7eb2e8f9f7 76 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
<> 144:ef7eb2e8f9f7 77 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 80 ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
<> 144:ef7eb2e8f9f7 81 ((SOURCE) == RCC_PLLSOURCE_HSE))
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #else
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
<> 144:ef7eb2e8f9f7 88 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
<> 144:ef7eb2e8f9f7 89 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
<> 144:ef7eb2e8f9f7 90 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
<> 144:ef7eb2e8f9f7 91 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
<> 144:ef7eb2e8f9f7 92 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
<> 144:ef7eb2e8f9f7 93 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 94 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 95 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
<> 144:ef7eb2e8f9f7 98 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
<> 144:ef7eb2e8f9f7 99 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
<> 144:ef7eb2e8f9f7 100 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 101 ((SOURCE) == RCC_PLLSOURCE_HSE))
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 #if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
<> 144:ef7eb2e8f9f7 108 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 109 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 110 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 111 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 112 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 113 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
<> 144:ef7eb2e8f9f7 114 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 115 ((SOURCE) == RCC_MCO1SOURCE_HSI14))
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
<> 144:ef7eb2e8f9f7 120 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 121 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 122 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 123 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 124 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 125 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
<> 144:ef7eb2e8f9f7 126 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 127 ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \
<> 144:ef7eb2e8f9f7 128 ((SOURCE) == RCC_MCO1SOURCE_HSI48))
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
<> 144:ef7eb2e8f9f7 133 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
<> 144:ef7eb2e8f9f7 134 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 135 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 136 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 137 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 138 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \
<> 144:ef7eb2e8f9f7 139 ((SOURCE) == RCC_MCO1SOURCE_HSI14))
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 #endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @}
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @addtogroup RCC_Exported_Constants
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @addtogroup RCC_PLL_Clock_Source
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
<> 144:ef7eb2e8f9f7 156 #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @addtogroup RCC_Interrupt
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 #define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /** @addtogroup RCC_Flag
<> 144:ef7eb2e8f9f7 171 * @{
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @addtogroup RCC_System_Clock_Source
<> 144:ef7eb2e8f9f7 179 * @{
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @}
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /** @addtogroup RCC_System_Clock_Source_Status
<> 144:ef7eb2e8f9f7 187 * @{
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 #else
<> 144:ef7eb2e8f9f7 195 /** @addtogroup RCC_PLL_Clock_Source
<> 144:ef7eb2e8f9f7 196 * @{
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 200 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
<> 144:ef7eb2e8f9f7 201 #else
<> 144:ef7eb2e8f9f7 202 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
<> 144:ef7eb2e8f9f7 203 #endif
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @}
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @addtogroup RCC_MCO_Clock_Source
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #if defined(RCC_CFGR_PLLNODIV)
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 #endif /* RCC_CFGR_PLLNODIV */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #if defined(RCC_CFGR_MCO_HSI48)
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #endif /* SRCC_CFGR_MCO_HSI48 */
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @}
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /** @addtogroup RCCEx
<> 144:ef7eb2e8f9f7 239 * @{
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Private Constants -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 243 #if defined(CRS)
<> 144:ef7eb2e8f9f7 244 /** @addtogroup RCCEx_Private_Constants
<> 144:ef7eb2e8f9f7 245 * @{
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* CRS IT Error Mask */
<> 144:ef7eb2e8f9f7 249 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* CRS Flag Error Mask */
<> 144:ef7eb2e8f9f7 252 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @}
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 #endif /* CRS */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 260 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
<> 144:ef7eb2e8f9f7 261 * @{
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 264 || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 267 RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 268 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
<> 144:ef7eb2e8f9f7 269 STM32F030xC */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 274 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 275 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 #if defined(STM32F042x6) || defined(STM32F048xx)
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 280 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
<> 144:ef7eb2e8f9f7 281 RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 282 #endif /* STM32F042x6 || STM32F048xx */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #if defined(STM32F051x8) || defined(STM32F058xx)
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
<> 144:ef7eb2e8f9f7 287 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 288 #endif /* STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #if defined(STM32F071xB)
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
<> 144:ef7eb2e8f9f7 293 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
<> 144:ef7eb2e8f9f7 294 RCC_PERIPHCLK_RTC))
<> 144:ef7eb2e8f9f7 295 #endif /* STM32F071xB */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 #if defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
<> 144:ef7eb2e8f9f7 300 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
<> 144:ef7eb2e8f9f7 301 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 302 #endif /* STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
<> 144:ef7eb2e8f9f7 307 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
<> 144:ef7eb2e8f9f7 308 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
<> 144:ef7eb2e8f9f7 309 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
<> 144:ef7eb2e8f9f7 314 ((SOURCE) == RCC_USBCLKSOURCE_PLL))
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \
<> 144:ef7eb2e8f9f7 321 ((SOURCE) == RCC_USBCLKSOURCE_PLL))
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 326 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 329 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 330 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 331 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 334 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
<> 144:ef7eb2e8f9f7 339 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
<> 144:ef7eb2e8f9f7 340 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 341 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
<> 144:ef7eb2e8f9f7 342 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 346 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 347 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 348 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
<> 144:ef7eb2e8f9f7 351 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
<> 144:ef7eb2e8f9f7 352 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 353 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 354 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 355 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
<> 144:ef7eb2e8f9f7 360 ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
<> 144:ef7eb2e8f9f7 361 ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
<> 144:ef7eb2e8f9f7 362 ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
<> 144:ef7eb2e8f9f7 363 #else
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 #endif /* RCC_CFGR_MCOPRE */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
<> 144:ef7eb2e8f9f7 370 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
<> 144:ef7eb2e8f9f7 371 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
<> 144:ef7eb2e8f9f7 372 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 #if defined(CRS)
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
<> 144:ef7eb2e8f9f7 377 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
<> 144:ef7eb2e8f9f7 378 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
<> 144:ef7eb2e8f9f7 379 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
<> 144:ef7eb2e8f9f7 380 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
<> 144:ef7eb2e8f9f7 381 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
<> 144:ef7eb2e8f9f7 382 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
<> 144:ef7eb2e8f9f7 383 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
<> 144:ef7eb2e8f9f7 384 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
<> 144:ef7eb2e8f9f7 385 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
<> 144:ef7eb2e8f9f7 386 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
<> 144:ef7eb2e8f9f7 387 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
<> 144:ef7eb2e8f9f7 388 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
<> 144:ef7eb2e8f9f7 389 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
<> 144:ef7eb2e8f9f7 390 #endif /* CRS */
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @}
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
<> 144:ef7eb2e8f9f7 398 * @{
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /**
<> 144:ef7eb2e8f9f7 402 * @brief RCC extended clocks structure definition
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 405 || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 406 typedef struct
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 409 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 412 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 415 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 418 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 421 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
<> 144:ef7eb2e8f9f7 422 STM32F030xC */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 425 typedef struct
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 428 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 431 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 434 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 437 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 uint32_t UsbClockSelection; /*!< USB clock source
<> 144:ef7eb2e8f9f7 440 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 443 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 #if defined(STM32F042x6) || defined(STM32F048xx)
<> 144:ef7eb2e8f9f7 446 typedef struct
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 449 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 452 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 455 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 458 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 461 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 uint32_t UsbClockSelection; /*!< USB clock source
<> 144:ef7eb2e8f9f7 464 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 467 #endif /* STM32F042x6 || STM32F048xx */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 #if defined(STM32F051x8) || defined(STM32F058xx)
<> 144:ef7eb2e8f9f7 470 typedef struct
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 473 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 476 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 479 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 482 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 485 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 488 #endif /* STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 #if defined(STM32F071xB)
<> 144:ef7eb2e8f9f7 491 typedef struct
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 494 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 497 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 500 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 uint32_t Usart2ClockSelection; /*!< USART2 clock source
<> 144:ef7eb2e8f9f7 503 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 506 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 509 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 512 #endif /* STM32F071xB */
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 #if defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 515 typedef struct
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 518 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 521 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 524 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 uint32_t Usart2ClockSelection; /*!< USART2 clock source
<> 144:ef7eb2e8f9f7 527 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 530 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 533 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 uint32_t UsbClockSelection; /*!< USB clock source
<> 144:ef7eb2e8f9f7 536 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 539 #endif /* STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 543 typedef struct
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 546 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
<> 144:ef7eb2e8f9f7 549 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 uint32_t Usart1ClockSelection; /*!< USART1 clock source
<> 144:ef7eb2e8f9f7 552 This parameter can be a value of @ref RCC_USART1_Clock_Source */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 uint32_t Usart2ClockSelection; /*!< USART2 clock source
<> 144:ef7eb2e8f9f7 555 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 uint32_t Usart3ClockSelection; /*!< USART3 clock source
<> 144:ef7eb2e8f9f7 558 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<> 144:ef7eb2e8f9f7 561 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 uint32_t CecClockSelection; /*!< HDMI CEC clock source
<> 144:ef7eb2e8f9f7 564 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 567 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 #if defined(CRS)
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /**
<> 144:ef7eb2e8f9f7 572 * @brief RCC_CRS Init structure definition
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 typedef struct
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
<> 144:ef7eb2e8f9f7 577 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 uint32_t Source; /*!< Specifies the SYNC signal source.
<> 144:ef7eb2e8f9f7 580 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
<> 144:ef7eb2e8f9f7 583 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
<> 144:ef7eb2e8f9f7 586 It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
<> 144:ef7eb2e8f9f7 587 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
<> 144:ef7eb2e8f9f7 590 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
<> 144:ef7eb2e8f9f7 593 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 }RCC_CRSInitTypeDef;
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /**
<> 144:ef7eb2e8f9f7 598 * @brief RCC_CRS Synchronization structure definition
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 typedef struct
<> 144:ef7eb2e8f9f7 601 {
<> 144:ef7eb2e8f9f7 602 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
<> 144:ef7eb2e8f9f7 603 This parameter must be a number between 0 and 0xFFFF */
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
<> 144:ef7eb2e8f9f7 606 This parameter must be a number between 0 and 0x3F */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
<> 144:ef7eb2e8f9f7 609 value latched in the time of the last SYNC event.
<> 144:ef7eb2e8f9f7 610 This parameter must be a number between 0 and 0xFFFF */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
<> 144:ef7eb2e8f9f7 613 frequency error counter latched in the time of the last SYNC event.
<> 144:ef7eb2e8f9f7 614 It shows whether the actual frequency is below or above the target.
<> 144:ef7eb2e8f9f7 615 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 }RCC_CRSSynchroInfoTypeDef;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 #endif /* CRS */
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @}
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
<> 144:ef7eb2e8f9f7 628 * @{
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
<> 144:ef7eb2e8f9f7 632 * @{
<> 144:ef7eb2e8f9f7 633 */
<> 144:ef7eb2e8f9f7 634 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 635 || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 636 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 637 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 638 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
<> 144:ef7eb2e8f9f7 641 STM32F030xC */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 644 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 645 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 646 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 647 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 #if defined(STM32F042x6) || defined(STM32F048xx)
<> 144:ef7eb2e8f9f7 652 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 653 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 654 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 655 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 656 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #endif /* STM32F042x6 || STM32F048xx */
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 #if defined(STM32F051x8) || defined(STM32F058xx)
<> 144:ef7eb2e8f9f7 661 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 662 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 663 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 664 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 #endif /* STM32F051x8 || STM32F058xx */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 #if defined(STM32F071xB)
<> 144:ef7eb2e8f9f7 669 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 670 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 671 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 672 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 673 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 #endif /* STM32F071xB */
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 #if defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 678 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 679 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 680 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 681 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 682 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 683 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 #endif /* STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 688 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 689 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 690 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 691 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 692 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 693 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /**
<> 144:ef7eb2e8f9f7 698 * @}
<> 144:ef7eb2e8f9f7 699 */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
<> 144:ef7eb2e8f9f7 704 * @{
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706 #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */
<> 144:ef7eb2e8f9f7 707 #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /**
<> 144:ef7eb2e8f9f7 710 * @}
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 #if defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
<> 144:ef7eb2e8f9f7 718 * @{
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000) /*!< USB clock disabled */
<> 144:ef7eb2e8f9f7 721 #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /**
<> 144:ef7eb2e8f9f7 724 * @}
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 #endif /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 730 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
<> 144:ef7eb2e8f9f7 733 * @{
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
<> 144:ef7eb2e8f9f7 736 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
<> 144:ef7eb2e8f9f7 737 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
<> 144:ef7eb2e8f9f7 738 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /**
<> 144:ef7eb2e8f9f7 741 * @}
<> 144:ef7eb2e8f9f7 742 */
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 745 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
<> 144:ef7eb2e8f9f7 750 * @{
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
<> 144:ef7eb2e8f9f7 753 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
<> 144:ef7eb2e8f9f7 754 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
<> 144:ef7eb2e8f9f7 755 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /**
<> 144:ef7eb2e8f9f7 758 * @}
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 765 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 766 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 767 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
<> 144:ef7eb2e8f9f7 770 * @{
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
<> 144:ef7eb2e8f9f7 773 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /**
<> 144:ef7eb2e8f9f7 776 * @}
<> 144:ef7eb2e8f9f7 777 */
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 780 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 781 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 782 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
<> 144:ef7eb2e8f9f7 785 * @{
<> 144:ef7eb2e8f9f7 786 */
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 791 #define RCC_MCODIV_2 ((uint32_t)0x10000000)
<> 144:ef7eb2e8f9f7 792 #define RCC_MCODIV_4 ((uint32_t)0x20000000)
<> 144:ef7eb2e8f9f7 793 #define RCC_MCODIV_8 ((uint32_t)0x30000000)
<> 144:ef7eb2e8f9f7 794 #define RCC_MCODIV_16 ((uint32_t)0x40000000)
<> 144:ef7eb2e8f9f7 795 #define RCC_MCODIV_32 ((uint32_t)0x50000000)
<> 144:ef7eb2e8f9f7 796 #define RCC_MCODIV_64 ((uint32_t)0x60000000)
<> 144:ef7eb2e8f9f7 797 #define RCC_MCODIV_128 ((uint32_t)0x70000000)
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 #else
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 #endif /* RCC_CFGR_MCOPRE */
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /**
<> 144:ef7eb2e8f9f7 806 * @}
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
<> 144:ef7eb2e8f9f7 810 * @{
<> 144:ef7eb2e8f9f7 811 */
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /*!< Xtal mode lower driving capability */
<> 144:ef7eb2e8f9f7 814 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
<> 144:ef7eb2e8f9f7 815 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
<> 144:ef7eb2e8f9f7 816 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /**
<> 144:ef7eb2e8f9f7 819 * @}
<> 144:ef7eb2e8f9f7 820 */
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 #if defined(CRS)
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
<> 144:ef7eb2e8f9f7 825 * @{
<> 144:ef7eb2e8f9f7 826 */
<> 144:ef7eb2e8f9f7 827 #define RCC_CRS_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 828 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 829 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 830 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 831 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 832 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 833 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /**
<> 144:ef7eb2e8f9f7 836 * @}
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
<> 144:ef7eb2e8f9f7 840 * @{
<> 144:ef7eb2e8f9f7 841 */
<> 144:ef7eb2e8f9f7 842 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
<> 144:ef7eb2e8f9f7 843 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
<> 144:ef7eb2e8f9f7 844 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @}
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
<> 144:ef7eb2e8f9f7 850 * @{
<> 144:ef7eb2e8f9f7 851 */
<> 144:ef7eb2e8f9f7 852 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */
<> 144:ef7eb2e8f9f7 853 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
<> 144:ef7eb2e8f9f7 854 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
<> 144:ef7eb2e8f9f7 855 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
<> 144:ef7eb2e8f9f7 856 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
<> 144:ef7eb2e8f9f7 857 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
<> 144:ef7eb2e8f9f7 858 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
<> 144:ef7eb2e8f9f7 859 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
<> 144:ef7eb2e8f9f7 860 /**
<> 144:ef7eb2e8f9f7 861 * @}
<> 144:ef7eb2e8f9f7 862 */
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
<> 144:ef7eb2e8f9f7 865 * @{
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
<> 144:ef7eb2e8f9f7 868 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @}
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
<> 144:ef7eb2e8f9f7 874 * @{
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
<> 144:ef7eb2e8f9f7 877 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @}
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
<> 144:ef7eb2e8f9f7 883 * @{
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
<> 144:ef7eb2e8f9f7 886 /**
<> 144:ef7eb2e8f9f7 887 * @}
<> 144:ef7eb2e8f9f7 888 */
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
<> 144:ef7eb2e8f9f7 891 * @{
<> 144:ef7eb2e8f9f7 892 */
<> 144:ef7eb2e8f9f7 893 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
<> 144:ef7eb2e8f9f7 894 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
<> 144:ef7eb2e8f9f7 895 corresponds to a higher output frequency */
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @}
<> 144:ef7eb2e8f9f7 898 */
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
<> 144:ef7eb2e8f9f7 901 * @{
<> 144:ef7eb2e8f9f7 902 */
<> 144:ef7eb2e8f9f7 903 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
<> 144:ef7eb2e8f9f7 904 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
<> 144:ef7eb2e8f9f7 905 /**
<> 144:ef7eb2e8f9f7 906 * @}
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
<> 144:ef7eb2e8f9f7 910 * @{
<> 144:ef7eb2e8f9f7 911 */
<> 144:ef7eb2e8f9f7 912 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
<> 144:ef7eb2e8f9f7 913 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
<> 144:ef7eb2e8f9f7 914 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
<> 144:ef7eb2e8f9f7 915 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
<> 144:ef7eb2e8f9f7 916 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
<> 144:ef7eb2e8f9f7 917 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
<> 144:ef7eb2e8f9f7 918 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /**
<> 144:ef7eb2e8f9f7 921 * @}
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
<> 144:ef7eb2e8f9f7 925 * @{
<> 144:ef7eb2e8f9f7 926 */
<> 144:ef7eb2e8f9f7 927 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
<> 144:ef7eb2e8f9f7 928 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
<> 144:ef7eb2e8f9f7 929 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
<> 144:ef7eb2e8f9f7 930 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
<> 144:ef7eb2e8f9f7 931 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
<> 144:ef7eb2e8f9f7 932 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
<> 144:ef7eb2e8f9f7 933 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /**
<> 144:ef7eb2e8f9f7 936 * @}
<> 144:ef7eb2e8f9f7 937 */
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 #endif /* CRS */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /**
<> 144:ef7eb2e8f9f7 942 * @}
<> 144:ef7eb2e8f9f7 943 */
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 946 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
<> 144:ef7eb2e8f9f7 947 * @{
<> 144:ef7eb2e8f9f7 948 */
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
<> 144:ef7eb2e8f9f7 951 * @brief Enables or disables the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 952 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 953 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 954 * using it.
<> 144:ef7eb2e8f9f7 955 * @{
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 960 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 961 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
<> 144:ef7eb2e8f9f7 962 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 963 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
<> 144:ef7eb2e8f9f7 964 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 965 } while(0)
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 #endif /* GPIOD */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 974 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 975 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
<> 144:ef7eb2e8f9f7 976 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 977 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
<> 144:ef7eb2e8f9f7 978 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 979 } while(0)
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 #endif /* GPIOE */
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 986 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 987 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 988 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 #define __HAL_RCC_TSC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 991 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 992 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
<> 144:ef7eb2e8f9f7 993 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 994 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
<> 144:ef7eb2e8f9f7 995 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 996 } while(0)
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1001 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1002 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1003 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1008 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1009 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 1010 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1011 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 1012 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1013 } while(0)
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<> 144:ef7eb2e8f9f7 1020 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1021 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1022 * using it.
<> 144:ef7eb2e8f9f7 1023 */
<> 144:ef7eb2e8f9f7 1024 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1025 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1026 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1027 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1028 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1031 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1032 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 144:ef7eb2e8f9f7 1033 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1034 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<> 144:ef7eb2e8f9f7 1035 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1036 } while(0)
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1041 /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1042 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1043 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1046 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1047 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1048 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1049 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1052 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1053 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 1054 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1055 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 1056 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1057 } while(0)
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1062 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1063 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1064 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 #if defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 1067 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1068 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1069 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1070 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1071
<> 144:ef7eb2e8f9f7 1072 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1073 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1074 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 144:ef7eb2e8f9f7 1075 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1076 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<> 144:ef7eb2e8f9f7 1077 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1078 } while(0)
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 #endif /* STM32F031x6 || STM32F038xx || */
<> 144:ef7eb2e8f9f7 1083 /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1084 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1085 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1086 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1089 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1090 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1091 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1094 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1095 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 1096 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1097 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 1098 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1099 } while(0)
<> 144:ef7eb2e8f9f7 1100 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1101 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1102 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 1103 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1104 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 1105 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1106 } while(0)
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<> 144:ef7eb2e8f9f7 1109 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 #endif /* STM32F030x8 || */
<> 144:ef7eb2e8f9f7 1112 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1113 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1114 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 #if defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1117 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1118 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1121 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1122 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 1123 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1124 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 1125 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1126 } while(0)
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1131 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1132 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1135 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1136 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1137 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1140 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1141 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 144:ef7eb2e8f9f7 1142 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1143 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 144:ef7eb2e8f9f7 1144 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1145 } while(0)
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1150 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1151 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1152 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1155 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1158 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1159 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 1160 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1161 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 1162 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1163 } while(0)
<> 144:ef7eb2e8f9f7 1164 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1165 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1166 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 1167 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1168 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 1169 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1170 } while(0)
<> 144:ef7eb2e8f9f7 1171 #define __HAL_RCC_USART4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1172 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1173 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
<> 144:ef7eb2e8f9f7 1174 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1175 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
<> 144:ef7eb2e8f9f7 1176 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1177 } while(0)
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<> 144:ef7eb2e8f9f7 1180 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<> 144:ef7eb2e8f9f7 1181 #define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1184 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1187 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 #define __HAL_RCC_USB_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1190 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1191 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 144:ef7eb2e8f9f7 1192 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1193 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 144:ef7eb2e8f9f7 1194 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1195 } while(0)
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1200 /* STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
<> 144:ef7eb2e8f9f7 1203 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1206 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1207 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
<> 144:ef7eb2e8f9f7 1208 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1209 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
<> 144:ef7eb2e8f9f7 1210 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1211 } while(0)
<> 144:ef7eb2e8f9f7 1212 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
<> 144:ef7eb2e8f9f7 1215 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1216
<> 144:ef7eb2e8f9f7 1217 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1220 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1221 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
<> 144:ef7eb2e8f9f7 1222 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1223 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
<> 144:ef7eb2e8f9f7 1224 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1225 } while(0)
<> 144:ef7eb2e8f9f7 1226
<> 144:ef7eb2e8f9f7 1227 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 #endif /* CRS */
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 #define __HAL_RCC_USART5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1234 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1235 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
<> 144:ef7eb2e8f9f7 1236 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1237 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
<> 144:ef7eb2e8f9f7 1238 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1239 } while(0)
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<> 144:ef7eb2e8f9f7 1246 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1247 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1248 * using it.
<> 144:ef7eb2e8f9f7 1249 */
<> 144:ef7eb2e8f9f7 1250 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1251 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1252 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1253 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1256 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1257 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
<> 144:ef7eb2e8f9f7 1258 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1259 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
<> 144:ef7eb2e8f9f7 1260 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1261 } while(0)
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1266 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1267 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1268 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1273 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1274 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<> 144:ef7eb2e8f9f7 1275 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1276 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<> 144:ef7eb2e8f9f7 1277 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1278 } while(0)
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 #define __HAL_RCC_USART7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1287 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1288 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
<> 144:ef7eb2e8f9f7 1289 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1290 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
<> 144:ef7eb2e8f9f7 1291 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1292 } while(0)
<> 144:ef7eb2e8f9f7 1293 #define __HAL_RCC_USART8_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1294 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
<> 144:ef7eb2e8f9f7 1296 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
<> 144:ef7eb2e8f9f7 1298 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1299 } while(0)
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
<> 144:ef7eb2e8f9f7 1302 #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 /**
<> 144:ef7eb2e8f9f7 1307 * @}
<> 144:ef7eb2e8f9f7 1308 */
<> 144:ef7eb2e8f9f7 1309
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
<> 144:ef7eb2e8f9f7 1312 * @brief Forces or releases peripheral reset.
<> 144:ef7eb2e8f9f7 1313 * @{
<> 144:ef7eb2e8f9f7 1314 */
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /** @brief Force or release AHB peripheral reset.
<> 144:ef7eb2e8f9f7 1317 */
<> 144:ef7eb2e8f9f7 1318 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 #endif /* GPIOD */
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
<> 144:ef7eb2e8f9f7 1331
<> 144:ef7eb2e8f9f7 1332 #endif /* GPIOE */
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1335 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1336 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1337 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1344 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1345 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1346 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 /** @brief Force or release APB1 peripheral reset.
<> 144:ef7eb2e8f9f7 1349 */
<> 144:ef7eb2e8f9f7 1350 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1351 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1352 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1353 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1354 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
<> 144:ef7eb2e8f9f7 1357 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<> 144:ef7eb2e8f9f7 1360 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1363 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1364 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1365 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 #if defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 1368 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1369 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1370 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1371 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 #endif /* STM32F031x6 || STM32F038xx || */
<> 144:ef7eb2e8f9f7 1378 /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1379 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1380 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1381 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1384 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1385 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1386 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1389 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1392 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 #endif /* STM32F030x8 || */
<> 144:ef7eb2e8f9f7 1395 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1396 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1397 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 #if defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1400 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1401 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1408 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1409 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1412 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1413 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1414 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1421 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1422 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1423 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1426 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1429 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1430 #define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1433 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1434 #define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1437 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1438
<> 144:ef7eb2e8f9f7 1439 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1440 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1447 /* STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
<> 144:ef7eb2e8f9f7 1450 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
<> 144:ef7eb2e8f9f7 1457 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
<> 144:ef7eb2e8f9f7 1462
<> 144:ef7eb2e8f9f7 1463 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 #endif /* CRS */
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 #define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 #define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /** @brief Force or release APB2 peripheral reset.
<> 144:ef7eb2e8f9f7 1477 */
<> 144:ef7eb2e8f9f7 1478 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1479 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1480 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1481 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1482
<> 144:ef7eb2e8f9f7 1483 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1488 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1489 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1490 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 #define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
<> 144:ef7eb2e8f9f7 1503 #define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505 #define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
<> 144:ef7eb2e8f9f7 1506 #define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /**
<> 144:ef7eb2e8f9f7 1511 * @}
<> 144:ef7eb2e8f9f7 1512 */
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1515 * @brief Get the enable or disable status of peripheral clock.
<> 144:ef7eb2e8f9f7 1516 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1517 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1518 * using it.
<> 144:ef7eb2e8f9f7 1519 * @{
<> 144:ef7eb2e8f9f7 1520 */
<> 144:ef7eb2e8f9f7 1521 /** @brief AHB Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1522 */
<> 144:ef7eb2e8f9f7 1523 #if defined(GPIOD)
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
<> 144:ef7eb2e8f9f7 1526 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 #endif /* GPIOD */
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 #if defined(GPIOE)
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
<> 144:ef7eb2e8f9f7 1533 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 #endif /* GPIOE */
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1538 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1539 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1540 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
<> 144:ef7eb2e8f9f7 1543 #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1546 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1547 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1548 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1553 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1556
<> 144:ef7eb2e8f9f7 1557 /** @brief APB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1558 */
<> 144:ef7eb2e8f9f7 1559 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1560 || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1561 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1562 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1563 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1566 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1567
<> 144:ef7eb2e8f9f7 1568 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1569 /* STM32F051x8 || STM32F058xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1570 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1571 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 #if defined(STM32F030x8)\
<> 144:ef7eb2e8f9f7 1574 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1575 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1576 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1577 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1578
<> 144:ef7eb2e8f9f7 1579 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1580 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1583 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1584 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1585 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 #if defined(STM32F031x6) || defined(STM32F038xx)\
<> 144:ef7eb2e8f9f7 1588 || defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1589 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1590 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1591 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1594 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1595
<> 144:ef7eb2e8f9f7 1596 #endif /* STM32F031x6 || STM32F038xx || */
<> 144:ef7eb2e8f9f7 1597 /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1598 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1599 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1600 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1601
<> 144:ef7eb2e8f9f7 1602 #if defined(STM32F030x8) \
<> 144:ef7eb2e8f9f7 1603 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1604 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1605 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1608 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1609 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1610 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 #endif /* STM32F030x8 || */
<> 144:ef7eb2e8f9f7 1613 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1614 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1615 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 #if defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1618 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1619 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1622 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1625 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1626 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1629 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1630 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1631 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
<> 144:ef7eb2e8f9f7 1634 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1637 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1638 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1639 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1640
<> 144:ef7eb2e8f9f7 1641 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1642 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1645 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1646 #define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1647 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1648 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1649 #define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1652 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1655 || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
<> 144:ef7eb2e8f9f7 1658 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1661 /* STM32F072xB || STM32F078xx || STM32F070xB */
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\
<> 144:ef7eb2e8f9f7 1664 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1667 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
<> 144:ef7eb2e8f9f7 1670 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
<> 144:ef7eb2e8f9f7 1675 #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 #endif /* CRS */
<> 144:ef7eb2e8f9f7 1678
<> 144:ef7eb2e8f9f7 1679 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1680
<> 144:ef7eb2e8f9f7 1681 #define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1682 #define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 /** @brief APB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1687 */
<> 144:ef7eb2e8f9f7 1688 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\
<> 144:ef7eb2e8f9f7 1689 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1690 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\
<> 144:ef7eb2e8f9f7 1691 || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
<> 144:ef7eb2e8f9f7 1694 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
<> 144:ef7eb2e8f9f7 1697 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1698 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
<> 144:ef7eb2e8f9f7 1699 /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 1702
<> 144:ef7eb2e8f9f7 1703 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1704 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 #define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1711 #define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
<> 144:ef7eb2e8f9f7 1712 #define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1713 #define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
<> 144:ef7eb2e8f9f7 1714
<> 144:ef7eb2e8f9f7 1715 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1716 /**
<> 144:ef7eb2e8f9f7 1717 * @}
<> 144:ef7eb2e8f9f7 1718 */
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
<> 144:ef7eb2e8f9f7 1722 * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
<> 144:ef7eb2e8f9f7 1723 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1724 * @note HSI48 can not be stopped if it is used as system clock source. In this case,
<> 144:ef7eb2e8f9f7 1725 * you have to select another source of the system clock then stop the HSI14.
<> 144:ef7eb2e8f9f7 1726 * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
<> 144:ef7eb2e8f9f7 1727 * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
<> 144:ef7eb2e8f9f7 1728 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
<> 144:ef7eb2e8f9f7 1729 * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
<> 144:ef7eb2e8f9f7 1730 * clock cycles.
<> 144:ef7eb2e8f9f7 1731 * @{
<> 144:ef7eb2e8f9f7 1732 */
<> 144:ef7eb2e8f9f7 1733 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
<> 144:ef7eb2e8f9f7 1736 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
<> 144:ef7eb2e8f9f7 1737
<> 144:ef7eb2e8f9f7 1738 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
<> 144:ef7eb2e8f9f7 1739 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1740 * @arg @ref RCC_HSI48_ON HSI48 enabled
<> 144:ef7eb2e8f9f7 1741 * @arg @ref RCC_HSI48_OFF HSI48 disabled
<> 144:ef7eb2e8f9f7 1742 */
<> 144:ef7eb2e8f9f7 1743 #define __HAL_RCC_GET_HSI48_STATE() \
<> 144:ef7eb2e8f9f7 1744 (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /**
<> 144:ef7eb2e8f9f7 1749 * @}
<> 144:ef7eb2e8f9f7 1750 */
<> 144:ef7eb2e8f9f7 1751
<> 144:ef7eb2e8f9f7 1752 /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
<> 144:ef7eb2e8f9f7 1753 * @{
<> 144:ef7eb2e8f9f7 1754 */
<> 144:ef7eb2e8f9f7 1755 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1756 || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1757 || defined(STM32F070x6) || defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 1758
<> 144:ef7eb2e8f9f7 1759 /** @brief Macro to configure the USB clock (USBCLK).
<> 144:ef7eb2e8f9f7 1760 * @param __USBCLKSOURCE__ specifies the USB clock source.
<> 144:ef7eb2e8f9f7 1761 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1762 @if STM32F070xB
<> 144:ef7eb2e8f9f7 1763 @elseif STM32F070x6
<> 144:ef7eb2e8f9f7 1764 @else
<> 144:ef7eb2e8f9f7 1765 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
<> 144:ef7eb2e8f9f7 1766 @endif
<> 144:ef7eb2e8f9f7 1767 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
<> 144:ef7eb2e8f9f7 1768 */
<> 144:ef7eb2e8f9f7 1769 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1770 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1771
<> 144:ef7eb2e8f9f7 1772 /** @brief Macro to get the USB clock source.
<> 144:ef7eb2e8f9f7 1773 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1774 @if STM32F070xB
<> 144:ef7eb2e8f9f7 1775 @elseif STM32F070x6
<> 144:ef7eb2e8f9f7 1776 @else
<> 144:ef7eb2e8f9f7 1777 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
<> 144:ef7eb2e8f9f7 1778 @endif
<> 144:ef7eb2e8f9f7 1779 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
<> 144:ef7eb2e8f9f7 1780 */
<> 144:ef7eb2e8f9f7 1781 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
<> 144:ef7eb2e8f9f7 1782
<> 144:ef7eb2e8f9f7 1783 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1784 /* STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1785 /* STM32F070x6 || STM32F070xB */
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 #if defined(STM32F042x6) || defined(STM32F048xx)\
<> 144:ef7eb2e8f9f7 1788 || defined(STM32F051x8) || defined(STM32F058xx)\
<> 144:ef7eb2e8f9f7 1789 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1790 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1791
<> 144:ef7eb2e8f9f7 1792 /** @brief Macro to configure the CEC clock.
<> 144:ef7eb2e8f9f7 1793 * @param __CECCLKSOURCE__ specifies the CEC clock source.
<> 144:ef7eb2e8f9f7 1794 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1795 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
<> 144:ef7eb2e8f9f7 1796 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
<> 144:ef7eb2e8f9f7 1797 */
<> 144:ef7eb2e8f9f7 1798 #define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1799 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1800
<> 144:ef7eb2e8f9f7 1801 /** @brief Macro to get the HDMI CEC clock source.
<> 144:ef7eb2e8f9f7 1802 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1803 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
<> 144:ef7eb2e8f9f7 1804 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
<> 144:ef7eb2e8f9f7 1805 */
<> 144:ef7eb2e8f9f7 1806 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
<> 144:ef7eb2e8f9f7 1807
<> 144:ef7eb2e8f9f7 1808 #endif /* STM32F042x6 || STM32F048xx || */
<> 144:ef7eb2e8f9f7 1809 /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1810 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 144:ef7eb2e8f9f7 1811 /* STM32F091xC || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
<> 144:ef7eb2e8f9f7 1814 || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1815 /** @brief Macro to configure the USART2 clock (USART2CLK).
<> 144:ef7eb2e8f9f7 1816 * @param __USART2CLKSOURCE__ specifies the USART2 clock source.
<> 144:ef7eb2e8f9f7 1817 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1818 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
<> 144:ef7eb2e8f9f7 1819 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
<> 144:ef7eb2e8f9f7 1820 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
<> 144:ef7eb2e8f9f7 1821 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
<> 144:ef7eb2e8f9f7 1822 */
<> 144:ef7eb2e8f9f7 1823 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1824 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 /** @brief Macro to get the USART2 clock source.
<> 144:ef7eb2e8f9f7 1827 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1828 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
<> 144:ef7eb2e8f9f7 1829 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
<> 144:ef7eb2e8f9f7 1830 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
<> 144:ef7eb2e8f9f7 1831 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
<> 144:ef7eb2e8f9f7 1832 */
<> 144:ef7eb2e8f9f7 1833 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
<> 144:ef7eb2e8f9f7 1834 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/
<> 144:ef7eb2e8f9f7 1835
<> 144:ef7eb2e8f9f7 1836 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1837 /** @brief Macro to configure the USART3 clock (USART3CLK).
<> 144:ef7eb2e8f9f7 1838 * @param __USART3CLKSOURCE__ specifies the USART3 clock source.
<> 144:ef7eb2e8f9f7 1839 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1840 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
<> 144:ef7eb2e8f9f7 1841 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
<> 144:ef7eb2e8f9f7 1842 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
<> 144:ef7eb2e8f9f7 1843 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
<> 144:ef7eb2e8f9f7 1844 */
<> 144:ef7eb2e8f9f7 1845 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1846 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /** @brief Macro to get the USART3 clock source.
<> 144:ef7eb2e8f9f7 1849 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1850 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
<> 144:ef7eb2e8f9f7 1851 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
<> 144:ef7eb2e8f9f7 1852 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
<> 144:ef7eb2e8f9f7 1853 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
<> 144:ef7eb2e8f9f7 1854 */
<> 144:ef7eb2e8f9f7 1855 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1858 /**
<> 144:ef7eb2e8f9f7 1859 * @}
<> 144:ef7eb2e8f9f7 1860 */
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
<> 144:ef7eb2e8f9f7 1863 * @{
<> 144:ef7eb2e8f9f7 1864 */
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /**
<> 144:ef7eb2e8f9f7 1867 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
<> 144:ef7eb2e8f9f7 1868 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
<> 144:ef7eb2e8f9f7 1869 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1870 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
<> 144:ef7eb2e8f9f7 1871 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
<> 144:ef7eb2e8f9f7 1872 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
<> 144:ef7eb2e8f9f7 1873 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
<> 144:ef7eb2e8f9f7 1874 * @retval None
<> 144:ef7eb2e8f9f7 1875 */
<> 144:ef7eb2e8f9f7 1876 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
<> 144:ef7eb2e8f9f7 1877 RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
<> 144:ef7eb2e8f9f7 1878
<> 144:ef7eb2e8f9f7 1879 /**
<> 144:ef7eb2e8f9f7 1880 * @}
<> 144:ef7eb2e8f9f7 1881 */
<> 144:ef7eb2e8f9f7 1882
<> 144:ef7eb2e8f9f7 1883 #if defined(CRS)
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
<> 144:ef7eb2e8f9f7 1886 * @{
<> 144:ef7eb2e8f9f7 1887 */
<> 144:ef7eb2e8f9f7 1888 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 1889
<> 144:ef7eb2e8f9f7 1890 /**
<> 144:ef7eb2e8f9f7 1891 * @brief Enable the specified CRS interrupts.
<> 144:ef7eb2e8f9f7 1892 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 1893 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1894 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1895 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1896 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1897 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1898 * @retval None
<> 144:ef7eb2e8f9f7 1899 */
<> 144:ef7eb2e8f9f7 1900 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1901
<> 144:ef7eb2e8f9f7 1902 /**
<> 144:ef7eb2e8f9f7 1903 * @brief Disable the specified CRS interrupts.
<> 144:ef7eb2e8f9f7 1904 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 1905 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1906 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1907 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1908 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1909 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1910 * @retval None
<> 144:ef7eb2e8f9f7 1911 */
<> 144:ef7eb2e8f9f7 1912 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1913
<> 144:ef7eb2e8f9f7 1914 /** @brief Check whether the CRS interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 1915 * @param __INTERRUPT__ specifies the CRS interrupt source to check.
<> 144:ef7eb2e8f9f7 1916 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1917 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1918 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1919 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1920 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1921 * @retval The new state of __INTERRUPT__ (SET or RESET).
<> 144:ef7eb2e8f9f7 1922 */
<> 144:ef7eb2e8f9f7 1923 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 /** @brief Clear the CRS interrupt pending bits
<> 144:ef7eb2e8f9f7 1926 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 1927 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1928 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
<> 144:ef7eb2e8f9f7 1929 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
<> 144:ef7eb2e8f9f7 1930 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
<> 144:ef7eb2e8f9f7 1931 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
<> 144:ef7eb2e8f9f7 1932 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
<> 144:ef7eb2e8f9f7 1933 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
<> 144:ef7eb2e8f9f7 1934 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
<> 144:ef7eb2e8f9f7 1935 */
<> 144:ef7eb2e8f9f7 1936 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
<> 144:ef7eb2e8f9f7 1937 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
<> 144:ef7eb2e8f9f7 1938 { \
<> 144:ef7eb2e8f9f7 1939 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
<> 144:ef7eb2e8f9f7 1940 } \
<> 144:ef7eb2e8f9f7 1941 else \
<> 144:ef7eb2e8f9f7 1942 { \
<> 144:ef7eb2e8f9f7 1943 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
<> 144:ef7eb2e8f9f7 1944 } \
<> 144:ef7eb2e8f9f7 1945 } while(0)
<> 144:ef7eb2e8f9f7 1946
<> 144:ef7eb2e8f9f7 1947 /**
<> 144:ef7eb2e8f9f7 1948 * @brief Check whether the specified CRS flag is set or not.
<> 144:ef7eb2e8f9f7 1949 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 1950 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1951 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
<> 144:ef7eb2e8f9f7 1952 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
<> 144:ef7eb2e8f9f7 1953 * @arg @ref RCC_CRS_FLAG_ERR Error
<> 144:ef7eb2e8f9f7 1954 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
<> 144:ef7eb2e8f9f7 1955 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
<> 144:ef7eb2e8f9f7 1956 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
<> 144:ef7eb2e8f9f7 1957 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
<> 144:ef7eb2e8f9f7 1958 * @retval The new state of _FLAG_ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 1959 */
<> 144:ef7eb2e8f9f7 1960 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /**
<> 144:ef7eb2e8f9f7 1963 * @brief Clear the CRS specified FLAG.
<> 144:ef7eb2e8f9f7 1964 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 1965 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1966 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
<> 144:ef7eb2e8f9f7 1967 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
<> 144:ef7eb2e8f9f7 1968 * @arg @ref RCC_CRS_FLAG_ERR Error
<> 144:ef7eb2e8f9f7 1969 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
<> 144:ef7eb2e8f9f7 1970 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
<> 144:ef7eb2e8f9f7 1971 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
<> 144:ef7eb2e8f9f7 1972 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
<> 144:ef7eb2e8f9f7 1973 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
<> 144:ef7eb2e8f9f7 1974 * @retval None
<> 144:ef7eb2e8f9f7 1975 */
<> 144:ef7eb2e8f9f7 1976 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
<> 144:ef7eb2e8f9f7 1977 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
<> 144:ef7eb2e8f9f7 1978 { \
<> 144:ef7eb2e8f9f7 1979 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
<> 144:ef7eb2e8f9f7 1980 } \
<> 144:ef7eb2e8f9f7 1981 else \
<> 144:ef7eb2e8f9f7 1982 { \
<> 144:ef7eb2e8f9f7 1983 WRITE_REG(CRS->ICR, (__FLAG__)); \
<> 144:ef7eb2e8f9f7 1984 } \
<> 144:ef7eb2e8f9f7 1985 } while(0)
<> 144:ef7eb2e8f9f7 1986
<> 144:ef7eb2e8f9f7 1987 /**
<> 144:ef7eb2e8f9f7 1988 * @}
<> 144:ef7eb2e8f9f7 1989 */
<> 144:ef7eb2e8f9f7 1990
<> 144:ef7eb2e8f9f7 1991 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
<> 144:ef7eb2e8f9f7 1992 * @{
<> 144:ef7eb2e8f9f7 1993 */
<> 144:ef7eb2e8f9f7 1994 /**
<> 144:ef7eb2e8f9f7 1995 * @brief Enable the oscillator clock for frequency error counter.
<> 144:ef7eb2e8f9f7 1996 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
<> 144:ef7eb2e8f9f7 1997 * @retval None
<> 144:ef7eb2e8f9f7 1998 */
<> 144:ef7eb2e8f9f7 1999 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001 /**
<> 144:ef7eb2e8f9f7 2002 * @brief Disable the oscillator clock for frequency error counter.
<> 144:ef7eb2e8f9f7 2003 * @retval None
<> 144:ef7eb2e8f9f7 2004 */
<> 144:ef7eb2e8f9f7 2005 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
<> 144:ef7eb2e8f9f7 2006
<> 144:ef7eb2e8f9f7 2007 /**
<> 144:ef7eb2e8f9f7 2008 * @brief Enable the automatic hardware adjustement of TRIM bits.
<> 144:ef7eb2e8f9f7 2009 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
<> 144:ef7eb2e8f9f7 2010 * @retval None
<> 144:ef7eb2e8f9f7 2011 */
<> 144:ef7eb2e8f9f7 2012 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 /**
<> 144:ef7eb2e8f9f7 2015 * @brief Disable the automatic hardware adjustement of TRIM bits.
<> 144:ef7eb2e8f9f7 2016 * @retval None
<> 144:ef7eb2e8f9f7 2017 */
<> 144:ef7eb2e8f9f7 2018 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
<> 144:ef7eb2e8f9f7 2019
<> 144:ef7eb2e8f9f7 2020 /**
<> 144:ef7eb2e8f9f7 2021 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
<> 144:ef7eb2e8f9f7 2022 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
<> 144:ef7eb2e8f9f7 2023 * of the synchronization source after prescaling. It is then decreased by one in order to
<> 144:ef7eb2e8f9f7 2024 * reach the expected synchronization on the zero value. The formula is the following:
<> 144:ef7eb2e8f9f7 2025 * RELOAD = (fTARGET / fSYNC) -1
<> 144:ef7eb2e8f9f7 2026 * @param __FTARGET__ Target frequency (value in Hz)
<> 144:ef7eb2e8f9f7 2027 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
<> 144:ef7eb2e8f9f7 2028 * @retval None
<> 144:ef7eb2e8f9f7 2029 */
<> 144:ef7eb2e8f9f7 2030 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
<> 144:ef7eb2e8f9f7 2031
<> 144:ef7eb2e8f9f7 2032 /**
<> 144:ef7eb2e8f9f7 2033 * @}
<> 144:ef7eb2e8f9f7 2034 */
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 #endif /* CRS */
<> 144:ef7eb2e8f9f7 2037
<> 144:ef7eb2e8f9f7 2038 /**
<> 144:ef7eb2e8f9f7 2039 * @}
<> 144:ef7eb2e8f9f7 2040 */
<> 144:ef7eb2e8f9f7 2041
<> 144:ef7eb2e8f9f7 2042 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2043 /** @addtogroup RCCEx_Exported_Functions
<> 144:ef7eb2e8f9f7 2044 * @{
<> 144:ef7eb2e8f9f7 2045 */
<> 144:ef7eb2e8f9f7 2046
<> 144:ef7eb2e8f9f7 2047 /** @addtogroup RCCEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 2048 * @{
<> 144:ef7eb2e8f9f7 2049 */
<> 144:ef7eb2e8f9f7 2050
<> 144:ef7eb2e8f9f7 2051 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 2052 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 2053 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
<> 144:ef7eb2e8f9f7 2054
<> 144:ef7eb2e8f9f7 2055 /**
<> 144:ef7eb2e8f9f7 2056 * @}
<> 144:ef7eb2e8f9f7 2057 */
<> 144:ef7eb2e8f9f7 2058
<> 144:ef7eb2e8f9f7 2059 #if defined(CRS)
<> 144:ef7eb2e8f9f7 2060
<> 144:ef7eb2e8f9f7 2061 /** @addtogroup RCCEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 2062 * @{
<> 144:ef7eb2e8f9f7 2063 */
<> 144:ef7eb2e8f9f7 2064
<> 144:ef7eb2e8f9f7 2065 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
<> 144:ef7eb2e8f9f7 2066 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
<> 144:ef7eb2e8f9f7 2067 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
<> 144:ef7eb2e8f9f7 2068 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 2069 void HAL_RCCEx_CRS_IRQHandler(void);
<> 144:ef7eb2e8f9f7 2070 void HAL_RCCEx_CRS_SyncOkCallback(void);
<> 144:ef7eb2e8f9f7 2071 void HAL_RCCEx_CRS_SyncWarnCallback(void);
<> 144:ef7eb2e8f9f7 2072 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
<> 144:ef7eb2e8f9f7 2073 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
<> 144:ef7eb2e8f9f7 2074
<> 144:ef7eb2e8f9f7 2075 /**
<> 144:ef7eb2e8f9f7 2076 * @}
<> 144:ef7eb2e8f9f7 2077 */
<> 144:ef7eb2e8f9f7 2078
<> 144:ef7eb2e8f9f7 2079 #endif /* CRS */
<> 144:ef7eb2e8f9f7 2080
<> 144:ef7eb2e8f9f7 2081 /**
<> 144:ef7eb2e8f9f7 2082 * @}
<> 144:ef7eb2e8f9f7 2083 */
<> 144:ef7eb2e8f9f7 2084
<> 144:ef7eb2e8f9f7 2085 /**
<> 144:ef7eb2e8f9f7 2086 * @}
<> 144:ef7eb2e8f9f7 2087 */
<> 144:ef7eb2e8f9f7 2088
<> 144:ef7eb2e8f9f7 2089 /**
<> 144:ef7eb2e8f9f7 2090 * @}
<> 144:ef7eb2e8f9f7 2091 */
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 /**
<> 144:ef7eb2e8f9f7 2094 * @}
<> 144:ef7eb2e8f9f7 2095 */
<> 144:ef7eb2e8f9f7 2096
<> 144:ef7eb2e8f9f7 2097 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 2098 }
<> 144:ef7eb2e8f9f7 2099 #endif
<> 144:ef7eb2e8f9f7 2100
<> 144:ef7eb2e8f9f7 2101 #endif /* __STM32F0xx_HAL_RCC_EX_H */
<> 144:ef7eb2e8f9f7 2102
<> 144:ef7eb2e8f9f7 2103 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/