mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_cortex.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_cortex.c@144:ef7eb2e8f9f7
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief CORTEX HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 *** How to configure Interrupts using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 20 ===========================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 23 The Cortex-M0 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 24 (#) Enable and Configure the priority of the selected IRQ Channels.
<> 144:ef7eb2e8f9f7 25 The priority can be 0..3.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 -@- Lower priority values gives higher priority.
<> 144:ef7eb2e8f9f7 28 -@- Priority Order:
<> 144:ef7eb2e8f9f7 29 (#@) Lowest priority.
<> 144:ef7eb2e8f9f7 30 (#@) Lowest hardware priority (IRQn position).
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 -@- Negative value of IRQn_Type are not allowed.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 *** How to configure Systick using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 41 ========================================================
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 Setup SysTick Timer for time base.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 46 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 47 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 144:ef7eb2e8f9f7 48 (++) Configures the SysTick IRQ priority to the lowest value (0x03).
<> 144:ef7eb2e8f9f7 49 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 51 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 52 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
<> 144:ef7eb2e8f9f7 55 HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 144:ef7eb2e8f9f7 56 HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined
<> 144:ef7eb2e8f9f7 57 inside the stm32f0xx_hal_cortex.h file.
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 67 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 @endverbatim
<> 144:ef7eb2e8f9f7 70 ******************************************************************************
<> 144:ef7eb2e8f9f7 71 * @attention
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 76 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 77 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 81 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 83 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 84 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 85 *
<> 144:ef7eb2e8f9f7 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 ******************************************************************************
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** @defgroup CORTEX CORTEX
<> 144:ef7eb2e8f9f7 108 * @brief CORTEX CORTEX HAL module driver
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 127 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 @verbatim
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 132 ==============================================================================
<> 144:ef7eb2e8f9f7 133 [..]
<> 144:ef7eb2e8f9f7 134 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 135 Systick functionalities
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 @endverbatim
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @brief Sets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 143 * @param IRQn: External interrupt number .
<> 144:ef7eb2e8f9f7 144 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 145 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32l0xx.h file)
<> 144:ef7eb2e8f9f7 146 * @param PreemptPriority: The preemption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 147 * This parameter can be a value between 0 and 3.
<> 144:ef7eb2e8f9f7 148 * A lower priority value indicates a higher priority
<> 144:ef7eb2e8f9f7 149 * @param SubPriority: the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 150 * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because
<> 144:ef7eb2e8f9f7 151 * no subpriority supported in Cortex M0 based products.
<> 144:ef7eb2e8f9f7 152 * @retval None
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 /* Check the parameters */
<> 144:ef7eb2e8f9f7 157 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 158 NVIC_SetPriority(IRQn,PreemptPriority);
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 163 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 164 * function should be called before.
<> 144:ef7eb2e8f9f7 165 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 166 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 167 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 168 * @retval None
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 /* Check the parameters */
<> 144:ef7eb2e8f9f7 173 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 176 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 181 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 182 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 183 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 184 * @retval None
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 /* Check the parameters */
<> 144:ef7eb2e8f9f7 189 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 192 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @brief Initiates a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 197 * @retval None
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 /* System Reset */
<> 144:ef7eb2e8f9f7 202 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 144:ef7eb2e8f9f7 207 * Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 208 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 209 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 210 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @}
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 221 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 222 *
<> 144:ef7eb2e8f9f7 223 @verbatim
<> 144:ef7eb2e8f9f7 224 ==============================================================================
<> 144:ef7eb2e8f9f7 225 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 226 ==============================================================================
<> 144:ef7eb2e8f9f7 227 [..]
<> 144:ef7eb2e8f9f7 228 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 229 (NVIC, SYSTICK) functionalities.
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 @endverbatim
<> 144:ef7eb2e8f9f7 233 * @{
<> 144:ef7eb2e8f9f7 234 */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief Gets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 239 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 240 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 241 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 242 * @retval None
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 247 return NVIC_GetPriority(IRQn);
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /**
<> 144:ef7eb2e8f9f7 251 * @brief Sets Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 252 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 253 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 254 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 255 * @retval None
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 /* Check the parameters */
<> 144:ef7eb2e8f9f7 260 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 263 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
<> 144:ef7eb2e8f9f7 268 * and returns the pending bit for the specified interrupt).
<> 144:ef7eb2e8f9f7 269 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 270 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 271 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 272 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 273 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 /* Check the parameters */
<> 144:ef7eb2e8f9f7 278 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 281 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @brief Clears the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 286 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 287 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 288 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h))
<> 144:ef7eb2e8f9f7 289 * @retval None
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* Check the parameters */
<> 144:ef7eb2e8f9f7 294 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 297 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @brief Configures the SysTick clock source.
<> 144:ef7eb2e8f9f7 302 * @param CLKSource: specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 303 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 304 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 305 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 306 * @retval None
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 309 {
<> 144:ef7eb2e8f9f7 310 /* Check the parameters */
<> 144:ef7eb2e8f9f7 311 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 312 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316 else
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @brief This function handles SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 324 * @retval None
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 333 * @retval None
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 338 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @}
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @}
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @}
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @}
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/