mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_can.c@144:ef7eb2e8f9f7
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_can.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief CAN HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Controller Area Network (CAN) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 (#) CAN pins configuration
<> 144:ef7eb2e8f9f7 23 (++) Enable the clock for the CAN GPIOs using the following function:
<> 144:ef7eb2e8f9f7 24 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 25 (++) Connect and configure the involved CAN pins to AF9 using the
<> 144:ef7eb2e8f9f7 26 following function HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 (#) Initialise and configure the CAN using HAL_CAN_Init() function.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 (#) Receive a CAN frame using HAL_CAN_Receive() function.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 35 =================================
<> 144:ef7eb2e8f9f7 36 [..]
<> 144:ef7eb2e8f9f7 37 (+) Start the CAN peripheral transmission and wait the end of this operation
<> 144:ef7eb2e8f9f7 38 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 39 according to his end application
<> 144:ef7eb2e8f9f7 40 (+) Start the CAN peripheral reception and wait the end of this operation
<> 144:ef7eb2e8f9f7 41 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 42 according to his end application
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 45 ===================================
<> 144:ef7eb2e8f9f7 46 [..]
<> 144:ef7eb2e8f9f7 47 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
<> 144:ef7eb2e8f9f7 48 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
<> 144:ef7eb2e8f9f7 49 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
<> 144:ef7eb2e8f9f7 50 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 51 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
<> 144:ef7eb2e8f9f7 52 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 53 add his own code by customization of function pointer HAL_CAN_ErrorCallback
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 *** CAN HAL driver macros list ***
<> 144:ef7eb2e8f9f7 56 =============================================
<> 144:ef7eb2e8f9f7 57 [..]
<> 144:ef7eb2e8f9f7 58 Below the list of most used macros in CAN HAL driver.
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 61 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 62 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
<> 144:ef7eb2e8f9f7 63 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
<> 144:ef7eb2e8f9f7 64 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 [..]
<> 144:ef7eb2e8f9f7 67 (@) You can refer to the CAN HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 @endverbatim
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 ******************************************************************************
<> 144:ef7eb2e8f9f7 72 * @attention
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 77 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 78 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 79 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 81 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 82 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 84 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 85 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 86 *
<> 144:ef7eb2e8f9f7 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 102 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 #ifdef HAL_CAN_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /** @defgroup CAN CAN
<> 144:ef7eb2e8f9f7 113 * @brief CAN driver modules
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup CAN_Private_Constants CAN Private Constants
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 #define CAN_TIMEOUT_VALUE 10
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /** @defgroup CAN_Private_Functions CAN Private Functions
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 133 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** @defgroup CAN_Exported_Functions CAN Exported Functions
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 145 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 @verbatim
<> 144:ef7eb2e8f9f7 148 ==============================================================================
<> 144:ef7eb2e8f9f7 149 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 150 ==============================================================================
<> 144:ef7eb2e8f9f7 151 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 152 (+) Initialize and configure the CAN.
<> 144:ef7eb2e8f9f7 153 (+) De-initialize the CAN.
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 @endverbatim
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief Initializes the CAN peripheral according to the specified
<> 144:ef7eb2e8f9f7 161 * parameters in the CAN_InitStruct.
<> 144:ef7eb2e8f9f7 162 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 163 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 164 * @retval HAL status
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
<> 144:ef7eb2e8f9f7 169 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 172 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Check the parameters */
<> 144:ef7eb2e8f9f7 178 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 179 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
<> 144:ef7eb2e8f9f7 183 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_CAN_MODE(hcan->Init.Mode));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_CAN_SJW(hcan->Init.SJW));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_CAN_BS1(hcan->Init.BS1));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_CAN_BS2(hcan->Init.BS2));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 if(hcan->State == HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 194 hcan->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 195 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 196 HAL_CAN_MspInit(hcan);
<> 144:ef7eb2e8f9f7 197 }
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Initialize the CAN state*/
<> 144:ef7eb2e8f9f7 200 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Exit from sleep mode */
<> 144:ef7eb2e8f9f7 203 hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Request initialisation */
<> 144:ef7eb2e8f9f7 206 hcan->Instance->MCR |= CAN_MCR_INRQ ;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Get tick */
<> 144:ef7eb2e8f9f7 209 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 212 while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 217 /* Process unlocked */
<> 144:ef7eb2e8f9f7 218 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 219 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Check acknowledge */
<> 144:ef7eb2e8f9f7 224 if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 /* Set the time triggered communication mode */
<> 144:ef7eb2e8f9f7 227 if (hcan->Init.TTCM == ENABLE)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 hcan->Instance->MCR |= CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231 else
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Set the automatic bus-off management */
<> 144:ef7eb2e8f9f7 237 if (hcan->Init.ABOM == ENABLE)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 hcan->Instance->MCR |= CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 else
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Set the automatic wake-up mode */
<> 144:ef7eb2e8f9f7 247 if (hcan->Init.AWUM == ENABLE)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 hcan->Instance->MCR |= CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 else
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Set the no automatic retransmission */
<> 144:ef7eb2e8f9f7 257 if (hcan->Init.NART == ENABLE)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 hcan->Instance->MCR |= CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 else
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Set the receive FIFO locked mode */
<> 144:ef7eb2e8f9f7 267 if (hcan->Init.RFLM == ENABLE)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 hcan->Instance->MCR |= CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271 else
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Set the transmit FIFO priority */
<> 144:ef7eb2e8f9f7 277 if (hcan->Init.TXFP == ENABLE)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 hcan->Instance->MCR |= CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 280 }
<> 144:ef7eb2e8f9f7 281 else
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Set the bit timing register */
<> 144:ef7eb2e8f9f7 287 hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
<> 144:ef7eb2e8f9f7 288 ((uint32_t)hcan->Init.SJW) | \
<> 144:ef7eb2e8f9f7 289 ((uint32_t)hcan->Init.BS1) | \
<> 144:ef7eb2e8f9f7 290 ((uint32_t)hcan->Init.BS2) | \
<> 144:ef7eb2e8f9f7 291 ((uint32_t)hcan->Init.Prescaler - 1);
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /* Request leave initialisation */
<> 144:ef7eb2e8f9f7 294 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Get tick */
<> 144:ef7eb2e8f9f7 297 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 300 while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 305 /* Process unlocked */
<> 144:ef7eb2e8f9f7 306 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 307 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Check acknowledged */
<> 144:ef7eb2e8f9f7 312 if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 status = CAN_INITSTATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 if(status == CAN_INITSTATUS_SUCCESS)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 321 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 324 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Return function status */
<> 144:ef7eb2e8f9f7 327 return HAL_OK;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329 else
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 332 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Return function status */
<> 144:ef7eb2e8f9f7 335 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /**
<> 144:ef7eb2e8f9f7 340 * @brief Configures the CAN reception filter according to the specified
<> 144:ef7eb2e8f9f7 341 * parameters in the CAN_FilterInitStruct.
<> 144:ef7eb2e8f9f7 342 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 343 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 344 * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
<> 144:ef7eb2e8f9f7 345 * contains the filter configuration information.
<> 144:ef7eb2e8f9f7 346 * @retval None
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 uint32_t filternbrbitpos = 0;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Check the parameters */
<> 144:ef7eb2e8f9f7 353 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
<> 144:ef7eb2e8f9f7 354 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
<> 144:ef7eb2e8f9f7 355 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
<> 144:ef7eb2e8f9f7 356 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
<> 144:ef7eb2e8f9f7 357 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
<> 144:ef7eb2e8f9f7 358 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 363 hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Select the start slave bank */
<> 144:ef7eb2e8f9f7 366 hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
<> 144:ef7eb2e8f9f7 367 hcan->Instance->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Filter Deactivation */
<> 144:ef7eb2e8f9f7 370 hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Filter Scale */
<> 144:ef7eb2e8f9f7 373 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 /* 16-bit scale for the filter */
<> 144:ef7eb2e8f9f7 376 hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* First 16-bit identifier and First 16-bit mask */
<> 144:ef7eb2e8f9f7 379 /* Or First 16-bit identifier and Second 16-bit identifier */
<> 144:ef7eb2e8f9f7 380 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 381 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
<> 144:ef7eb2e8f9f7 382 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Second 16-bit identifier and Second 16-bit mask */
<> 144:ef7eb2e8f9f7 385 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
<> 144:ef7eb2e8f9f7 386 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 387 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
<> 144:ef7eb2e8f9f7 388 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 /* 32-bit scale for the filter */
<> 144:ef7eb2e8f9f7 394 hcan->Instance->FS1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 395 /* 32-bit identifier or First 32-bit identifier */
<> 144:ef7eb2e8f9f7 396 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 397 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
<> 144:ef7eb2e8f9f7 398 (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 399 /* 32-bit mask or Second 32-bit identifier */
<> 144:ef7eb2e8f9f7 400 hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 401 ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
<> 144:ef7eb2e8f9f7 402 (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Filter Mode */
<> 144:ef7eb2e8f9f7 406 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 /*Id/Mask mode for the filter*/
<> 144:ef7eb2e8f9f7 409 hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 /*Identifier list mode for the filter*/
<> 144:ef7eb2e8f9f7 414 hcan->Instance->FM1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Filter FIFO assignment */
<> 144:ef7eb2e8f9f7 418 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 /* FIFO 0 assignation for the filter */
<> 144:ef7eb2e8f9f7 421 hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 /* FIFO 1 assignation for the filter */
<> 144:ef7eb2e8f9f7 427 hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Filter activation */
<> 144:ef7eb2e8f9f7 431 if (sFilterConfig->FilterActivation == ENABLE)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 hcan->Instance->FA1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Leave the initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 437 hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT);
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Return function status */
<> 144:ef7eb2e8f9f7 440 return HAL_OK;
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /**
<> 144:ef7eb2e8f9f7 444 * @brief Deinitializes the CANx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 445 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 446 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 447 * @retval HAL status
<> 144:ef7eb2e8f9f7 448 */
<> 144:ef7eb2e8f9f7 449 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 452 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 455 }
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Check the parameters */
<> 144:ef7eb2e8f9f7 458 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Change CAN state */
<> 144:ef7eb2e8f9f7 461 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 464 HAL_CAN_MspDeInit(hcan);
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Change CAN state */
<> 144:ef7eb2e8f9f7 467 hcan->State = HAL_CAN_STATE_RESET;
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Release Lock */
<> 144:ef7eb2e8f9f7 470 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Return function status */
<> 144:ef7eb2e8f9f7 473 return HAL_OK;
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @brief Initializes the CAN MSP.
<> 144:ef7eb2e8f9f7 478 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 479 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 480 * @retval None
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 485 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 488 the HAL_CAN_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @brief DeInitializes the CAN MSP.
<> 144:ef7eb2e8f9f7 494 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 495 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 496 * @retval None
<> 144:ef7eb2e8f9f7 497 */
<> 144:ef7eb2e8f9f7 498 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 499 {
<> 144:ef7eb2e8f9f7 500 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 501 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 504 the HAL_CAN_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @}
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 513 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 514 *
<> 144:ef7eb2e8f9f7 515 @verbatim
<> 144:ef7eb2e8f9f7 516 ==============================================================================
<> 144:ef7eb2e8f9f7 517 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 518 ==============================================================================
<> 144:ef7eb2e8f9f7 519 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 520 (+) Transmit a CAN frame message.
<> 144:ef7eb2e8f9f7 521 (+) Receive a CAN frame message.
<> 144:ef7eb2e8f9f7 522 (+) Enter CAN peripheral in sleep mode.
<> 144:ef7eb2e8f9f7 523 (+) Wake up the CAN peripheral from sleep mode.
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 @endverbatim
<> 144:ef7eb2e8f9f7 526 * @{
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /**
<> 144:ef7eb2e8f9f7 530 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 531 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 532 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 533 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 534 * @retval HAL status
<> 144:ef7eb2e8f9f7 535 */
<> 144:ef7eb2e8f9f7 536 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 537 {
<> 144:ef7eb2e8f9f7 538 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 144:ef7eb2e8f9f7 539 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Check the parameters */
<> 144:ef7eb2e8f9f7 542 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 543 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 544 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 547 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 548 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 /* Process locked */
<> 144:ef7eb2e8f9f7 551 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* Change CAN state */
<> 144:ef7eb2e8f9f7 556 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558 else
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Change CAN state */
<> 144:ef7eb2e8f9f7 561 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 565 if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 transmitmailbox = 0;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569 else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 transmitmailbox = 1;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 else
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 transmitmailbox = 2;
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* Set up the Id */
<> 144:ef7eb2e8f9f7 579 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 580 if (hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 583 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
<> 144:ef7eb2e8f9f7 584 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 else
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 589 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
<> 144:ef7eb2e8f9f7 590 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 591 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 595 hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
<> 144:ef7eb2e8f9f7 596 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 597 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Set up the data field */
<> 144:ef7eb2e8f9f7 600 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
<> 144:ef7eb2e8f9f7 601 ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
<> 144:ef7eb2e8f9f7 602 ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
<> 144:ef7eb2e8f9f7 603 ((uint32_t)hcan->pTxMsg->Data[0]));
<> 144:ef7eb2e8f9f7 604 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
<> 144:ef7eb2e8f9f7 605 ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
<> 144:ef7eb2e8f9f7 606 ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
<> 144:ef7eb2e8f9f7 607 ((uint32_t)hcan->pTxMsg->Data[4]));
<> 144:ef7eb2e8f9f7 608 /* Request transmission */
<> 144:ef7eb2e8f9f7 609 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Get tick */
<> 144:ef7eb2e8f9f7 612 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 615 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
<> 144:ef7eb2e8f9f7 616 {
<> 144:ef7eb2e8f9f7 617 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 618 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 623 /* Process unlocked */
<> 144:ef7eb2e8f9f7 624 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 625 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 /* Change CAN state */
<> 144:ef7eb2e8f9f7 632 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634 else
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 /* Change CAN state */
<> 144:ef7eb2e8f9f7 637 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Process unlocked */
<> 144:ef7eb2e8f9f7 641 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Return function status */
<> 144:ef7eb2e8f9f7 644 return HAL_OK;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646 else
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 /* Change CAN state */
<> 144:ef7eb2e8f9f7 649 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* Return function status */
<> 144:ef7eb2e8f9f7 652 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /**
<> 144:ef7eb2e8f9f7 657 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 658 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 659 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 660 * @retval HAL status
<> 144:ef7eb2e8f9f7 661 */
<> 144:ef7eb2e8f9f7 662 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /* Check the parameters */
<> 144:ef7eb2e8f9f7 667 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 668 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 669 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 672 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 673 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 /* Process Locked */
<> 144:ef7eb2e8f9f7 676 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 679 if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 transmitmailbox = 0;
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683 else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 transmitmailbox = 1;
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687 else
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 transmitmailbox = 2;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Set up the Id */
<> 144:ef7eb2e8f9f7 693 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 694 if(hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 697 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
<> 144:ef7eb2e8f9f7 698 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700 else
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 703 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
<> 144:ef7eb2e8f9f7 704 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 705 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 709 hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
<> 144:ef7eb2e8f9f7 710 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 711 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Set up the data field */
<> 144:ef7eb2e8f9f7 714 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
<> 144:ef7eb2e8f9f7 715 ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
<> 144:ef7eb2e8f9f7 716 ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
<> 144:ef7eb2e8f9f7 717 ((uint32_t)hcan->pTxMsg->Data[0]));
<> 144:ef7eb2e8f9f7 718 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
<> 144:ef7eb2e8f9f7 719 ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
<> 144:ef7eb2e8f9f7 720 ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
<> 144:ef7eb2e8f9f7 721 ((uint32_t)hcan->pTxMsg->Data[4]));
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 /* Change CAN state */
<> 144:ef7eb2e8f9f7 726 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 else
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 /* Change CAN state */
<> 144:ef7eb2e8f9f7 731 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 735 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 738 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Enable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 741 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Enable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 744 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Enable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 747 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Enable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 750 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Enable Error Interrupt */
<> 144:ef7eb2e8f9f7 753 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Enable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 756 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Request transmission */
<> 144:ef7eb2e8f9f7 759 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 else
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 /* Change CAN state */
<> 144:ef7eb2e8f9f7 764 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Return function status */
<> 144:ef7eb2e8f9f7 767 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 return HAL_OK;
<> 144:ef7eb2e8f9f7 771 }
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /**
<> 144:ef7eb2e8f9f7 774 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 775 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 776 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 777 * @param FIFONumber: FIFO number.
<> 144:ef7eb2e8f9f7 778 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 779 * @retval HAL status
<> 144:ef7eb2e8f9f7 780 * @retval None
<> 144:ef7eb2e8f9f7 781 */
<> 144:ef7eb2e8f9f7 782 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 783 {
<> 144:ef7eb2e8f9f7 784 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Check the parameters */
<> 144:ef7eb2e8f9f7 787 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Process locked */
<> 144:ef7eb2e8f9f7 790 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 /* Change CAN state */
<> 144:ef7eb2e8f9f7 795 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797 else
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 /* Change CAN state */
<> 144:ef7eb2e8f9f7 800 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 801 }
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* Get tick */
<> 144:ef7eb2e8f9f7 804 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Check pending message */
<> 144:ef7eb2e8f9f7 807 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 810 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 815 /* Process unlocked */
<> 144:ef7eb2e8f9f7 816 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 817 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /* Get the Id */
<> 144:ef7eb2e8f9f7 823 hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 824 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828 else
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 834 /* Get the DLC */
<> 144:ef7eb2e8f9f7 835 hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 836 /* Get the FMI */
<> 144:ef7eb2e8f9f7 837 hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
<> 144:ef7eb2e8f9f7 838 /* Get the data field */
<> 144:ef7eb2e8f9f7 839 hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 840 hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
<> 144:ef7eb2e8f9f7 841 hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
<> 144:ef7eb2e8f9f7 842 hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
<> 144:ef7eb2e8f9f7 843 hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 844 hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
<> 144:ef7eb2e8f9f7 845 hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
<> 144:ef7eb2e8f9f7 846 hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 849 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 852 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 855 {
<> 144:ef7eb2e8f9f7 856 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 857 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 /* Change CAN state */
<> 144:ef7eb2e8f9f7 863 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865 else
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 /* Change CAN state */
<> 144:ef7eb2e8f9f7 868 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* Process unlocked */
<> 144:ef7eb2e8f9f7 872 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Return function status */
<> 144:ef7eb2e8f9f7 875 return HAL_OK;
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 880 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 881 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 882 * @param FIFONumber: FIFO number.
<> 144:ef7eb2e8f9f7 883 * @retval HAL status
<> 144:ef7eb2e8f9f7 884 * @retval None
<> 144:ef7eb2e8f9f7 885 */
<> 144:ef7eb2e8f9f7 886 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 /* Check the parameters */
<> 144:ef7eb2e8f9f7 889 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
<> 144:ef7eb2e8f9f7 892 {
<> 144:ef7eb2e8f9f7 893 /* Process locked */
<> 144:ef7eb2e8f9f7 894 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 /* Change CAN state */
<> 144:ef7eb2e8f9f7 899 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 900 }
<> 144:ef7eb2e8f9f7 901 else
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 /* Change CAN state */
<> 144:ef7eb2e8f9f7 904 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 905 }
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 908 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Enable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 911 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* Enable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 914 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /* Enable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 917 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Enable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 920 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Enable Error Interrupt */
<> 144:ef7eb2e8f9f7 923 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Process unlocked */
<> 144:ef7eb2e8f9f7 926 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 /* Enable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 931 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 else
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 /* Enable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 936 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 937 }
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 }
<> 144:ef7eb2e8f9f7 940 else
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* Return function status */
<> 144:ef7eb2e8f9f7 946 return HAL_OK;
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /**
<> 144:ef7eb2e8f9f7 950 * @brief Enters the Sleep (low power) mode.
<> 144:ef7eb2e8f9f7 951 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 952 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 953 * @retval HAL status.
<> 144:ef7eb2e8f9f7 954 */
<> 144:ef7eb2e8f9f7 955 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 956 {
<> 144:ef7eb2e8f9f7 957 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Process locked */
<> 144:ef7eb2e8f9f7 960 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 /* Change CAN state */
<> 144:ef7eb2e8f9f7 963 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /* Request Sleep mode */
<> 144:ef7eb2e8f9f7 966 hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 969 if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 /* Process unlocked */
<> 144:ef7eb2e8f9f7 972 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /* Return function status */
<> 144:ef7eb2e8f9f7 975 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 976 }
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 /* Get tick */
<> 144:ef7eb2e8f9f7 979 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 982 while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 987 /* Process unlocked */
<> 144:ef7eb2e8f9f7 988 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 989 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /* Change CAN state */
<> 144:ef7eb2e8f9f7 994 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Process unlocked */
<> 144:ef7eb2e8f9f7 997 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /* Return function status */
<> 144:ef7eb2e8f9f7 1000 return HAL_OK;
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /**
<> 144:ef7eb2e8f9f7 1004 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
<> 144:ef7eb2e8f9f7 1005 * is in the normal mode.
<> 144:ef7eb2e8f9f7 1006 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1007 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1008 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 /* Process locked */
<> 144:ef7eb2e8f9f7 1015 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1018 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Wake up request */
<> 144:ef7eb2e8f9f7 1021 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Get tick */
<> 144:ef7eb2e8f9f7 1024 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 1027 while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1028 {
<> 144:ef7eb2e8f9f7 1029 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1030 {
<> 144:ef7eb2e8f9f7 1031 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1032 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1033 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1034 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1040 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 /* Return function status */
<> 144:ef7eb2e8f9f7 1043 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1047 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1050 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Return function status */
<> 144:ef7eb2e8f9f7 1053 return HAL_OK;
<> 144:ef7eb2e8f9f7 1054 }
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /**
<> 144:ef7eb2e8f9f7 1057 * @brief Handles CAN interrupt request
<> 144:ef7eb2e8f9f7 1058 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1059 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1060 * @retval None
<> 144:ef7eb2e8f9f7 1061 */
<> 144:ef7eb2e8f9f7 1062 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1063 {
<> 144:ef7eb2e8f9f7 1064 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 1065 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
<> 144:ef7eb2e8f9f7 1068 (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
<> 144:ef7eb2e8f9f7 1069 (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 /* Call transmit function */
<> 144:ef7eb2e8f9f7 1072 CAN_Transmit_IT(hcan);
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /* Check End of reception flag for FIFO0 */
<> 144:ef7eb2e8f9f7 1077 if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
<> 144:ef7eb2e8f9f7 1078 (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
<> 144:ef7eb2e8f9f7 1079 {
<> 144:ef7eb2e8f9f7 1080 /* Call receive function */
<> 144:ef7eb2e8f9f7 1081 CAN_Receive_IT(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /* Check End of reception flag for FIFO1 */
<> 144:ef7eb2e8f9f7 1085 if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
<> 144:ef7eb2e8f9f7 1086 (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 /* Call receive function */
<> 144:ef7eb2e8f9f7 1089 CAN_Receive_IT(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Check Error Warning Flag */
<> 144:ef7eb2e8f9f7 1093 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
<> 144:ef7eb2e8f9f7 1094 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
<> 144:ef7eb2e8f9f7 1095 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1096 {
<> 144:ef7eb2e8f9f7 1097 /* Set CAN error code to EWG error */
<> 144:ef7eb2e8f9f7 1098 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
<> 144:ef7eb2e8f9f7 1099 /* No need for clear of Error Warning Flag as read-only */
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /* Check Error Passive Flag */
<> 144:ef7eb2e8f9f7 1103 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
<> 144:ef7eb2e8f9f7 1104 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
<> 144:ef7eb2e8f9f7 1105 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1106 {
<> 144:ef7eb2e8f9f7 1107 /* Set CAN error code to EPV error */
<> 144:ef7eb2e8f9f7 1108 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
<> 144:ef7eb2e8f9f7 1109 /* No need for clear of Error Passive Flag as read-only */
<> 144:ef7eb2e8f9f7 1110 }
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /* Check Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1113 if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
<> 144:ef7eb2e8f9f7 1114 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
<> 144:ef7eb2e8f9f7 1115 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1116 {
<> 144:ef7eb2e8f9f7 1117 /* Set CAN error code to BOF error */
<> 144:ef7eb2e8f9f7 1118 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
<> 144:ef7eb2e8f9f7 1119 /* No need for clear of Bus-Off Flag as read-only */
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /* Check Last error code Flag */
<> 144:ef7eb2e8f9f7 1123 if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
<> 144:ef7eb2e8f9f7 1124 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
<> 144:ef7eb2e8f9f7 1125 (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 switch(hcan->Instance->ESR & CAN_ESR_LEC)
<> 144:ef7eb2e8f9f7 1128 {
<> 144:ef7eb2e8f9f7 1129 case(CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1130 /* Set CAN error code to STF error */
<> 144:ef7eb2e8f9f7 1131 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
<> 144:ef7eb2e8f9f7 1132 break;
<> 144:ef7eb2e8f9f7 1133 case(CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1134 /* Set CAN error code to FOR error */
<> 144:ef7eb2e8f9f7 1135 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
<> 144:ef7eb2e8f9f7 1136 break;
<> 144:ef7eb2e8f9f7 1137 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1138 /* Set CAN error code to ACK error */
<> 144:ef7eb2e8f9f7 1139 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
<> 144:ef7eb2e8f9f7 1140 break;
<> 144:ef7eb2e8f9f7 1141 case(CAN_ESR_LEC_2):
<> 144:ef7eb2e8f9f7 1142 /* Set CAN error code to BR error */
<> 144:ef7eb2e8f9f7 1143 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
<> 144:ef7eb2e8f9f7 1144 break;
<> 144:ef7eb2e8f9f7 1145 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1146 /* Set CAN error code to BD error */
<> 144:ef7eb2e8f9f7 1147 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
<> 144:ef7eb2e8f9f7 1148 break;
<> 144:ef7eb2e8f9f7 1149 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1150 /* Set CAN error code to CRC error */
<> 144:ef7eb2e8f9f7 1151 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
<> 144:ef7eb2e8f9f7 1152 break;
<> 144:ef7eb2e8f9f7 1153 default:
<> 144:ef7eb2e8f9f7 1154 break;
<> 144:ef7eb2e8f9f7 1155 }
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Clear Last error code Flag */
<> 144:ef7eb2e8f9f7 1158 hcan->Instance->ESR &= ~(CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1162 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1163 {
<> 144:ef7eb2e8f9f7 1164 /* Clear ERRI Flag */
<> 144:ef7eb2e8f9f7 1165 hcan->Instance->MSR |= CAN_MSR_ERRI;
<> 144:ef7eb2e8f9f7 1166 /* Set the CAN state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1167 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1168 /* Call Error callback function */
<> 144:ef7eb2e8f9f7 1169 HAL_CAN_ErrorCallback(hcan);
<> 144:ef7eb2e8f9f7 1170 }
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /**
<> 144:ef7eb2e8f9f7 1174 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1175 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1176 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1177 * @retval None
<> 144:ef7eb2e8f9f7 1178 */
<> 144:ef7eb2e8f9f7 1179 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1182 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1185 the HAL_CAN_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1186 */
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /**
<> 144:ef7eb2e8f9f7 1190 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1191 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1192 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1193 * @retval None
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1196 {
<> 144:ef7eb2e8f9f7 1197 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1198 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1201 the HAL_CAN_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1202 */
<> 144:ef7eb2e8f9f7 1203 }
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /**
<> 144:ef7eb2e8f9f7 1206 * @brief Error CAN callback.
<> 144:ef7eb2e8f9f7 1207 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1208 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1209 * @retval None
<> 144:ef7eb2e8f9f7 1210 */
<> 144:ef7eb2e8f9f7 1211 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1212 {
<> 144:ef7eb2e8f9f7 1213 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1214 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1217 the HAL_CAN_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1218 */
<> 144:ef7eb2e8f9f7 1219 }
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /**
<> 144:ef7eb2e8f9f7 1222 * @}
<> 144:ef7eb2e8f9f7 1223 */
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1226 * @brief CAN Peripheral State functions
<> 144:ef7eb2e8f9f7 1227 *
<> 144:ef7eb2e8f9f7 1228 @verbatim
<> 144:ef7eb2e8f9f7 1229 ==============================================================================
<> 144:ef7eb2e8f9f7 1230 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1231 ==============================================================================
<> 144:ef7eb2e8f9f7 1232 [..]
<> 144:ef7eb2e8f9f7 1233 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1234 (+) Check the CAN state.
<> 144:ef7eb2e8f9f7 1235 (+) Check CAN Errors detected during interrupt process
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 @endverbatim
<> 144:ef7eb2e8f9f7 1238 * @{
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /**
<> 144:ef7eb2e8f9f7 1242 * @brief return the CAN state
<> 144:ef7eb2e8f9f7 1243 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1244 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1245 * @retval HAL state
<> 144:ef7eb2e8f9f7 1246 */
<> 144:ef7eb2e8f9f7 1247 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Return CAN state */
<> 144:ef7eb2e8f9f7 1250 return hcan->State;
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /**
<> 144:ef7eb2e8f9f7 1254 * @brief Return the CAN error code
<> 144:ef7eb2e8f9f7 1255 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1256 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1257 * @retval CAN Error Code
<> 144:ef7eb2e8f9f7 1258 */
<> 144:ef7eb2e8f9f7 1259 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1260 {
<> 144:ef7eb2e8f9f7 1261 return hcan->ErrorCode;
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 /**
<> 144:ef7eb2e8f9f7 1265 * @}
<> 144:ef7eb2e8f9f7 1266 */
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /**
<> 144:ef7eb2e8f9f7 1269 * @}
<> 144:ef7eb2e8f9f7 1270 */
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /** @addtogroup CAN_Private_Functions CAN Private Functions
<> 144:ef7eb2e8f9f7 1273 * @brief CAN Frame message Rx/Tx functions
<> 144:ef7eb2e8f9f7 1274 *
<> 144:ef7eb2e8f9f7 1275 * @{
<> 144:ef7eb2e8f9f7 1276 */
<> 144:ef7eb2e8f9f7 1277 /**
<> 144:ef7eb2e8f9f7 1278 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 1279 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1280 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1281 * @retval HAL status
<> 144:ef7eb2e8f9f7 1282 */
<> 144:ef7eb2e8f9f7 1283 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1284 {
<> 144:ef7eb2e8f9f7 1285 /* Disable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 1286 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1289 {
<> 144:ef7eb2e8f9f7 1290 /* Disable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 1291 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 /* Disable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 1294 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /* Disable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 1297 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /* Disable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 1300 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /* Disable Error Interrupt */
<> 144:ef7eb2e8f9f7 1303 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1304 }
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1307 {
<> 144:ef7eb2e8f9f7 1308 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1309 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1310 }
<> 144:ef7eb2e8f9f7 1311 else
<> 144:ef7eb2e8f9f7 1312 {
<> 144:ef7eb2e8f9f7 1313 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1314 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1315 }
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317 /* Transmission complete callback */
<> 144:ef7eb2e8f9f7 1318 HAL_CAN_TxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 return HAL_OK;
<> 144:ef7eb2e8f9f7 1321 }
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 /**
<> 144:ef7eb2e8f9f7 1324 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 1325 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1326 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1327 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 1328 * @retval HAL status
<> 144:ef7eb2e8f9f7 1329 * @retval None
<> 144:ef7eb2e8f9f7 1330 */
<> 144:ef7eb2e8f9f7 1331 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1332 {
<> 144:ef7eb2e8f9f7 1333 /* Get the Id */
<> 144:ef7eb2e8f9f7 1334 hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1335 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 1336 {
<> 144:ef7eb2e8f9f7 1337 hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
<> 144:ef7eb2e8f9f7 1338 }
<> 144:ef7eb2e8f9f7 1339 else
<> 144:ef7eb2e8f9f7 1340 {
<> 144:ef7eb2e8f9f7 1341 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
<> 144:ef7eb2e8f9f7 1342 }
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1345 /* Get the DLC */
<> 144:ef7eb2e8f9f7 1346 hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 1347 /* Get the FMI */
<> 144:ef7eb2e8f9f7 1348 hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
<> 144:ef7eb2e8f9f7 1349 /* Get the data field */
<> 144:ef7eb2e8f9f7 1350 hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 1351 hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
<> 144:ef7eb2e8f9f7 1352 hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
<> 144:ef7eb2e8f9f7 1353 hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
<> 144:ef7eb2e8f9f7 1354 hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 1355 hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
<> 144:ef7eb2e8f9f7 1356 hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
<> 144:ef7eb2e8f9f7 1357 hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
<> 144:ef7eb2e8f9f7 1358 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 1359 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 1360 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1361 {
<> 144:ef7eb2e8f9f7 1362 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /* Disable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1365 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 1368 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1369 {
<> 144:ef7eb2e8f9f7 1370 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Disable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1373 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1374 }
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1377 {
<> 144:ef7eb2e8f9f7 1378 /* Disable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 1379 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 /* Disable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 1382 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Disable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 1385 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Disable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 1388 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Disable Error Interrupt */
<> 144:ef7eb2e8f9f7 1391 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1392 }
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1395 {
<> 144:ef7eb2e8f9f7 1396 /* Disable CAN state */
<> 144:ef7eb2e8f9f7 1397 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399 else
<> 144:ef7eb2e8f9f7 1400 {
<> 144:ef7eb2e8f9f7 1401 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1402 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1403 }
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 /* Receive complete callback */
<> 144:ef7eb2e8f9f7 1406 HAL_CAN_RxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Return function status */
<> 144:ef7eb2e8f9f7 1409 return HAL_OK;
<> 144:ef7eb2e8f9f7 1410 }
<> 144:ef7eb2e8f9f7 1411 /**
<> 144:ef7eb2e8f9f7 1412 * @}
<> 144:ef7eb2e8f9f7 1413 */
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /**
<> 144:ef7eb2e8f9f7 1416 * @}
<> 144:ef7eb2e8f9f7 1417 */
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 /**
<> 144:ef7eb2e8f9f7 1420 * @}
<> 144:ef7eb2e8f9f7 1421 */
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 #endif /* defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 #endif /* HAL_CAN_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/