mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h@144:ef7eb2e8f9f7
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.4.0
<> 144:ef7eb2e8f9f7 6 * @date 27-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 8 * module driver.
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @attention
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 15 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 16 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 20 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 22 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 23 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 *
<> 144:ef7eb2e8f9f7 36 ******************************************************************************
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 40 #ifndef __STM32F0xx_HAL_H
<> 144:ef7eb2e8f9f7 41 #define __STM32F0xx_HAL_H
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f0xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup HAL
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @addtogroup HAL_Private_Macros
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
<> 144:ef7eb2e8f9f7 63 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
<> 144:ef7eb2e8f9f7 64 defined(STM32F070xB) || defined(STM32F030x6)
<> 144:ef7eb2e8f9f7 65 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
<> 144:ef7eb2e8f9f7 66 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
<> 144:ef7eb2e8f9f7 67 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
<> 144:ef7eb2e8f9f7 68 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
<> 144:ef7eb2e8f9f7 69 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
<> 144:ef7eb2e8f9f7 70 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
<> 144:ef7eb2e8f9f7 71 #else
<> 144:ef7eb2e8f9f7 72 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
<> 144:ef7eb2e8f9f7 73 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
<> 144:ef7eb2e8f9f7 74 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
<> 144:ef7eb2e8f9f7 75 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
<> 144:ef7eb2e8f9f7 76 #endif
<> 144:ef7eb2e8f9f7 77 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<> 144:ef7eb2e8f9f7 78 #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
<> 144:ef7eb2e8f9f7 79 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<> 144:ef7eb2e8f9f7 80 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 81 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
<> 144:ef7eb2e8f9f7 82 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
<> 144:ef7eb2e8f9f7 83 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
<> 144:ef7eb2e8f9f7 84 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 85 /**
<> 144:ef7eb2e8f9f7 86 * @}
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 90 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 91 /** @defgroup HAL_Exported_Constants HAL Exported Constants
<> 144:ef7eb2e8f9f7 92 * @{
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<> 144:ef7eb2e8f9f7 96 /** @defgroup HAL_Pin_remapping HAL Pin remapping
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
<> 144:ef7eb2e8f9f7 100 0: No remap (pin pair PA9/10 mapped on the pins)
<> 144:ef7eb2e8f9f7 101 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @}
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #if defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 109 /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
<> 144:ef7eb2e8f9f7 110 * @note Applicable on STM32F09x
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
<> 144:ef7eb2e8f9f7 114 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
<> 144:ef7eb2e8f9f7 115 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /**
<> 144:ef7eb2e8f9f7 118 * @}
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** @brief Fast-mode Plus driving capability on a specific GPIO
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
<> 144:ef7eb2e8f9f7 130 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
<> 144:ef7eb2e8f9f7 131 defined(STM32F070xB) || defined(STM32F030x6)
<> 144:ef7eb2e8f9f7 132 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
<> 144:ef7eb2e8f9f7 133 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
<> 144:ef7eb2e8f9f7 134 #endif
<> 144:ef7eb2e8f9f7 135 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
<> 144:ef7eb2e8f9f7 136 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
<> 144:ef7eb2e8f9f7 137 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
<> 144:ef7eb2e8f9f7 138 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 #if defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 146 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
<> 144:ef7eb2e8f9f7 147 * @brief ISR Wrapper
<> 144:ef7eb2e8f9f7 148 * @note applicable on STM32F09x
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 #define HAL_SYSCFG_ITLINE0 ((uint32_t) 0x00000000) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 152 #define HAL_SYSCFG_ITLINE1 ((uint32_t) 0x00000001) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 153 #define HAL_SYSCFG_ITLINE2 ((uint32_t) 0x00000002) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 154 #define HAL_SYSCFG_ITLINE3 ((uint32_t) 0x00000003) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 155 #define HAL_SYSCFG_ITLINE4 ((uint32_t) 0x00000004) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 156 #define HAL_SYSCFG_ITLINE5 ((uint32_t) 0x00000005) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 157 #define HAL_SYSCFG_ITLINE6 ((uint32_t) 0x00000006) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 158 #define HAL_SYSCFG_ITLINE7 ((uint32_t) 0x00000007) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 159 #define HAL_SYSCFG_ITLINE8 ((uint32_t) 0x00000008) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 160 #define HAL_SYSCFG_ITLINE9 ((uint32_t) 0x00000009) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 161 #define HAL_SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 162 #define HAL_SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 163 #define HAL_SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 164 #define HAL_SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 165 #define HAL_SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 166 #define HAL_SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 167 #define HAL_SYSCFG_ITLINE16 ((uint32_t) 0x00000010) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 168 #define HAL_SYSCFG_ITLINE17 ((uint32_t) 0x00000011) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 169 #define HAL_SYSCFG_ITLINE18 ((uint32_t) 0x00000012) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 170 #define HAL_SYSCFG_ITLINE19 ((uint32_t) 0x00000013) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 171 #define HAL_SYSCFG_ITLINE20 ((uint32_t) 0x00000014) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 172 #define HAL_SYSCFG_ITLINE21 ((uint32_t) 0x00000015) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 173 #define HAL_SYSCFG_ITLINE22 ((uint32_t) 0x00000016) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 174 #define HAL_SYSCFG_ITLINE23 ((uint32_t) 0x00000017) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 175 #define HAL_SYSCFG_ITLINE24 ((uint32_t) 0x00000018) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 176 #define HAL_SYSCFG_ITLINE25 ((uint32_t) 0x00000019) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 177 #define HAL_SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 178 #define HAL_SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 179 #define HAL_SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 180 #define HAL_SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 181 #define HAL_SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 182 #define HAL_SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) /*!< Internal define for macro handling */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
<> 144:ef7eb2e8f9f7 185 #if defined(STM32F091xC)
<> 144:ef7eb2e8f9f7 186 #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
<> 144:ef7eb2e8f9f7 187 #endif
<> 144:ef7eb2e8f9f7 188 #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
<> 144:ef7eb2e8f9f7 189 #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
<> 144:ef7eb2e8f9f7 190 #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
<> 144:ef7eb2e8f9f7 191 #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
<> 144:ef7eb2e8f9f7 192 #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
<> 144:ef7eb2e8f9f7 193 #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
<> 144:ef7eb2e8f9f7 194 #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
<> 144:ef7eb2e8f9f7 195 #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
<> 144:ef7eb2e8f9f7 196 #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
<> 144:ef7eb2e8f9f7 197 #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
<> 144:ef7eb2e8f9f7 198 #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
<> 144:ef7eb2e8f9f7 199 #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
<> 144:ef7eb2e8f9f7 200 #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
<> 144:ef7eb2e8f9f7 201 #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
<> 144:ef7eb2e8f9f7 202 #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
<> 144:ef7eb2e8f9f7 203 #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
<> 144:ef7eb2e8f9f7 204 #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
<> 144:ef7eb2e8f9f7 205 #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
<> 144:ef7eb2e8f9f7 206 #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
<> 144:ef7eb2e8f9f7 207 #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
<> 144:ef7eb2e8f9f7 208 #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
<> 144:ef7eb2e8f9f7 209 #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
<> 144:ef7eb2e8f9f7 210 #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
<> 144:ef7eb2e8f9f7 211 #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
<> 144:ef7eb2e8f9f7 212 #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
<> 144:ef7eb2e8f9f7 213 #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
<> 144:ef7eb2e8f9f7 214 #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
<> 144:ef7eb2e8f9f7 215 #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
<> 144:ef7eb2e8f9f7 216 #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
<> 144:ef7eb2e8f9f7 217 #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
<> 144:ef7eb2e8f9f7 218 #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
<> 144:ef7eb2e8f9f7 219 #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
<> 144:ef7eb2e8f9f7 220 #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
<> 144:ef7eb2e8f9f7 221 #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
<> 144:ef7eb2e8f9f7 222 #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
<> 144:ef7eb2e8f9f7 223 #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
<> 144:ef7eb2e8f9f7 224 #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
<> 144:ef7eb2e8f9f7 225 #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
<> 144:ef7eb2e8f9f7 226 #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
<> 144:ef7eb2e8f9f7 227 #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
<> 144:ef7eb2e8f9f7 228 #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
<> 144:ef7eb2e8f9f7 229 #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
<> 144:ef7eb2e8f9f7 230 #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
<> 144:ef7eb2e8f9f7 231 #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
<> 144:ef7eb2e8f9f7 232 #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
<> 144:ef7eb2e8f9f7 233 #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
<> 144:ef7eb2e8f9f7 234 #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
<> 144:ef7eb2e8f9f7 235 #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
<> 144:ef7eb2e8f9f7 236 #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
<> 144:ef7eb2e8f9f7 237 #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
<> 144:ef7eb2e8f9f7 238 #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
<> 144:ef7eb2e8f9f7 239 #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
<> 144:ef7eb2e8f9f7 240 #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
<> 144:ef7eb2e8f9f7 241 #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
<> 144:ef7eb2e8f9f7 242 #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
<> 144:ef7eb2e8f9f7 243 #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
<> 144:ef7eb2e8f9f7 244 #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
<> 144:ef7eb2e8f9f7 245 #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
<> 144:ef7eb2e8f9f7 246 #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
<> 144:ef7eb2e8f9f7 247 #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
<> 144:ef7eb2e8f9f7 248 #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
<> 144:ef7eb2e8f9f7 249 #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
<> 144:ef7eb2e8f9f7 250 #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
<> 144:ef7eb2e8f9f7 251 #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
<> 144:ef7eb2e8f9f7 252 #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
<> 144:ef7eb2e8f9f7 253 #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
<> 144:ef7eb2e8f9f7 254 #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
<> 144:ef7eb2e8f9f7 255 #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 #endif /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @}
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 266 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 267 * @{
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
<> 144:ef7eb2e8f9f7 271 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 272 * @{
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
<> 144:ef7eb2e8f9f7 276 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
<> 144:ef7eb2e8f9f7 277 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
<> 144:ef7eb2e8f9f7 278 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
<> 144:ef7eb2e8f9f7 281 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
<> 144:ef7eb2e8f9f7 282 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
<> 144:ef7eb2e8f9f7 283 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 286 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 287 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 288 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 291 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
<> 144:ef7eb2e8f9f7 292 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
<> 144:ef7eb2e8f9f7 293 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 296 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
<> 144:ef7eb2e8f9f7 297 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
<> 144:ef7eb2e8f9f7 298 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 301 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
<> 144:ef7eb2e8f9f7 302 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
<> 144:ef7eb2e8f9f7 303 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 306 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
<> 144:ef7eb2e8f9f7 307 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
<> 144:ef7eb2e8f9f7 308 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 311 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
<> 144:ef7eb2e8f9f7 312 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
<> 144:ef7eb2e8f9f7 313 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 316 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
<> 144:ef7eb2e8f9f7 317 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
<> 144:ef7eb2e8f9f7 318 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 321 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
<> 144:ef7eb2e8f9f7 322 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
<> 144:ef7eb2e8f9f7 323 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 326 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
<> 144:ef7eb2e8f9f7 327 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
<> 144:ef7eb2e8f9f7 328 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 331 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
<> 144:ef7eb2e8f9f7 332 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
<> 144:ef7eb2e8f9f7 333 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 336 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
<> 144:ef7eb2e8f9f7 337 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
<> 144:ef7eb2e8f9f7 338 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 341 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
<> 144:ef7eb2e8f9f7 342 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
<> 144:ef7eb2e8f9f7 343 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
<> 144:ef7eb2e8f9f7 350 * @{
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 #if defined(SYSCFG_CFGR1_MEM_MODE)
<> 144:ef7eb2e8f9f7 353 /** @brief Main Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
<> 144:ef7eb2e8f9f7 356 #endif /* SYSCFG_CFGR1_MEM_MODE */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
<> 144:ef7eb2e8f9f7 359 /** @brief System Flash memory mapped at 0x00000000
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
<> 144:ef7eb2e8f9f7 362 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
<> 144:ef7eb2e8f9f7 363 }while(0)
<> 144:ef7eb2e8f9f7 364 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
<> 144:ef7eb2e8f9f7 367 /** @brief Embedded SRAM mapped at 0x00000000
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
<> 144:ef7eb2e8f9f7 370 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
<> 144:ef7eb2e8f9f7 371 }while(0)
<> 144:ef7eb2e8f9f7 372 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @}
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
<> 144:ef7eb2e8f9f7 379 /** @defgroup HAL_Pin_remap HAL Pin remap
<> 144:ef7eb2e8f9f7 380 * @brief Pin remapping enable/disable macros
<> 144:ef7eb2e8f9f7 381 * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping
<> 144:ef7eb2e8f9f7 382 * @{
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
<> 144:ef7eb2e8f9f7 385 SYSCFG->CFGR1 |= (__PIN_REMAP__); \
<> 144:ef7eb2e8f9f7 386 }while(0)
<> 144:ef7eb2e8f9f7 387 #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
<> 144:ef7eb2e8f9f7 388 SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
<> 144:ef7eb2e8f9f7 389 }while(0)
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @}
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /** @brief Fast-mode Plus driving capability enable/disable macros
<> 144:ef7eb2e8f9f7 396 * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
<> 144:ef7eb2e8f9f7 397 * That you can find above these macros.
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
<> 144:ef7eb2e8f9f7 400 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
<> 144:ef7eb2e8f9f7 401 }while(0)
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
<> 144:ef7eb2e8f9f7 404 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
<> 144:ef7eb2e8f9f7 405 }while(0)
<> 144:ef7eb2e8f9f7 406 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
<> 144:ef7eb2e8f9f7 407 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
<> 144:ef7eb2e8f9f7 408 * @{
<> 144:ef7eb2e8f9f7 409 */
<> 144:ef7eb2e8f9f7 410 /** @brief SYSCFG Break Lockup lock
<> 144:ef7eb2e8f9f7 411 * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
<> 144:ef7eb2e8f9f7 412 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
<> 144:ef7eb2e8f9f7 415 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
<> 144:ef7eb2e8f9f7 416 }while(0)
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @}
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #if defined(SYSCFG_CFGR2_PVD_LOCK)
<> 144:ef7eb2e8f9f7 423 /** @defgroup PVD_Lock_Enable PVD Lock
<> 144:ef7eb2e8f9f7 424 * @{
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426 /** @brief SYSCFG Break PVD lock
<> 144:ef7eb2e8f9f7 427 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
<> 144:ef7eb2e8f9f7 428 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
<> 144:ef7eb2e8f9f7 431 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
<> 144:ef7eb2e8f9f7 432 }while(0)
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @}
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 #endif /* SYSCFG_CFGR2_PVD_LOCK */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
<> 144:ef7eb2e8f9f7 439 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
<> 144:ef7eb2e8f9f7 440 * @{
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 /** @brief SYSCFG Break SRAM PARITY lock
<> 144:ef7eb2e8f9f7 443 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
<> 144:ef7eb2e8f9f7 444 * @note The selected configuration is locked and can be unlocked by system reset
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
<> 144:ef7eb2e8f9f7 447 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
<> 144:ef7eb2e8f9f7 448 }while(0)
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @}
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 #if defined(SYSCFG_CFGR2_SRAM_PEF)
<> 144:ef7eb2e8f9f7 455 /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
<> 144:ef7eb2e8f9f7 456 * @brief Parity check on RAM disable macro
<> 144:ef7eb2e8f9f7 457 * @note Disabling the parity check on RAM locks the configuration bit.
<> 144:ef7eb2e8f9f7 458 * To re-enable the parity check on RAM perform a system reset.
<> 144:ef7eb2e8f9f7 459 * @{
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 #endif /* SYSCFG_CFGR2_SRAM_PEF */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 #if defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 469 /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
<> 144:ef7eb2e8f9f7 470 * @brief ISR wrapper check
<> 144:ef7eb2e8f9f7 471 * @note This feature is applicable on STM32F09x
<> 144:ef7eb2e8f9f7 472 * @note Allow to determine interrupt source per line.
<> 144:ef7eb2e8f9f7 473 * @{
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18)] & ((__SOURCE__) & 0x00FFFFFF))
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 #if defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 482 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
<> 144:ef7eb2e8f9f7 483 * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
<> 144:ef7eb2e8f9f7 484 * @note This feature is applicable on STM32F09x
<> 144:ef7eb2e8f9f7 485 * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL
<> 144:ef7eb2e8f9f7 486 * @{
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
<> 144:ef7eb2e8f9f7 489 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
<> 144:ef7eb2e8f9f7 490 SYSCFG->CFGR1 |= (__SOURCE__); \
<> 144:ef7eb2e8f9f7 491 }while(0)
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
<> 144:ef7eb2e8f9f7 494 /**
<> 144:ef7eb2e8f9f7 495 * @}
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @}
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /** @addtogroup HAL_Exported_Functions
<> 144:ef7eb2e8f9f7 506 * @{
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /** @addtogroup HAL_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 510 * @{
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 513 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 514 HAL_StatusTypeDef HAL_DeInit(void);
<> 144:ef7eb2e8f9f7 515 void HAL_MspInit(void);
<> 144:ef7eb2e8f9f7 516 void HAL_MspDeInit(void);
<> 144:ef7eb2e8f9f7 517 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @}
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /** @addtogroup HAL_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 523 * @{
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 527 void HAL_IncTick(void);
<> 144:ef7eb2e8f9f7 528 void HAL_Delay(__IO uint32_t Delay);
<> 144:ef7eb2e8f9f7 529 uint32_t HAL_GetTick(void);
<> 144:ef7eb2e8f9f7 530 void HAL_SuspendTick(void);
<> 144:ef7eb2e8f9f7 531 void HAL_ResumeTick(void);
<> 144:ef7eb2e8f9f7 532 uint32_t HAL_GetHalVersion(void);
<> 144:ef7eb2e8f9f7 533 uint32_t HAL_GetREVID(void);
<> 144:ef7eb2e8f9f7 534 uint32_t HAL_GetDEVID(void);
<> 144:ef7eb2e8f9f7 535 void HAL_DBGMCU_EnableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 536 void HAL_DBGMCU_DisableDBGStopMode(void);
<> 144:ef7eb2e8f9f7 537 void HAL_DBGMCU_EnableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 538 void HAL_DBGMCU_DisableDBGStandbyMode(void);
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @}
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /**
<> 144:ef7eb2e8f9f7 544 * @}
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @}
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /**
<> 144:ef7eb2e8f9f7 552 * @}
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 #endif
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 #endif /* __STM32F0xx_HAL_H */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/