mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC15XX/can_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_NXP/TARGET_LPC15XX/can_api.c@144:ef7eb2e8f9f7
Child:
156:95d6b41a828b
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "can_api.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 20 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #include <math.h>
<> 144:ef7eb2e8f9f7 23 #include <string.h>
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 /* Handy defines */
<> 144:ef7eb2e8f9f7 26 #define MSG_OBJ_MAX 32
<> 144:ef7eb2e8f9f7 27 #define DLC_MAX 8
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 #define ID_STD_MASK 0x07FF
<> 144:ef7eb2e8f9f7 30 #define ID_EXT_MASK 0x1FFFFFFF
<> 144:ef7eb2e8f9f7 31 #define DLC_MASK 0x0F
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #define CANIFn_ARB2_DIR (1UL << 13)
<> 144:ef7eb2e8f9f7 34 #define CANIFn_ARB2_XTD (1UL << 14)
<> 144:ef7eb2e8f9f7 35 #define CANIFn_ARB2_MSGVAL (1UL << 15)
<> 144:ef7eb2e8f9f7 36 #define CANIFn_MSK2_MXTD (1UL << 15)
<> 144:ef7eb2e8f9f7 37 #define CANIFn_MSK2_MDIR (1UL << 14)
<> 144:ef7eb2e8f9f7 38 #define CANIFn_MCTRL_EOB (1UL << 7)
<> 144:ef7eb2e8f9f7 39 #define CANIFn_MCTRL_TXRQST (1UL << 8)
<> 144:ef7eb2e8f9f7 40 #define CANIFn_MCTRL_RMTEN (1UL << 9)
<> 144:ef7eb2e8f9f7 41 #define CANIFn_MCTRL_RXIE (1UL << 10)
<> 144:ef7eb2e8f9f7 42 #define CANIFn_MCTRL_TXIE (1UL << 11)
<> 144:ef7eb2e8f9f7 43 #define CANIFn_MCTRL_UMASK (1UL << 12)
<> 144:ef7eb2e8f9f7 44 #define CANIFn_MCTRL_INTPND (1UL << 13)
<> 144:ef7eb2e8f9f7 45 #define CANIFn_MCTRL_MSGLST (1UL << 14)
<> 144:ef7eb2e8f9f7 46 #define CANIFn_MCTRL_NEWDAT (1UL << 15)
<> 144:ef7eb2e8f9f7 47 #define CANIFn_CMDMSK_DATA_B (1UL << 0)
<> 144:ef7eb2e8f9f7 48 #define CANIFn_CMDMSK_DATA_A (1UL << 1)
<> 144:ef7eb2e8f9f7 49 #define CANIFn_CMDMSK_TXRQST (1UL << 2)
<> 144:ef7eb2e8f9f7 50 #define CANIFn_CMDMSK_NEWDAT (1UL << 2)
<> 144:ef7eb2e8f9f7 51 #define CANIFn_CMDMSK_CLRINTPND (1UL << 3)
<> 144:ef7eb2e8f9f7 52 #define CANIFn_CMDMSK_CTRL (1UL << 4)
<> 144:ef7eb2e8f9f7 53 #define CANIFn_CMDMSK_ARB (1UL << 5)
<> 144:ef7eb2e8f9f7 54 #define CANIFn_CMDMSK_MASK (1UL << 6)
<> 144:ef7eb2e8f9f7 55 #define CANIFn_CMDMSK_WR (1UL << 7)
<> 144:ef7eb2e8f9f7 56 #define CANIFn_CMDMSK_RD (0UL << 7)
<> 144:ef7eb2e8f9f7 57 #define CANIFn_CMDREQ_BUSY (1UL << 15)
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 #define CANCNTL_INIT (1 << 0) // Initialization
<> 144:ef7eb2e8f9f7 60 #define CANCNTL_IE (1 << 1) // Module interrupt enable
<> 144:ef7eb2e8f9f7 61 #define CANCNTL_SIE (1 << 2) // Status change interrupt enable
<> 144:ef7eb2e8f9f7 62 #define CANCNTL_EIE (1 << 3) // Error interrupt enable
<> 144:ef7eb2e8f9f7 63 #define CANCNTL_DAR (1 << 5) // Disable automatic retransmission
<> 144:ef7eb2e8f9f7 64 #define CANCNTL_CCE (1 << 6) // Configuration change enable
<> 144:ef7eb2e8f9f7 65 #define CANCNTL_TEST (1 << 7) // Test mode enable
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 #define CANTEST_BASIC (1 << 2) // Basic mode
<> 144:ef7eb2e8f9f7 68 #define CANTEST_SILENT (1 << 3) // Silent mode
<> 144:ef7eb2e8f9f7 69 #define CANTEST_LBACK (1 << 4) // Loop back mode
<> 144:ef7eb2e8f9f7 70 #define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins
<> 144:ef7eb2e8f9f7 71 #define CANTEST_TX_SHIFT 5
<> 144:ef7eb2e8f9f7 72 #define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin.
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 static uint32_t can_irq_id = 0;
<> 144:ef7eb2e8f9f7 75 static can_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 static inline void can_disable(can_t *obj) {
<> 144:ef7eb2e8f9f7 78 LPC_C_CAN0->CANCNTL |= 0x1;
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 static inline void can_enable(can_t *obj) {
<> 144:ef7eb2e8f9f7 82 if (LPC_C_CAN0->CANCNTL & 0x1) {
<> 144:ef7eb2e8f9f7 83 LPC_C_CAN0->CANCNTL &= ~(0x1);
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85 }
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 int can_mode(can_t *obj, CanMode mode) {
<> 144:ef7eb2e8f9f7 88 int success = 0;
<> 144:ef7eb2e8f9f7 89 switch (mode) {
<> 144:ef7eb2e8f9f7 90 case MODE_RESET:
<> 144:ef7eb2e8f9f7 91 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
<> 144:ef7eb2e8f9f7 92 can_disable(obj);
<> 144:ef7eb2e8f9f7 93 success = 1;
<> 144:ef7eb2e8f9f7 94 break;
<> 144:ef7eb2e8f9f7 95 case MODE_NORMAL:
<> 144:ef7eb2e8f9f7 96 LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST;
<> 144:ef7eb2e8f9f7 97 can_enable(obj);
<> 144:ef7eb2e8f9f7 98 success = 1;
<> 144:ef7eb2e8f9f7 99 break;
<> 144:ef7eb2e8f9f7 100 case MODE_SILENT:
<> 144:ef7eb2e8f9f7 101 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
<> 144:ef7eb2e8f9f7 102 LPC_C_CAN0->CANTEST |= CANTEST_SILENT;
<> 144:ef7eb2e8f9f7 103 LPC_C_CAN0->CANTEST &=~ CANTEST_LBACK;
<> 144:ef7eb2e8f9f7 104 success = 1;
<> 144:ef7eb2e8f9f7 105 break;
<> 144:ef7eb2e8f9f7 106 case MODE_TEST_LOCAL:
<> 144:ef7eb2e8f9f7 107 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
<> 144:ef7eb2e8f9f7 108 LPC_C_CAN0->CANTEST &=~CANTEST_SILENT;
<> 144:ef7eb2e8f9f7 109 LPC_C_CAN0->CANTEST |= CANTEST_LBACK;
<> 144:ef7eb2e8f9f7 110 success = 1;
<> 144:ef7eb2e8f9f7 111 break;
<> 144:ef7eb2e8f9f7 112 case MODE_TEST_SILENT:
<> 144:ef7eb2e8f9f7 113 LPC_C_CAN0->CANCNTL |= CANCNTL_TEST;
<> 144:ef7eb2e8f9f7 114 LPC_C_CAN0->CANTEST |= (CANTEST_LBACK | CANTEST_SILENT);
<> 144:ef7eb2e8f9f7 115 success = 1;
<> 144:ef7eb2e8f9f7 116 break;
<> 144:ef7eb2e8f9f7 117 case MODE_TEST_GLOBAL:
<> 144:ef7eb2e8f9f7 118 default:
<> 144:ef7eb2e8f9f7 119 success = 0;
<> 144:ef7eb2e8f9f7 120 break;
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 return success;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
<> 144:ef7eb2e8f9f7 127 uint16_t i;
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 // Find first free message object
<> 144:ef7eb2e8f9f7 130 if (handle == 0) {
<> 144:ef7eb2e8f9f7 131 uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16);
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 // Find first free messagebox
<> 144:ef7eb2e8f9f7 134 for (i = 0; i < 32; i++) {
<> 144:ef7eb2e8f9f7 135 if ((msgval & (1 << i)) == 0) {
<> 144:ef7eb2e8f9f7 136 handle = i+1;
<> 144:ef7eb2e8f9f7 137 break;
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139 }
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if (handle > 0 && handle < 32) {
<> 144:ef7eb2e8f9f7 143 if (format == CANExtended) {
<> 144:ef7eb2e8f9f7 144 // Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything
<> 144:ef7eb2e8f9f7 145 LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF);
<> 144:ef7eb2e8f9f7 146 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF);
<> 144:ef7eb2e8f9f7 147 LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF);
<> 144:ef7eb2e8f9f7 148 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF);
<> 144:ef7eb2e8f9f7 149 } else {
<> 144:ef7eb2e8f9f7 150 // Mark message valid, Direction = TX, Set Identifier and mask everything
<> 144:ef7eb2e8f9f7 151 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF);
<> 144:ef7eb2e8f9f7 152 LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF);
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 // Use mask, single message object and set DLC
<> 144:ef7eb2e8f9f7 156 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | CANIFn_MCTRL_RXIE | (DLC_MAX & 0xF);
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 // Transfer all fields to message object
<> 144:ef7eb2e8f9f7 159 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 // Start Transfer to given message number
<> 144:ef7eb2e8f9f7 162 LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 // Wait until transfer to message ram complete - TODO: maybe not block??
<> 144:ef7eb2e8f9f7 165 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 return handle;
<> 144:ef7eb2e8f9f7 169 }
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 static inline void can_irq() {
<> 144:ef7eb2e8f9f7 172 irq_handler(can_irq_id, IRQ_RX);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 // Register CAN object's irq handler
<> 144:ef7eb2e8f9f7 176 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 177 irq_handler = handler;
<> 144:ef7eb2e8f9f7 178 can_irq_id = id;
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 // Unregister CAN object's irq handler
<> 144:ef7eb2e8f9f7 182 void can_irq_free(can_t *obj) {
<> 144:ef7eb2e8f9f7 183 LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :)
<> 144:ef7eb2e8f9f7 184 can_irq_id = 0;
<> 144:ef7eb2e8f9f7 185 NVIC_DisableIRQ(C_CAN0_IRQn);
<> 144:ef7eb2e8f9f7 186 }
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 // Clear or set a irq
<> 144:ef7eb2e8f9f7 189 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
<> 144:ef7eb2e8f9f7 190 // Put CAN in Reset Mode and enable interrupt
<> 144:ef7eb2e8f9f7 191 can_disable(obj);
<> 144:ef7eb2e8f9f7 192 if (enable == 0) {
<> 144:ef7eb2e8f9f7 193 LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2);
<> 144:ef7eb2e8f9f7 194 } else {
<> 144:ef7eb2e8f9f7 195 LPC_C_CAN0->CANCNTL |= 1UL << 1 | 1UL << 2;
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197 // Take it out of reset...
<> 144:ef7eb2e8f9f7 198 can_enable(obj);
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 // Enable NVIC if at least 1 interrupt is active
<> 144:ef7eb2e8f9f7 201 NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq);
<> 144:ef7eb2e8f9f7 202 NVIC_EnableIRQ(C_CAN0_IRQn);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 // This table has the sampling points as close to 75% as possible. The first
<> 144:ef7eb2e8f9f7 206 // value is TSEG1, the second TSEG2.
<> 144:ef7eb2e8f9f7 207 static const int timing_pts[23][2] = {
<> 144:ef7eb2e8f9f7 208 {0x0, 0x0}, // 2, 50%
<> 144:ef7eb2e8f9f7 209 {0x1, 0x0}, // 3, 67%
<> 144:ef7eb2e8f9f7 210 {0x2, 0x0}, // 4, 75%
<> 144:ef7eb2e8f9f7 211 {0x3, 0x0}, // 5, 80%
<> 144:ef7eb2e8f9f7 212 {0x3, 0x1}, // 6, 67%
<> 144:ef7eb2e8f9f7 213 {0x4, 0x1}, // 7, 71%
<> 144:ef7eb2e8f9f7 214 {0x5, 0x1}, // 8, 75%
<> 144:ef7eb2e8f9f7 215 {0x6, 0x1}, // 9, 78%
<> 144:ef7eb2e8f9f7 216 {0x6, 0x2}, // 10, 70%
<> 144:ef7eb2e8f9f7 217 {0x7, 0x2}, // 11, 73%
<> 144:ef7eb2e8f9f7 218 {0x8, 0x2}, // 12, 75%
<> 144:ef7eb2e8f9f7 219 {0x9, 0x2}, // 13, 77%
<> 144:ef7eb2e8f9f7 220 {0x9, 0x3}, // 14, 71%
<> 144:ef7eb2e8f9f7 221 {0xA, 0x3}, // 15, 73%
<> 144:ef7eb2e8f9f7 222 {0xB, 0x3}, // 16, 75%
<> 144:ef7eb2e8f9f7 223 {0xC, 0x3}, // 17, 76%
<> 144:ef7eb2e8f9f7 224 {0xD, 0x3}, // 18, 78%
<> 144:ef7eb2e8f9f7 225 {0xD, 0x4}, // 19, 74%
<> 144:ef7eb2e8f9f7 226 {0xE, 0x4}, // 20, 75%
<> 144:ef7eb2e8f9f7 227 {0xF, 0x4}, // 21, 76%
<> 144:ef7eb2e8f9f7 228 {0xF, 0x5}, // 22, 73%
<> 144:ef7eb2e8f9f7 229 {0xF, 0x6}, // 23, 70%
<> 144:ef7eb2e8f9f7 230 {0xF, 0x7}, // 24, 67%
<> 144:ef7eb2e8f9f7 231 };
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
<> 144:ef7eb2e8f9f7 234 uint32_t btr;
<> 144:ef7eb2e8f9f7 235 uint32_t clkdiv = 1;
<> 144:ef7eb2e8f9f7 236 uint16_t brp = 0;
<> 144:ef7eb2e8f9f7 237 uint32_t calcbit;
<> 144:ef7eb2e8f9f7 238 uint32_t bitwidth;
<> 144:ef7eb2e8f9f7 239 int hit = 0;
<> 144:ef7eb2e8f9f7 240 int bits = 0;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 bitwidth = sclk / cclk;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 brp = bitwidth / 0x18;
<> 144:ef7eb2e8f9f7 245 while ((!hit) && (brp < bitwidth / 4)) {
<> 144:ef7eb2e8f9f7 246 brp++;
<> 144:ef7eb2e8f9f7 247 for (bits = 22; bits > 0; bits--) {
<> 144:ef7eb2e8f9f7 248 calcbit = (bits + 3) * (brp + 1);
<> 144:ef7eb2e8f9f7 249 if (calcbit == bitwidth) {
<> 144:ef7eb2e8f9f7 250 hit = 1;
<> 144:ef7eb2e8f9f7 251 break;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 clkdiv = clkdiv - 1;
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 if (hit) {
<> 144:ef7eb2e8f9f7 259 btr = (timing_pts[bits][1] & 0x7) << 12
<> 144:ef7eb2e8f9f7 260 | (timing_pts[bits][0] & 0xf) << 8
<> 144:ef7eb2e8f9f7 261 | (psjw & 0x3) << 6
<> 144:ef7eb2e8f9f7 262 | (brp & 0x3F);
<> 144:ef7eb2e8f9f7 263 btr = btr | (clkdiv << 16);
<> 144:ef7eb2e8f9f7 264 } else {
<> 144:ef7eb2e8f9f7 265 btr = 0;
<> 144:ef7eb2e8f9f7 266 }
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 return btr;
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 int can_config_rxmsgobj(can_t *obj) {
<> 144:ef7eb2e8f9f7 273 uint16_t i = 0;
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 // Make sure the interface is available
<> 144:ef7eb2e8f9f7 276 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 // Mark message valid, Direction = RX, Don't care about anything else
<> 144:ef7eb2e8f9f7 279 LPC_C_CAN0->CANIF1_ARB1 = 0;
<> 144:ef7eb2e8f9f7 280 LPC_C_CAN0->CANIF1_ARB2 = 0;
<> 144:ef7eb2e8f9f7 281 LPC_C_CAN0->CANIF1_MCTRL = 0;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 for ( i = 0; i < MSG_OBJ_MAX; i++ ) {
<> 144:ef7eb2e8f9f7 284 // Transfer arb and control fields to message object
<> 144:ef7eb2e8f9f7 285 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 // Start Transfer to given message number
<> 144:ef7eb2e8f9f7 288 LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F);
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 // Wait until transfer to message ram complete - TODO: maybe not block??
<> 144:ef7eb2e8f9f7 291 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 // Accept all messages
<> 144:ef7eb2e8f9f7 295 can_filter(obj, 0, 0, CANStandard, 1);
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 return 1;
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 void can_init(can_t *obj, PinName rd, PinName td) {
<> 144:ef7eb2e8f9f7 302 // Enable power and clock
<> 144:ef7eb2e8f9f7 303 LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7);
<> 144:ef7eb2e8f9f7 304 LPC_SYSCON->PRESETCTRL1 |= (1UL << 7);
<> 144:ef7eb2e8f9f7 305 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 // Enable Initialization mode
<> 144:ef7eb2e8f9f7 308 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
<> 144:ef7eb2e8f9f7 309 LPC_C_CAN0->CANCNTL |= (1UL << 0);
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L);
<> 144:ef7eb2e8f9f7 313 LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8);
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 can_frequency(obj, 100000);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 // Resume operation
<> 144:ef7eb2e8f9f7 318 LPC_C_CAN0->CANCNTL &= ~(1UL << 0);
<> 144:ef7eb2e8f9f7 319 while ( LPC_C_CAN0->CANCNTL & (1UL << 0) );
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 // Initialize RX message object
<> 144:ef7eb2e8f9f7 322 can_config_rxmsgobj(obj);
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 void can_free(can_t *obj) {
<> 144:ef7eb2e8f9f7 326 LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7);
<> 144:ef7eb2e8f9f7 327 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 int can_frequency(can_t *obj, int f) {
<> 144:ef7eb2e8f9f7 331 int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
<> 144:ef7eb2e8f9f7 332 int clkdiv = (btr >> 16) & 0x0F;
<> 144:ef7eb2e8f9f7 333 btr = btr & 0xFFFF;
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 if (btr > 0) {
<> 144:ef7eb2e8f9f7 336 // Set the bit clock
<> 144:ef7eb2e8f9f7 337 LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT
<> 144:ef7eb2e8f9f7 338 LPC_C_CAN0->CANCLKDIV = clkdiv;
<> 144:ef7eb2e8f9f7 339 LPC_C_CAN0->CANBT = btr;
<> 144:ef7eb2e8f9f7 340 LPC_C_CAN0->CANBRPE = 0x0000;
<> 144:ef7eb2e8f9f7 341 LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT
<> 144:ef7eb2e8f9f7 342 return 1;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 return 0;
<> 144:ef7eb2e8f9f7 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 int can_write(can_t *obj, CAN_Message msg, int cc) {
<> 144:ef7eb2e8f9f7 348 uint16_t msgnum = 0;
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 // Make sure controller is enabled
<> 144:ef7eb2e8f9f7 351 can_enable(obj);
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 // Make sure the interface is available
<> 144:ef7eb2e8f9f7 354 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY );
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 // Set the direction bit based on the message type
<> 144:ef7eb2e8f9f7 357 uint32_t direction = 0;
<> 144:ef7eb2e8f9f7 358 if (msg.type == CANData) {
<> 144:ef7eb2e8f9f7 359 direction = CANIFn_ARB2_DIR;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 if (msg.format == CANExtended) {
<> 144:ef7eb2e8f9f7 363 // Mark message valid, Extended Frame, Set Identifier and mask everything
<> 144:ef7eb2e8f9f7 364 LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF);
<> 144:ef7eb2e8f9f7 365 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF);
<> 144:ef7eb2e8f9f7 366 LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF);
<> 144:ef7eb2e8f9f7 367 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF);
<> 144:ef7eb2e8f9f7 368 } else {
<> 144:ef7eb2e8f9f7 369 // Mark message valid, Set Identifier and mask everything
<> 144:ef7eb2e8f9f7 370 LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF);
<> 144:ef7eb2e8f9f7 371 LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF);
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 // Use mask, request transmission, single message object and set DLC
<> 144:ef7eb2e8f9f7 375 LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF);
<> 144:ef7eb2e8f9f7 378 LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF);
<> 144:ef7eb2e8f9f7 379 LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF);
<> 144:ef7eb2e8f9f7 380 LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF);
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 // Transfer all fields to message object
<> 144:ef7eb2e8f9f7 383 LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 // Start Transfer to given message number
<> 144:ef7eb2e8f9f7 386 LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F);
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 // Wait until transfer to message ram complete - TODO: maybe not block??
<> 144:ef7eb2e8f9f7 389 while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 // Wait until TXOK is set, then clear it - TODO: maybe not block
<> 144:ef7eb2e8f9f7 392 //while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) );
<> 144:ef7eb2e8f9f7 393 LPC_C_CAN0->CANSTAT &= ~(1UL << 3);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 return 1;
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 int can_read(can_t *obj, CAN_Message *msg, int handle) {
<> 144:ef7eb2e8f9f7 399 uint16_t i;
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 // Make sure controller is enabled
<> 144:ef7eb2e8f9f7 402 can_enable(obj);
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 // Find first message object with new data
<> 144:ef7eb2e8f9f7 405 if (handle == 0) {
<> 144:ef7eb2e8f9f7 406 uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16);
<> 144:ef7eb2e8f9f7 407 // Find first free messagebox
<> 144:ef7eb2e8f9f7 408 for (i = 0; i < 32; i++) {
<> 144:ef7eb2e8f9f7 409 if (newdata & (1 << i)) {
<> 144:ef7eb2e8f9f7 410 handle = i+1;
<> 144:ef7eb2e8f9f7 411 break;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 if (handle > 0 && handle < 32) {
<> 144:ef7eb2e8f9f7 417 // Wait until message interface is free
<> 144:ef7eb2e8f9f7 418 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 // Transfer all fields to message object
<> 144:ef7eb2e8f9f7 421 LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 // Start Transfer from given message number
<> 144:ef7eb2e8f9f7 424 LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 // Wait until transfer to message ram complete
<> 144:ef7eb2e8f9f7 427 while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY );
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) {
<> 144:ef7eb2e8f9f7 430 msg->format = CANExtended;
<> 144:ef7eb2e8f9f7 431 msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16;
<> 144:ef7eb2e8f9f7 432 msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF);
<> 144:ef7eb2e8f9f7 433 } else {
<> 144:ef7eb2e8f9f7 434 msg->format = CANStandard;
<> 144:ef7eb2e8f9f7 435 msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) {
<> 144:ef7eb2e8f9f7 439 msg->type = CANRemote;
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441 else {
<> 144:ef7eb2e8f9f7 442 msg->type = CANData;
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 msg->len = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8
<> 144:ef7eb2e8f9f7 446 msg->data[0] = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF);
<> 144:ef7eb2e8f9f7 447 msg->data[1] = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF);
<> 144:ef7eb2e8f9f7 448 msg->data[2] = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF);
<> 144:ef7eb2e8f9f7 449 msg->data[3] = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF);
<> 144:ef7eb2e8f9f7 450 msg->data[4] = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF);
<> 144:ef7eb2e8f9f7 451 msg->data[5] = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF);
<> 144:ef7eb2e8f9f7 452 msg->data[6] = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF);
<> 144:ef7eb2e8f9f7 453 msg->data[7] = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF);
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 LPC_C_CAN0->CANSTAT &= ~(1UL << 4);
<> 144:ef7eb2e8f9f7 456 return 1;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458 return 0;
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 void can_reset(can_t *obj) {
<> 144:ef7eb2e8f9f7 462 LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7);
<> 144:ef7eb2e8f9f7 463 LPC_C_CAN0->CANSTAT = 0;
<> 144:ef7eb2e8f9f7 464 can_config_rxmsgobj(obj);
<> 144:ef7eb2e8f9f7 465 }
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 unsigned char can_rderror(can_t *obj) {
<> 144:ef7eb2e8f9f7 468 return ((LPC_C_CAN0->CANEC >> 8) & 0x7F);
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 unsigned char can_tderror(can_t *obj) {
<> 144:ef7eb2e8f9f7 472 return (LPC_C_CAN0->CANEC & 0xFF);
<> 144:ef7eb2e8f9f7 473 }
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 void can_monitor(can_t *obj, int silent) {
<> 144:ef7eb2e8f9f7 476 if (silent) {
<> 144:ef7eb2e8f9f7 477 LPC_C_CAN0->CANCNTL |= (1UL << 7);
<> 144:ef7eb2e8f9f7 478 LPC_C_CAN0->CANTEST |= (1UL << 3);
<> 144:ef7eb2e8f9f7 479 } else {
<> 144:ef7eb2e8f9f7 480 LPC_C_CAN0->CANCNTL &= ~(1UL << 7);
<> 144:ef7eb2e8f9f7 481 LPC_C_CAN0->CANTEST &= ~(1UL << 3);
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) {
<> 144:ef7eb2e8f9f7 485 LPC_C_CAN0->CANCNTL |= (1UL << 0);
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 }