mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.h@184:08ed48f1de7f, 2018-04-19 (annotated)

Committer:
AnnaBridge
Date:
Thu Apr 19 17:12:19 2018 +0100
Revision:
184:08ed48f1de7f
Parent:
149:156823d33999 
mbed-dev library. Release version 161

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_i2s.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Header file of I2S HAL module.
<> 149:156823d33999 6 ******************************************************************************
<> 149:156823d33999 7 * @attention
<> 149:156823d33999 8 *
AnnaBridge 184:08ed48f1de7f 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 12 * are permitted provided that the following conditions are met:
<> 149:156823d33999 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 14 * this list of conditions and the following disclaimer.
<> 149:156823d33999 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 16 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 17 * and/or other materials provided with the distribution.
<> 149:156823d33999 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 19 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 20 * without specific prior written permission.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 32 *
<> 149:156823d33999 33 ******************************************************************************
<> 149:156823d33999 34 */
<> 149:156823d33999 35
<> 149:156823d33999 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 37 #ifndef __STM32L1xx_HAL_I2S_H
<> 149:156823d33999 38 #define __STM32L1xx_HAL_I2S_H
<> 149:156823d33999 39
<> 149:156823d33999 40 #ifdef __cplusplus
<> 149:156823d33999 41 extern "C" {
<> 149:156823d33999 42 #endif
<> 149:156823d33999 43
<> 149:156823d33999 44 #if defined(STM32L100xC) || \
<> 149:156823d33999 45 defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || defined(STM32L151xDX) || \
<> 149:156823d33999 46 defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L151xE) || defined(STM32L151xDX) || \
<> 149:156823d33999 47 defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
<> 149:156823d33999 48
<> 149:156823d33999 49 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 50 #include "stm32l1xx_hal_def.h"
<> 149:156823d33999 51
<> 149:156823d33999 52 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 53 * @{
<> 149:156823d33999 54 */
<> 149:156823d33999 55
<> 149:156823d33999 56 /** @addtogroup I2S
<> 149:156823d33999 57 * @{
<> 149:156823d33999 58 */
<> 149:156823d33999 59
<> 149:156823d33999 60 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 61 /** @defgroup I2S_Exported_Types I2S Exported Types
<> 149:156823d33999 62 * @{
<> 149:156823d33999 63 */
<> 149:156823d33999 64
<> 149:156823d33999 65 /**
<> 149:156823d33999 66 * @brief I2S Init structure definition
<> 149:156823d33999 67 */
<> 149:156823d33999 68 typedef struct
<> 149:156823d33999 69 {
<> 149:156823d33999 70 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 149:156823d33999 71 This parameter can be a value of @ref I2S_Mode */
<> 149:156823d33999 72
<> 149:156823d33999 73 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 149:156823d33999 74 This parameter can be a value of @ref I2S_Standard */
<> 149:156823d33999 75
<> 149:156823d33999 76 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 149:156823d33999 77 This parameter can be a value of @ref I2S_Data_Format */
<> 149:156823d33999 78
<> 149:156823d33999 79 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 149:156823d33999 80 This parameter can be a value of @ref I2S_MCLK_Output */
<> 149:156823d33999 81
<> 149:156823d33999 82 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 149:156823d33999 83 This parameter can be a value of @ref I2S_Audio_Frequency */
<> 149:156823d33999 84
<> 149:156823d33999 85 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
<> 149:156823d33999 86 This parameter can be a value of @ref I2S_Clock_Polarity */
<> 149:156823d33999 87
<> 149:156823d33999 88 }I2S_InitTypeDef;
<> 149:156823d33999 89
<> 149:156823d33999 90 /**
<> 149:156823d33999 91 * @brief HAL State structures definition
<> 149:156823d33999 92 */
<> 149:156823d33999 93 typedef enum
<> 149:156823d33999 94 {
<> 149:156823d33999 95 HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
<> 149:156823d33999 96 HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
<> 149:156823d33999 97 HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
<> 149:156823d33999 98 HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 149:156823d33999 99 HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 149:156823d33999 100 HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S pause state: used in case of DMA */
<> 149:156823d33999 101 HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
<> 149:156823d33999 102 }HAL_I2S_StateTypeDef;
<> 149:156823d33999 103
<> 149:156823d33999 104 /**
<> 149:156823d33999 105 * @brief I2S handle Structure definition
<> 149:156823d33999 106 */
<> 149:156823d33999 107 typedef struct
<> 149:156823d33999 108 {
<> 149:156823d33999 109 SPI_TypeDef *Instance; /* I2S registers base address */
<> 149:156823d33999 110
<> 149:156823d33999 111 I2S_InitTypeDef Init; /* I2S communication parameters */
<> 149:156823d33999 112
<> 149:156823d33999 113 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
<> 149:156823d33999 114
<> 149:156823d33999 115 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
<> 149:156823d33999 116
<> 149:156823d33999 117 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
<> 149:156823d33999 118
<> 149:156823d33999 119 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
<> 149:156823d33999 120
<> 149:156823d33999 121 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
<> 149:156823d33999 122
<> 149:156823d33999 123 __IO uint16_t RxXferCount; /* I2S Rx transfer counter
<> 149:156823d33999 124 (This field is initialized at the
<> 149:156823d33999 125 same value as transfer size at the
<> 149:156823d33999 126 beginning of the transfer and
<> 149:156823d33999 127 decremented when a sample is received.
<> 149:156823d33999 128 NbSamplesReceived = RxBufferSize-RxBufferCount) */
<> 149:156823d33999 129
<> 149:156823d33999 130 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
<> 149:156823d33999 131
<> 149:156823d33999 132 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
<> 149:156823d33999 133
<> 149:156823d33999 134 __IO HAL_LockTypeDef Lock; /* I2S locking object */
<> 149:156823d33999 135
<> 149:156823d33999 136 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
<> 149:156823d33999 137
<> 149:156823d33999 138 __IO uint32_t ErrorCode; /* I2S Error code */
<> 149:156823d33999 139
<> 149:156823d33999 140 }I2S_HandleTypeDef;
<> 149:156823d33999 141 /**
<> 149:156823d33999 142 * @}
<> 149:156823d33999 143 */
<> 149:156823d33999 144
<> 149:156823d33999 145 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 146 /** @defgroup I2S_Exported_Constants I2S Exported Constants
<> 149:156823d33999 147 * @{
<> 149:156823d33999 148 */
<> 149:156823d33999 149
<> 149:156823d33999 150 /** @defgroup I2S_Error_Codes I2S Error Codes
<> 149:156823d33999 151 * @{
<> 149:156823d33999 152 */
<> 149:156823d33999 153
AnnaBridge 184:08ed48f1de7f 154 #define HAL_I2S_ERROR_NONE (0x00U) /*!< No error */
AnnaBridge 184:08ed48f1de7f 155 #define HAL_I2S_ERROR_UDR (0x01U) /*!< I2S Underrun error */
AnnaBridge 184:08ed48f1de7f 156 #define HAL_I2S_ERROR_OVR (0x02U) /*!< I2S Overrun error */
AnnaBridge 184:08ed48f1de7f 157 #define HAL_I2S_ERROR_FRE (0x04U) /*!< I2S Frame format error */
AnnaBridge 184:08ed48f1de7f 158 #define HAL_I2S_ERROR_DMA (0x08U) /*!< DMA transfer error */
<> 149:156823d33999 159
<> 149:156823d33999 160 /**
<> 149:156823d33999 161 * @}
<> 149:156823d33999 162 */
<> 149:156823d33999 163
<> 149:156823d33999 164 /** @defgroup I2S_Mode I2S Mode
<> 149:156823d33999 165 * @{
<> 149:156823d33999 166 */
AnnaBridge 184:08ed48f1de7f 167 #define I2S_MODE_SLAVE_TX (0x00000000U)
AnnaBridge 184:08ed48f1de7f 168 #define I2S_MODE_SLAVE_RX (0x00000100U)
AnnaBridge 184:08ed48f1de7f 169 #define I2S_MODE_MASTER_TX (0x00000200U)
AnnaBridge 184:08ed48f1de7f 170 #define I2S_MODE_MASTER_RX (0x00000300U)
<> 149:156823d33999 171
<> 149:156823d33999 172 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
<> 149:156823d33999 173 ((MODE) == I2S_MODE_SLAVE_RX) || \
<> 149:156823d33999 174 ((MODE) == I2S_MODE_MASTER_TX) || \
<> 149:156823d33999 175 ((MODE) == I2S_MODE_MASTER_RX))
<> 149:156823d33999 176 /**
<> 149:156823d33999 177 * @}
<> 149:156823d33999 178 */
<> 149:156823d33999 179
<> 149:156823d33999 180 /** @defgroup I2S_Standard I2S Standard
<> 149:156823d33999 181 * @{
<> 149:156823d33999 182 */
AnnaBridge 184:08ed48f1de7f 183 #define I2S_STANDARD_PHILIPS (0x00000000U)
<> 149:156823d33999 184 #define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
<> 149:156823d33999 185 #define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
<> 149:156823d33999 186 #define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
<> 149:156823d33999 187 SPI_I2SCFGR_I2SSTD_1))
<> 149:156823d33999 188 #define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
<> 149:156823d33999 189 SPI_I2SCFGR_I2SSTD_1 |\
<> 149:156823d33999 190 SPI_I2SCFGR_PCMSYNC))
<> 149:156823d33999 191
<> 149:156823d33999 192 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
<> 149:156823d33999 193 ((STANDARD) == I2S_STANDARD_MSB) || \
<> 149:156823d33999 194 ((STANDARD) == I2S_STANDARD_LSB) || \
<> 149:156823d33999 195 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
<> 149:156823d33999 196 ((STANDARD) == I2S_STANDARD_PCM_LONG))
<> 149:156823d33999 197
<> 149:156823d33999 198 /**
<> 149:156823d33999 199 * @}
<> 149:156823d33999 200 */
<> 149:156823d33999 201
<> 149:156823d33999 202 /** @defgroup I2S_Data_Format I2S Data Format
<> 149:156823d33999 203 * @{
<> 149:156823d33999 204 */
AnnaBridge 184:08ed48f1de7f 205 #define I2S_DATAFORMAT_16B (0x00000000U)
<> 149:156823d33999 206 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
<> 149:156823d33999 207 #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
<> 149:156823d33999 208 #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
<> 149:156823d33999 209
<> 149:156823d33999 210 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
<> 149:156823d33999 211 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
<> 149:156823d33999 212 ((FORMAT) == I2S_DATAFORMAT_24B) || \
<> 149:156823d33999 213 ((FORMAT) == I2S_DATAFORMAT_32B))
<> 149:156823d33999 214 /**
<> 149:156823d33999 215 * @}
<> 149:156823d33999 216 */
<> 149:156823d33999 217
<> 149:156823d33999 218 /** @defgroup I2S_MCLK_Output I2S MCLK Output
<> 149:156823d33999 219 * @{
<> 149:156823d33999 220 */
<> 149:156823d33999 221 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
AnnaBridge 184:08ed48f1de7f 222 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
<> 149:156823d33999 223
<> 149:156823d33999 224 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
<> 149:156823d33999 225 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
<> 149:156823d33999 226 /**
<> 149:156823d33999 227 * @}
<> 149:156823d33999 228 */
<> 149:156823d33999 229
<> 149:156823d33999 230 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
<> 149:156823d33999 231 * @{
<> 149:156823d33999 232 */
AnnaBridge 184:08ed48f1de7f 233 #define I2S_AUDIOFREQ_192K (192000U)
AnnaBridge 184:08ed48f1de7f 234 #define I2S_AUDIOFREQ_96K (96000U)
AnnaBridge 184:08ed48f1de7f 235 #define I2S_AUDIOFREQ_48K (48000U)
AnnaBridge 184:08ed48f1de7f 236 #define I2S_AUDIOFREQ_44K (44100U)
AnnaBridge 184:08ed48f1de7f 237 #define I2S_AUDIOFREQ_32K (32000U)
AnnaBridge 184:08ed48f1de7f 238 #define I2S_AUDIOFREQ_22K (22050U)
AnnaBridge 184:08ed48f1de7f 239 #define I2S_AUDIOFREQ_16K (16000U)
AnnaBridge 184:08ed48f1de7f 240 #define I2S_AUDIOFREQ_11K (11025U)
AnnaBridge 184:08ed48f1de7f 241 #define I2S_AUDIOFREQ_8K (8000U)
AnnaBridge 184:08ed48f1de7f 242 #define I2S_AUDIOFREQ_DEFAULT (2U)
<> 149:156823d33999 243
<> 149:156823d33999 244 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
<> 149:156823d33999 245 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
<> 149:156823d33999 246 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
<> 149:156823d33999 247 /**
<> 149:156823d33999 248 * @}
<> 149:156823d33999 249 */
<> 149:156823d33999 250
<> 149:156823d33999 251 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
<> 149:156823d33999 252 * @{
<> 149:156823d33999 253 */
AnnaBridge 184:08ed48f1de7f 254 #define I2S_CPOL_LOW (0x00000000U)
<> 149:156823d33999 255 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
<> 149:156823d33999 256
<> 149:156823d33999 257 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
<> 149:156823d33999 258 ((CPOL) == I2S_CPOL_HIGH))
<> 149:156823d33999 259 /**
<> 149:156823d33999 260 * @}
<> 149:156823d33999 261 */
<> 149:156823d33999 262
<> 149:156823d33999 263 /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
<> 149:156823d33999 264 * @{
<> 149:156823d33999 265 */
<> 149:156823d33999 266 #define I2S_IT_TXE SPI_CR2_TXEIE
<> 149:156823d33999 267 #define I2S_IT_RXNE SPI_CR2_RXNEIE
<> 149:156823d33999 268 #define I2S_IT_ERR SPI_CR2_ERRIE
<> 149:156823d33999 269 /**
<> 149:156823d33999 270 * @}
<> 149:156823d33999 271 */
<> 149:156823d33999 272
<> 149:156823d33999 273 /** @defgroup I2S_Flag_definition I2S Flag definition
<> 149:156823d33999 274 * @{
<> 149:156823d33999 275 */
<> 149:156823d33999 276 #define I2S_FLAG_TXE SPI_SR_TXE
<> 149:156823d33999 277 #define I2S_FLAG_RXNE SPI_SR_RXNE
<> 149:156823d33999 278
<> 149:156823d33999 279 #define I2S_FLAG_UDR SPI_SR_UDR
<> 149:156823d33999 280 #define I2S_FLAG_OVR SPI_SR_OVR
<> 149:156823d33999 281 #define I2S_FLAG_FRE SPI_SR_FRE
<> 149:156823d33999 282
<> 149:156823d33999 283 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
<> 149:156823d33999 284 #define I2S_FLAG_BSY SPI_SR_BSY
<> 149:156823d33999 285 /**
<> 149:156823d33999 286 * @}
<> 149:156823d33999 287 */
<> 149:156823d33999 288
<> 149:156823d33999 289 /**
<> 149:156823d33999 290 * @}
<> 149:156823d33999 291 */
<> 149:156823d33999 292
<> 149:156823d33999 293 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 294 /** @defgroup I2S_Exported_macros I2S Exported Macros
<> 149:156823d33999 295 * @{
<> 149:156823d33999 296 */
<> 149:156823d33999 297
<> 149:156823d33999 298 /** @brief Reset I2S handle state
<> 149:156823d33999 299 * @param __HANDLE__: specifies the I2S Handle.
<> 149:156823d33999 300 * @retval None
<> 149:156823d33999 301 */
<> 149:156823d33999 302 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
<> 149:156823d33999 303
<> 149:156823d33999 304 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
<> 149:156823d33999 305 * @param __HANDLE__: specifies the I2S Handle.
<> 149:156823d33999 306 * @retval None
<> 149:156823d33999 307 */
<> 149:156823d33999 308 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 149:156823d33999 309 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 149:156823d33999 310
<> 149:156823d33999 311 /** @brief Enable or disable the specified I2S interrupts.
<> 149:156823d33999 312 * @param __HANDLE__: specifies the I2S Handle.
<> 149:156823d33999 313 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 149:156823d33999 314 * This parameter can be one of the following values:
<> 149:156823d33999 315 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 149:156823d33999 316 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 149:156823d33999 317 * @arg I2S_IT_ERR: Error interrupt enable
<> 149:156823d33999 318 * @retval None
<> 149:156823d33999 319 */
<> 149:156823d33999 320 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
<> 149:156823d33999 321 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
<> 149:156823d33999 322
<> 149:156823d33999 323 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
<> 149:156823d33999 324 * @param __HANDLE__: specifies the I2S Handle.
<> 149:156823d33999 325 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
<> 149:156823d33999 326 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
<> 149:156823d33999 327 * This parameter can be one of the following values:
<> 149:156823d33999 328 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 149:156823d33999 329 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 149:156823d33999 330 * @arg I2S_IT_ERR: Error interrupt enable
<> 149:156823d33999 331 * @retval The new state of __IT__ (TRUE or FALSE).
<> 149:156823d33999 332 */
<> 149:156823d33999 333 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 149:156823d33999 334
<> 149:156823d33999 335 /** @brief Checks whether the specified I2S flag is set or not.
<> 149:156823d33999 336 * @param __HANDLE__: specifies the I2S Handle.
<> 149:156823d33999 337 * @param __FLAG__: specifies the flag to check.
<> 149:156823d33999 338 * This parameter can be one of the following values:
<> 149:156823d33999 339 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
<> 149:156823d33999 340 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
<> 149:156823d33999 341 * @arg I2S_FLAG_UDR: Underrun flag
<> 149:156823d33999 342 * @arg I2S_FLAG_OVR: Overrun flag
<> 149:156823d33999 343 * @arg I2S_FLAG_FRE: Frame error flag
<> 149:156823d33999 344 * @arg I2S_FLAG_CHSIDE: Channel Side flag
<> 149:156823d33999 345 * @arg I2S_FLAG_BSY: Busy flag
<> 149:156823d33999 346 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 149:156823d33999 347 */
<> 149:156823d33999 348 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 149:156823d33999 349
<> 149:156823d33999 350 /** @brief Clears the I2S OVR pending flag.
<> 149:156823d33999 351 * @param __HANDLE__: specifies the I2S Handle.
<> 149:156823d33999 352 * @retval None
<> 149:156823d33999 353 */
<> 149:156823d33999 354 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
<> 149:156823d33999 355 tmpreg = (__HANDLE__)->Instance->SR;\
<> 149:156823d33999 356 UNUSED(tmpreg); \
<> 149:156823d33999 357 }while(0)
<> 149:156823d33999 358 /** @brief Clears the I2S UDR pending flag.
<> 149:156823d33999 359 * @param __HANDLE__: specifies the I2S Handle.
<> 149:156823d33999 360 * @retval None
<> 149:156823d33999 361 */
<> 149:156823d33999 362 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
<> 149:156823d33999 363 /**
<> 149:156823d33999 364 * @}
<> 149:156823d33999 365 */
<> 149:156823d33999 366
<> 149:156823d33999 367 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 368 /** @addtogroup I2S_Exported_Functions
<> 149:156823d33999 369 * @{
<> 149:156823d33999 370 */
<> 149:156823d33999 371
<> 149:156823d33999 372 /** @addtogroup I2S_Exported_Functions_Group1
<> 149:156823d33999 373 * @{
<> 149:156823d33999 374 */
<> 149:156823d33999 375 /* Initialization/de-initialization functions ********************************/
<> 149:156823d33999 376 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 377 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 378 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 379 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 380 /**
<> 149:156823d33999 381 * @}
<> 149:156823d33999 382 */
<> 149:156823d33999 383
<> 149:156823d33999 384 /** @addtogroup I2S_Exported_Functions_Group2
<> 149:156823d33999 385 * @{
<> 149:156823d33999 386 */
<> 149:156823d33999 387 /* I/O operation functions ***************************************************/
<> 149:156823d33999 388 /* Blocking mode: Polling */
<> 149:156823d33999 389 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 149:156823d33999 390 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 149:156823d33999 391
<> 149:156823d33999 392 /* Non-Blocking mode: Interrupt */
<> 149:156823d33999 393 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 149:156823d33999 394 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 149:156823d33999 395 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 396
<> 149:156823d33999 397 /* Non-Blocking mode: DMA */
<> 149:156823d33999 398 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 149:156823d33999 399 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 149:156823d33999 400
<> 149:156823d33999 401 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 402 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 403 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 404
<> 149:156823d33999 405 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
<> 149:156823d33999 406 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 407 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 408 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 409 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 410 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 411 /**
<> 149:156823d33999 412 * @}
<> 149:156823d33999 413 */
<> 149:156823d33999 414
<> 149:156823d33999 415 /** @addtogroup I2S_Exported_Functions_Group3
<> 149:156823d33999 416 * @{
<> 149:156823d33999 417 */
<> 149:156823d33999 418 /* Peripheral Control and State functions ************************************/
<> 149:156823d33999 419 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 420 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
<> 149:156823d33999 421 /**
<> 149:156823d33999 422 * @}
<> 149:156823d33999 423 */
<> 149:156823d33999 424
<> 149:156823d33999 425 /**
<> 149:156823d33999 426 * @}
<> 149:156823d33999 427 */
<> 149:156823d33999 428
<> 149:156823d33999 429
<> 149:156823d33999 430 /**
<> 149:156823d33999 431 * @}
<> 149:156823d33999 432 */
<> 149:156823d33999 433
<> 149:156823d33999 434 /**
<> 149:156823d33999 435 * @}
<> 149:156823d33999 436 */
<> 149:156823d33999 437 #endif /* STM32L100xC ||
<> 149:156823d33999 438 STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE || STM32L151xDX ||\\
<> 149:156823d33999 439 STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L152xDX || STM32L151xE || STM32L151xDX ||\\
<> 149:156823d33999 440 STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
<> 149:156823d33999 441
<> 149:156823d33999 442 #ifdef __cplusplus
<> 149:156823d33999 443 }
<> 149:156823d33999 444 #endif
<> 149:156823d33999 445
<> 149:156823d33999 446 #endif /* __STM32L1xx_HAL_I2S_H */
<> 149:156823d33999 447
<> 149:156823d33999 448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/