mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c@187:0387e8f68319, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:40:20 2018 +0100
Revision:
187:0387e8f68319
Parent:
182:a56a73fd2a6f
Child:
189:f392fc9709a3
mbed-dev library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 168:9672193075cf 1 /* mbed Microcontroller Library
AnnaBridge 168:9672193075cf 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 168:9672193075cf 3 *
AnnaBridge 168:9672193075cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 168:9672193075cf 5 * you may not use this file except in compliance with the License.
AnnaBridge 168:9672193075cf 6 * You may obtain a copy of the License at
AnnaBridge 168:9672193075cf 7 *
AnnaBridge 168:9672193075cf 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 168:9672193075cf 9 *
AnnaBridge 168:9672193075cf 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 168:9672193075cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 168:9672193075cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 168:9672193075cf 13 * See the License for the specific language governing permissions and
AnnaBridge 168:9672193075cf 14 * limitations under the License.
AnnaBridge 168:9672193075cf 15 */
AnnaBridge 168:9672193075cf 16
AnnaBridge 168:9672193075cf 17 /**
AnnaBridge 168:9672193075cf 18 * This file configures the system clock as follows:
AnnaBridge 168:9672193075cf 19 *-----------------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
AnnaBridge 168:9672193075cf 21 * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1
AnnaBridge 168:9672193075cf 22 * | 3- USE_PLL_HSI (internal 16 MHz clock) |
AnnaBridge 168:9672193075cf 23 *-----------------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 24 * SYSCLK(MHz) | 180 | 168
AnnaBridge 168:9672193075cf 25 * AHBCLK (MHz) | 180 | 168
AnnaBridge 168:9672193075cf 26 * APB1CLK (MHz) | 45 | 42
AnnaBridge 168:9672193075cf 27 * APB2CLK (MHz) | 90 | 84
AnnaBridge 168:9672193075cf 28 * USB capable (48 MHz) | NO | YES (HSI calibration needed)
AnnaBridge 168:9672193075cf 29 *-----------------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 30 **/
AnnaBridge 168:9672193075cf 31
AnnaBridge 168:9672193075cf 32 #include "stm32f4xx.h"
AnnaBridge 168:9672193075cf 33
AnnaBridge 187:0387e8f68319 34 #include "mbed_error.h"
AnnaBridge 168:9672193075cf 35
AnnaBridge 168:9672193075cf 36 // clock source is selected with CLOCK_SOURCE in json config
AnnaBridge 168:9672193075cf 37 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
AnnaBridge 168:9672193075cf 38 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
AnnaBridge 168:9672193075cf 39 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 168:9672193075cf 40
AnnaBridge 168:9672193075cf 41 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 42 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 168:9672193075cf 43 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 44
AnnaBridge 168:9672193075cf 45 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 46 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 168:9672193075cf 47 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 168:9672193075cf 48
AnnaBridge 168:9672193075cf 49
AnnaBridge 168:9672193075cf 50 /**
AnnaBridge 168:9672193075cf 51 * @brief Setup the microcontroller system
AnnaBridge 168:9672193075cf 52 * Initialize the FPU setting, vector table location and External memory
AnnaBridge 168:9672193075cf 53 * configuration.
AnnaBridge 168:9672193075cf 54 * @param None
AnnaBridge 168:9672193075cf 55 * @retval None
AnnaBridge 168:9672193075cf 56 */
AnnaBridge 168:9672193075cf 57 void SystemInit(void)
AnnaBridge 168:9672193075cf 58 {
AnnaBridge 168:9672193075cf 59 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 168:9672193075cf 60 /* Set HSION bit */
AnnaBridge 168:9672193075cf 61 RCC->CR |= (uint32_t)0x00000001;
AnnaBridge 168:9672193075cf 62
AnnaBridge 168:9672193075cf 63 /* Reset CFGR register */
AnnaBridge 168:9672193075cf 64 RCC->CFGR = 0x00000000;
AnnaBridge 168:9672193075cf 65
AnnaBridge 168:9672193075cf 66 /* Reset HSEON, CSSON and PLLON bits */
AnnaBridge 168:9672193075cf 67 RCC->CR &= (uint32_t)0xFEF6FFFF;
AnnaBridge 168:9672193075cf 68
AnnaBridge 168:9672193075cf 69 /* Reset PLLCFGR register */
AnnaBridge 168:9672193075cf 70 RCC->PLLCFGR = 0x24003010;
AnnaBridge 168:9672193075cf 71
AnnaBridge 168:9672193075cf 72 /* Reset HSEBYP bit */
AnnaBridge 168:9672193075cf 73 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 168:9672193075cf 74
AnnaBridge 168:9672193075cf 75 /* Disable all interrupts */
AnnaBridge 168:9672193075cf 76 RCC->CIR = 0x00000000;
AnnaBridge 168:9672193075cf 77
AnnaBridge 168:9672193075cf 78 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
AnnaBridge 168:9672193075cf 79 SystemInit_ExtMemCtl();
AnnaBridge 168:9672193075cf 80 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
AnnaBridge 168:9672193075cf 81
AnnaBridge 168:9672193075cf 82 }
AnnaBridge 168:9672193075cf 83
AnnaBridge 168:9672193075cf 84 /**
AnnaBridge 168:9672193075cf 85 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 168:9672193075cf 86 * AHB/APBx prescalers and Flash settings
AnnaBridge 168:9672193075cf 87 * @note This function should be called only once the RCC clock configuration
AnnaBridge 168:9672193075cf 88 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 168:9672193075cf 89 * @param None
AnnaBridge 168:9672193075cf 90 * @retval None
AnnaBridge 168:9672193075cf 91 */
AnnaBridge 168:9672193075cf 92
AnnaBridge 168:9672193075cf 93 void SetSysClock(void)
AnnaBridge 168:9672193075cf 94 {
AnnaBridge 168:9672193075cf 95 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 168:9672193075cf 96 /* 1- Try to start with HSE and external clock */
AnnaBridge 168:9672193075cf 97 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 168:9672193075cf 98 #endif
AnnaBridge 168:9672193075cf 99 {
AnnaBridge 168:9672193075cf 100 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 168:9672193075cf 101 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 168:9672193075cf 102 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 168:9672193075cf 103 #endif
AnnaBridge 168:9672193075cf 104 {
AnnaBridge 168:9672193075cf 105 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 106 /* 3- If fail start with HSI clock */
AnnaBridge 168:9672193075cf 107 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 168:9672193075cf 108 #endif
AnnaBridge 168:9672193075cf 109 {
AnnaBridge 187:0387e8f68319 110 {
AnnaBridge 187:0387e8f68319 111 error("SetSysClock failed\n");
AnnaBridge 168:9672193075cf 112 }
AnnaBridge 168:9672193075cf 113 }
AnnaBridge 168:9672193075cf 114 }
AnnaBridge 168:9672193075cf 115 }
AnnaBridge 168:9672193075cf 116 }
AnnaBridge 168:9672193075cf 117
AnnaBridge 168:9672193075cf 118 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 168:9672193075cf 119 /******************************************************************************/
AnnaBridge 168:9672193075cf 120 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 168:9672193075cf 121 /******************************************************************************/
AnnaBridge 168:9672193075cf 122 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 168:9672193075cf 123 {
AnnaBridge 168:9672193075cf 124 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 125 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 126
AnnaBridge 168:9672193075cf 127 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 128 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 129 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 130 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 131 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 132
AnnaBridge 168:9672193075cf 133 // Enable HSE oscillator and activate PLL with HSE as source
AnnaBridge 168:9672193075cf 134 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 135 if (bypass == 0) {
AnnaBridge 168:9672193075cf 136 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
AnnaBridge 168:9672193075cf 137 } else {
AnnaBridge 168:9672193075cf 138 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
AnnaBridge 168:9672193075cf 139 }
AnnaBridge 168:9672193075cf 140
AnnaBridge 168:9672193075cf 141 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 142 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 168:9672193075cf 143 RCC_OscInitStruct.PLL.PLLM = 8;
AnnaBridge 168:9672193075cf 144 #if (CLOCK_SOURCE_USB)
AnnaBridge 168:9672193075cf 145 RCC_OscInitStruct.PLL.PLLN = 336;
AnnaBridge 168:9672193075cf 146 #else
AnnaBridge 168:9672193075cf 147 RCC_OscInitStruct.PLL.PLLN = 360;
AnnaBridge 168:9672193075cf 148 #endif
AnnaBridge 168:9672193075cf 149 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
AnnaBridge 168:9672193075cf 150 RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
AnnaBridge 168:9672193075cf 151 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 152 return 0; // FAIL
AnnaBridge 168:9672193075cf 153 }
AnnaBridge 168:9672193075cf 154
AnnaBridge 168:9672193075cf 155 // Activate the OverDrive to reach the 180 MHz Frequency
AnnaBridge 168:9672193075cf 156 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
AnnaBridge 168:9672193075cf 157 return 0; // FAIL
AnnaBridge 168:9672193075cf 158 }
AnnaBridge 168:9672193075cf 159
AnnaBridge 168:9672193075cf 160 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 168:9672193075cf 161 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
AnnaBridge 168:9672193075cf 162 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
AnnaBridge 168:9672193075cf 163 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
AnnaBridge 168:9672193075cf 164 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
AnnaBridge 168:9672193075cf 165 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
AnnaBridge 168:9672193075cf 166 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
AnnaBridge 168:9672193075cf 167 return 0; // FAIL
AnnaBridge 168:9672193075cf 168 }
AnnaBridge 168:9672193075cf 169
AnnaBridge 168:9672193075cf 170 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
AnnaBridge 168:9672193075cf 171
AnnaBridge 168:9672193075cf 172 return 1;
AnnaBridge 168:9672193075cf 173 }
AnnaBridge 168:9672193075cf 174 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 168:9672193075cf 175
AnnaBridge 168:9672193075cf 176 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 168:9672193075cf 177 /******************************************************************************/
AnnaBridge 168:9672193075cf 178 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 168:9672193075cf 179 /******************************************************************************/
AnnaBridge 168:9672193075cf 180 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 168:9672193075cf 181 {
AnnaBridge 168:9672193075cf 182 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 183 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 184
AnnaBridge 168:9672193075cf 185 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 186 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 187 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 188 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 189 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
AnnaBridge 168:9672193075cf 190
AnnaBridge 168:9672193075cf 191 // Enable HSI oscillator and activate PLL with HSI as source
AnnaBridge 168:9672193075cf 192 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 193 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 168:9672193075cf 194 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 182:a56a73fd2a6f 195 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 168:9672193075cf 196 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 197 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 168:9672193075cf 198 RCC_OscInitStruct.PLL.PLLM = 8;
AnnaBridge 168:9672193075cf 199 #if (CLOCK_SOURCE_USB)
AnnaBridge 168:9672193075cf 200 RCC_OscInitStruct.PLL.PLLN = 168;
AnnaBridge 168:9672193075cf 201 #else
AnnaBridge 168:9672193075cf 202 RCC_OscInitStruct.PLL.PLLN = 180;
AnnaBridge 168:9672193075cf 203 #endif
AnnaBridge 168:9672193075cf 204 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if CLOCK_SOURCE_USB defined
AnnaBridge 168:9672193075cf 205 RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if CLOCK_SOURCE_USB defined
AnnaBridge 168:9672193075cf 206 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 207 return 0; // FAIL
AnnaBridge 168:9672193075cf 208 }
AnnaBridge 168:9672193075cf 209
AnnaBridge 168:9672193075cf 210 // Activate the OverDrive to reach the 180 MHz Frequency
AnnaBridge 168:9672193075cf 211 if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
AnnaBridge 168:9672193075cf 212 return 0; // FAIL
AnnaBridge 168:9672193075cf 213 }
AnnaBridge 168:9672193075cf 214
AnnaBridge 168:9672193075cf 215 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 216 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 217 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
AnnaBridge 168:9672193075cf 218 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz
AnnaBridge 168:9672193075cf 219 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz
AnnaBridge 168:9672193075cf 220 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz
AnnaBridge 168:9672193075cf 221 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
AnnaBridge 168:9672193075cf 222 return 0; // FAIL
AnnaBridge 168:9672193075cf 223 }
AnnaBridge 168:9672193075cf 224
AnnaBridge 168:9672193075cf 225 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
AnnaBridge 168:9672193075cf 226
AnnaBridge 168:9672193075cf 227 return 1;
AnnaBridge 168:9672193075cf 228 }
AnnaBridge 168:9672193075cf 229 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */