mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c@187:0387e8f68319, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:40:20 2018 +0100
Revision:
187:0387e8f68319
Parent:
182:a56a73fd2a6f 
mbed-dev library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 168:9672193075cf 1 /* mbed Microcontroller Library
AnnaBridge 168:9672193075cf 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 168:9672193075cf 3 *
AnnaBridge 168:9672193075cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 168:9672193075cf 5 * you may not use this file except in compliance with the License.
AnnaBridge 168:9672193075cf 6 * You may obtain a copy of the License at
AnnaBridge 168:9672193075cf 7 *
AnnaBridge 168:9672193075cf 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 168:9672193075cf 9 *
AnnaBridge 168:9672193075cf 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 168:9672193075cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 168:9672193075cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 168:9672193075cf 13 * See the License for the specific language governing permissions and
AnnaBridge 168:9672193075cf 14 * limitations under the License.
AnnaBridge 168:9672193075cf 15 */
AnnaBridge 168:9672193075cf 16
AnnaBridge 168:9672193075cf 17 /**
AnnaBridge 168:9672193075cf 18 * This file configures the system clock as follows:
AnnaBridge 168:9672193075cf 19 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
AnnaBridge 168:9672193075cf 21 * | (external 8 MHz clock) | (internal 16 MHz)
AnnaBridge 168:9672193075cf 22 * | 2- PLL_HSE_XTAL |
AnnaBridge 168:9672193075cf 23 * | (external 8 MHz xtal) |
AnnaBridge 168:9672193075cf 24 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 25 * SYSCLK(MHz) | 96 | 96
AnnaBridge 168:9672193075cf 26 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 27 * AHBCLK (MHz) | 96 | 96
AnnaBridge 168:9672193075cf 28 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 29 * APB1CLK (MHz) | 48 | 48
AnnaBridge 168:9672193075cf 30 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 31 * APB2CLK (MHz) | 96 | 96
AnnaBridge 168:9672193075cf 32 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 33 * USB capable (48 MHz precise clock) | YES | YES
AnnaBridge 168:9672193075cf 34 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 35 **/
AnnaBridge 168:9672193075cf 36
AnnaBridge 168:9672193075cf 37 #include "stm32f4xx.h"
AnnaBridge 168:9672193075cf 38
AnnaBridge 168:9672193075cf 39
AnnaBridge 168:9672193075cf 40 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 168:9672193075cf 41 Internal SRAM. */
AnnaBridge 168:9672193075cf 42 /* #define VECT_TAB_SRAM */
AnnaBridge 168:9672193075cf 43 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
AnnaBridge 168:9672193075cf 44 This value must be a multiple of 0x200. */
AnnaBridge 168:9672193075cf 45
AnnaBridge 168:9672193075cf 46
AnnaBridge 168:9672193075cf 47 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
AnnaBridge 168:9672193075cf 48 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
AnnaBridge 168:9672193075cf 49 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
AnnaBridge 168:9672193075cf 50
AnnaBridge 168:9672193075cf 51
AnnaBridge 168:9672193075cf 52 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
AnnaBridge 168:9672193075cf 53 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 168:9672193075cf 54 #endif
AnnaBridge 168:9672193075cf 55
AnnaBridge 168:9672193075cf 56 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 168:9672193075cf 57
AnnaBridge 168:9672193075cf 58
AnnaBridge 168:9672193075cf 59 /**
AnnaBridge 168:9672193075cf 60 * @brief Setup the microcontroller system
AnnaBridge 168:9672193075cf 61 * Initialize the FPU setting, vector table location and External memory
AnnaBridge 168:9672193075cf 62 * configuration.
AnnaBridge 168:9672193075cf 63 * @param None
AnnaBridge 168:9672193075cf 64 * @retval None
AnnaBridge 168:9672193075cf 65 */
AnnaBridge 168:9672193075cf 66 void SystemInit(void)
AnnaBridge 168:9672193075cf 67 {
AnnaBridge 168:9672193075cf 68 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 168:9672193075cf 69 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 187:0387e8f68319 70 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
AnnaBridge 168:9672193075cf 71 #endif
AnnaBridge 168:9672193075cf 72 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 168:9672193075cf 73 /* Set HSION bit */
AnnaBridge 168:9672193075cf 74 RCC->CR |= (uint32_t)0x00000001;
AnnaBridge 168:9672193075cf 75
AnnaBridge 168:9672193075cf 76 /* Reset CFGR register */
AnnaBridge 168:9672193075cf 77 RCC->CFGR = 0x00000000;
AnnaBridge 168:9672193075cf 78
AnnaBridge 168:9672193075cf 79 /* Reset HSEON, CSSON and PLLON bits */
AnnaBridge 168:9672193075cf 80 RCC->CR &= (uint32_t)0xFEF6FFFF;
AnnaBridge 168:9672193075cf 81
AnnaBridge 168:9672193075cf 82 /* Reset PLLCFGR register */
AnnaBridge 168:9672193075cf 83 RCC->PLLCFGR = 0x24003010;
AnnaBridge 168:9672193075cf 84
AnnaBridge 168:9672193075cf 85 /* Reset HSEBYP bit */
AnnaBridge 168:9672193075cf 86 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 168:9672193075cf 87
AnnaBridge 168:9672193075cf 88 /* Disable all interrupts */
AnnaBridge 168:9672193075cf 89 RCC->CIR = 0x00000000;
AnnaBridge 168:9672193075cf 90
AnnaBridge 168:9672193075cf 91 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
AnnaBridge 168:9672193075cf 92 SystemInit_ExtMemCtl();
AnnaBridge 168:9672193075cf 93 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
AnnaBridge 168:9672193075cf 94
AnnaBridge 168:9672193075cf 95 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 168:9672193075cf 96 #ifdef VECT_TAB_SRAM
AnnaBridge 168:9672193075cf 97 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 168:9672193075cf 98 #else
AnnaBridge 168:9672193075cf 99 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 168:9672193075cf 100 #endif
AnnaBridge 168:9672193075cf 101
AnnaBridge 168:9672193075cf 102 }
AnnaBridge 168:9672193075cf 103
AnnaBridge 168:9672193075cf 104
AnnaBridge 168:9672193075cf 105 /**
AnnaBridge 168:9672193075cf 106 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 168:9672193075cf 107 * AHB/APBx prescalers and Flash settings
AnnaBridge 168:9672193075cf 108 * @note This function should be called only once the RCC clock configuration
AnnaBridge 168:9672193075cf 109 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 168:9672193075cf 110 * @param None
AnnaBridge 168:9672193075cf 111 * @retval None
AnnaBridge 168:9672193075cf 112 */
AnnaBridge 168:9672193075cf 113 void SetSysClock(void)
AnnaBridge 168:9672193075cf 114 {
AnnaBridge 168:9672193075cf 115 /* 1- Try to start with HSE and external clock */
AnnaBridge 168:9672193075cf 116 #if USE_PLL_HSE_EXTC != 0
AnnaBridge 168:9672193075cf 117 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 168:9672193075cf 118 #endif
AnnaBridge 168:9672193075cf 119 {
AnnaBridge 168:9672193075cf 120 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 168:9672193075cf 121 #if USE_PLL_HSE_XTAL != 0
AnnaBridge 168:9672193075cf 122 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 168:9672193075cf 123 #endif
AnnaBridge 168:9672193075cf 124 {
AnnaBridge 168:9672193075cf 125 /* 3- If fail start with HSI clock */
AnnaBridge 168:9672193075cf 126 if (SetSysClock_PLL_HSI() == 0) {
AnnaBridge 187:0387e8f68319 127 while (1) {
AnnaBridge 168:9672193075cf 128 // [TODO] Put something here to tell the user that a problem occured...
AnnaBridge 168:9672193075cf 129 }
AnnaBridge 168:9672193075cf 130 }
AnnaBridge 168:9672193075cf 131 }
AnnaBridge 168:9672193075cf 132 }
AnnaBridge 168:9672193075cf 133
AnnaBridge 168:9672193075cf 134 /* Output clock on MCO2 pin(PC9) for debugging purpose */
AnnaBridge 168:9672193075cf 135 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
AnnaBridge 168:9672193075cf 136 }
AnnaBridge 168:9672193075cf 137
AnnaBridge 168:9672193075cf 138 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
AnnaBridge 168:9672193075cf 139 /******************************************************************************/
AnnaBridge 168:9672193075cf 140 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 168:9672193075cf 141 /******************************************************************************/
AnnaBridge 168:9672193075cf 142 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 168:9672193075cf 143 {
AnnaBridge 168:9672193075cf 144 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 145 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 146
AnnaBridge 168:9672193075cf 147 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 148 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 149 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 150 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 151 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
AnnaBridge 168:9672193075cf 152
AnnaBridge 168:9672193075cf 153 /* Enable HSE oscillator and activate PLL with HSE as source */
AnnaBridge 168:9672193075cf 154 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 155 if (bypass == 0) {
AnnaBridge 168:9672193075cf 156 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
AnnaBridge 168:9672193075cf 157 } else {
AnnaBridge 168:9672193075cf 158 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
AnnaBridge 168:9672193075cf 159 }
AnnaBridge 168:9672193075cf 160 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 161 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 168:9672193075cf 162 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
AnnaBridge 168:9672193075cf 163 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
AnnaBridge 168:9672193075cf 164 //RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
AnnaBridge 168:9672193075cf 165 //RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
AnnaBridge 168:9672193075cf 166
AnnaBridge 168:9672193075cf 167 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 2 MHz (8 MHz / 4)
AnnaBridge 168:9672193075cf 168 RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (2 MHz * 192)
AnnaBridge 168:9672193075cf 169
AnnaBridge 168:9672193075cf 170
AnnaBridge 168:9672193075cf 171 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
AnnaBridge 168:9672193075cf 172 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
AnnaBridge 168:9672193075cf 173 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 174 return 0; // FAIL
AnnaBridge 168:9672193075cf 175 }
AnnaBridge 168:9672193075cf 176
AnnaBridge 168:9672193075cf 177 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 178 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 179 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
AnnaBridge 168:9672193075cf 180 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
AnnaBridge 168:9672193075cf 181 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
AnnaBridge 168:9672193075cf 182 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
AnnaBridge 168:9672193075cf 183 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
AnnaBridge 168:9672193075cf 184 return 0; // FAIL
AnnaBridge 168:9672193075cf 185 }
AnnaBridge 168:9672193075cf 186
AnnaBridge 168:9672193075cf 187 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 168:9672193075cf 188
AnnaBridge 168:9672193075cf 189 //if (bypass == 0)
AnnaBridge 168:9672193075cf 190 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
AnnaBridge 168:9672193075cf 191 //else
AnnaBridge 168:9672193075cf 192 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
AnnaBridge 168:9672193075cf 193
AnnaBridge 168:9672193075cf 194 return 1; // OK
AnnaBridge 168:9672193075cf 195 }
AnnaBridge 168:9672193075cf 196 #endif
AnnaBridge 168:9672193075cf 197
AnnaBridge 168:9672193075cf 198 /******************************************************************************/
AnnaBridge 168:9672193075cf 199 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 168:9672193075cf 200 /******************************************************************************/
AnnaBridge 168:9672193075cf 201 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 168:9672193075cf 202 {
AnnaBridge 168:9672193075cf 203 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 204 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 205
AnnaBridge 168:9672193075cf 206 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 207 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 208 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 209 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 210 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
AnnaBridge 168:9672193075cf 211
AnnaBridge 168:9672193075cf 212 /* Enable HSI oscillator and activate PLL with HSI as source */
AnnaBridge 168:9672193075cf 213 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 214 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 168:9672193075cf 215 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 182:a56a73fd2a6f 216 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 168:9672193075cf 217 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 218 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 168:9672193075cf 219 //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
AnnaBridge 168:9672193075cf 220 //RCC_OscInitStruct.PLL.PLLN = 384; // VCO output clock = 384 MHz (1 MHz * 384)
AnnaBridge 168:9672193075cf 221 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
AnnaBridge 168:9672193075cf 222 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 384 MHz (2 MHz * 192)
AnnaBridge 168:9672193075cf 223 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 96 MHz (384 MHz / 4)
AnnaBridge 168:9672193075cf 224 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 48 MHz (384 MHz / 8) --> Good for USB
AnnaBridge 168:9672193075cf 225 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 226 return 0; // FAIL
AnnaBridge 168:9672193075cf 227 }
AnnaBridge 168:9672193075cf 228
AnnaBridge 168:9672193075cf 229 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 230 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 231 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
AnnaBridge 168:9672193075cf 232 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
AnnaBridge 168:9672193075cf 233 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
AnnaBridge 168:9672193075cf 234 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
AnnaBridge 168:9672193075cf 235 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
AnnaBridge 168:9672193075cf 236 return 0; // FAIL
AnnaBridge 168:9672193075cf 237 }
AnnaBridge 168:9672193075cf 238
AnnaBridge 168:9672193075cf 239 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 168:9672193075cf 240 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 168:9672193075cf 241
AnnaBridge 168:9672193075cf 242 return 1; // OK
AnnaBridge 168:9672193075cf 243 }