mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h@187:0387e8f68319, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:40:20 2018 +0100
Revision:
187:0387e8f68319
Parent:
165:e614a9f1c9e2 
mbed-dev library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_flash_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of Flash HAL Extended module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F1xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F1xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup FLASHEx
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup FLASHEx_Private_Constants
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
AnnaBridge 165:e614a9f1c9e2 59 #define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
AnnaBridge 165:e614a9f1c9e2 60 #define OBR_REG_INDEX 1U
AnnaBridge 165:e614a9f1c9e2 61 #define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @}
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /** @addtogroup FLASHEx_Private_Macros
<> 144:ef7eb2e8f9f7 68 * @{
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
<> 144:ef7eb2e8f9f7 74
AnnaBridge 165:e614a9f1c9e2 75 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 88 #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
<> 144:ef7eb2e8f9f7 89 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* Low Density */
<> 144:ef7eb2e8f9f7 92 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
AnnaBridge 165:e614a9f1c9e2 93 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
AnnaBridge 165:e614a9f1c9e2 94 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
<> 144:ef7eb2e8f9f7 95 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Medium Density */
<> 144:ef7eb2e8f9f7 98 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
AnnaBridge 165:e614a9f1c9e2 99 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
AnnaBridge 165:e614a9f1c9e2 100 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
AnnaBridge 165:e614a9f1c9e2 101 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
AnnaBridge 165:e614a9f1c9e2 102 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
<> 144:ef7eb2e8f9f7 103 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* High Density */
<> 144:ef7eb2e8f9f7 106 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
AnnaBridge 165:e614a9f1c9e2 107 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
AnnaBridge 165:e614a9f1c9e2 108 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
AnnaBridge 165:e614a9f1c9e2 109 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
<> 144:ef7eb2e8f9f7 110 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* XL Density */
<> 144:ef7eb2e8f9f7 113 #if defined(FLASH_BANK2_END)
AnnaBridge 165:e614a9f1c9e2 114 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
AnnaBridge 165:e614a9f1c9e2 115 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
<> 144:ef7eb2e8f9f7 116 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Connectivity Line */
<> 144:ef7eb2e8f9f7 119 #if (defined(STM32F105xC) || defined(STM32F107xC))
AnnaBridge 165:e614a9f1c9e2 120 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
AnnaBridge 165:e614a9f1c9e2 121 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
AnnaBridge 165:e614a9f1c9e2 122 ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
<> 144:ef7eb2e8f9f7 123 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 124
AnnaBridge 165:e614a9f1c9e2 125 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 128 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
<> 144:ef7eb2e8f9f7 129 ((BANK) == FLASH_BANK_2) || \
<> 144:ef7eb2e8f9f7 130 ((BANK) == FLASH_BANK_BOTH))
<> 144:ef7eb2e8f9f7 131 #else
<> 144:ef7eb2e8f9f7 132 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
<> 144:ef7eb2e8f9f7 133 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* Low Density */
<> 144:ef7eb2e8f9f7 136 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
AnnaBridge 165:e614a9f1c9e2 137 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
AnnaBridge 165:e614a9f1c9e2 138 ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Medium Density */
<> 144:ef7eb2e8f9f7 143 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
AnnaBridge 165:e614a9f1c9e2 144 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
AnnaBridge 165:e614a9f1c9e2 145 ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
AnnaBridge 165:e614a9f1c9e2 146 ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
AnnaBridge 165:e614a9f1c9e2 147 ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* High Density */
<> 144:ef7eb2e8f9f7 152 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
AnnaBridge 165:e614a9f1c9e2 153 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
AnnaBridge 165:e614a9f1c9e2 154 ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
AnnaBridge 165:e614a9f1c9e2 155 ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* XL Density */
<> 144:ef7eb2e8f9f7 160 #if defined(FLASH_BANK2_END)
AnnaBridge 165:e614a9f1c9e2 161 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
AnnaBridge 165:e614a9f1c9e2 162 ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Connectivity Line */
<> 144:ef7eb2e8f9f7 167 #if (defined(STM32F105xC) || defined(STM32F107xC))
AnnaBridge 165:e614a9f1c9e2 168 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
AnnaBridge 165:e614a9f1c9e2 169 ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
AnnaBridge 165:e614a9f1c9e2 170 ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /**
<> 144:ef7eb2e8f9f7 175 * @}
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 179 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief FLASH Erase structure definition
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186 typedef struct
<> 144:ef7eb2e8f9f7 187 {
<> 144:ef7eb2e8f9f7 188 uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
<> 144:ef7eb2e8f9f7 189 This parameter can be a value of @ref FLASHEx_Type_Erase */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
<> 144:ef7eb2e8f9f7 192 This parameter must be a value of @ref FLASHEx_Banks */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
<> 144:ef7eb2e8f9f7 195 This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
<> 144:ef7eb2e8f9f7 196 (x = 1 or 2 depending on devices)*/
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
<> 144:ef7eb2e8f9f7 199 This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 } FLASH_EraseInitTypeDef;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @brief FLASH Options bytes program structure definition
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206 typedef struct
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
<> 144:ef7eb2e8f9f7 209 This parameter can be a value of @ref FLASHEx_OB_Type */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
<> 144:ef7eb2e8f9f7 212 This parameter can be a value of @ref FLASHEx_OB_WRP_State */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
<> 144:ef7eb2e8f9f7 215 This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
<> 144:ef7eb2e8f9f7 218 This parameter must be a value of @ref FLASHEx_Banks */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
<> 144:ef7eb2e8f9f7 221 This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 224 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
<> 144:ef7eb2e8f9f7 225 IWDG / STOP / STDBY / BOOT1
<> 144:ef7eb2e8f9f7 226 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
<> 144:ef7eb2e8f9f7 227 @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
<> 144:ef7eb2e8f9f7 228 #else
<> 144:ef7eb2e8f9f7 229 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
<> 144:ef7eb2e8f9f7 230 IWDG / STOP / STDBY
<> 144:ef7eb2e8f9f7 231 This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
<> 144:ef7eb2e8f9f7 232 @ref FLASHEx_OB_nRST_STDBY */
<> 144:ef7eb2e8f9f7 233 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
<> 144:ef7eb2e8f9f7 236 This parameter can be a value of @ref FLASHEx_OB_Data_Address */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
<> 144:ef7eb2e8f9f7 239 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 240 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 247 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /** @defgroup FLASHEx_Constants FLASH Constants
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup FLASHEx_Page_Size Page Size
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
AnnaBridge 165:e614a9f1c9e2 259 #define FLASH_PAGE_SIZE 0x400U
<> 144:ef7eb2e8f9f7 260 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 261 /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
AnnaBridge 165:e614a9f1c9e2 264 #define FLASH_PAGE_SIZE 0x800U
<> 144:ef7eb2e8f9f7 265 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 266 /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 267 /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @defgroup FLASHEx_Type_Erase Type Erase
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
AnnaBridge 165:e614a9f1c9e2 276 #define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
AnnaBridge 165:e614a9f1c9e2 277 #define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup FLASHEx_Banks Banks
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #if defined(FLASH_BANK2_END)
AnnaBridge 165:e614a9f1c9e2 287 #define FLASH_BANK_1 1U /*!< Bank 1 */
AnnaBridge 165:e614a9f1c9e2 288 #define FLASH_BANK_2 2U /*!< Bank 2 */
<> 144:ef7eb2e8f9f7 289 #define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 #else
AnnaBridge 165:e614a9f1c9e2 292 #define FLASH_BANK_1 1U /*!< Bank 1 */
<> 144:ef7eb2e8f9f7 293 #endif
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @}
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @}
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
<> 144:ef7eb2e8f9f7 303 * @{
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** @defgroup FLASHEx_OB_Type Option Bytes Type
<> 144:ef7eb2e8f9f7 307 * @{
<> 144:ef7eb2e8f9f7 308 */
AnnaBridge 165:e614a9f1c9e2 309 #define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/
AnnaBridge 165:e614a9f1c9e2 310 #define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/
AnnaBridge 165:e614a9f1c9e2 311 #define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/
AnnaBridge 165:e614a9f1c9e2 312 #define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
<> 144:ef7eb2e8f9f7 319 * @{
<> 144:ef7eb2e8f9f7 320 */
AnnaBridge 165:e614a9f1c9e2 321 #define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/
AnnaBridge 165:e614a9f1c9e2 322 #define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 /* STM32 Low and Medium density devices */
<> 144:ef7eb2e8f9f7 332 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
<> 144:ef7eb2e8f9f7 333 || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
<> 144:ef7eb2e8f9f7 334 || defined(STM32F103xB)
AnnaBridge 165:e614a9f1c9e2 335 #define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */
AnnaBridge 165:e614a9f1c9e2 336 #define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */
AnnaBridge 165:e614a9f1c9e2 337 #define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */
AnnaBridge 165:e614a9f1c9e2 338 #define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */
AnnaBridge 165:e614a9f1c9e2 339 #define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */
AnnaBridge 165:e614a9f1c9e2 340 #define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */
AnnaBridge 165:e614a9f1c9e2 341 #define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */
AnnaBridge 165:e614a9f1c9e2 342 #define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */
<> 144:ef7eb2e8f9f7 343 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 344 /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* STM32 Medium-density devices */
<> 144:ef7eb2e8f9f7 347 #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
AnnaBridge 165:e614a9f1c9e2 348 #define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */
AnnaBridge 165:e614a9f1c9e2 349 #define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */
AnnaBridge 165:e614a9f1c9e2 350 #define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */
AnnaBridge 165:e614a9f1c9e2 351 #define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */
AnnaBridge 165:e614a9f1c9e2 352 #define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */
AnnaBridge 165:e614a9f1c9e2 353 #define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */
AnnaBridge 165:e614a9f1c9e2 354 #define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */
AnnaBridge 165:e614a9f1c9e2 355 #define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */
AnnaBridge 165:e614a9f1c9e2 356 #define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */
AnnaBridge 165:e614a9f1c9e2 357 #define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */
AnnaBridge 165:e614a9f1c9e2 358 #define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */
AnnaBridge 165:e614a9f1c9e2 359 #define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */
AnnaBridge 165:e614a9f1c9e2 360 #define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */
AnnaBridge 165:e614a9f1c9e2 361 #define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */
AnnaBridge 165:e614a9f1c9e2 362 #define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */
AnnaBridge 165:e614a9f1c9e2 363 #define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */
AnnaBridge 165:e614a9f1c9e2 364 #define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */
AnnaBridge 165:e614a9f1c9e2 365 #define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */
AnnaBridge 165:e614a9f1c9e2 366 #define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */
AnnaBridge 165:e614a9f1c9e2 367 #define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */
AnnaBridge 165:e614a9f1c9e2 368 #define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */
AnnaBridge 165:e614a9f1c9e2 369 #define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */
AnnaBridge 165:e614a9f1c9e2 370 #define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */
AnnaBridge 165:e614a9f1c9e2 371 #define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
<> 144:ef7eb2e8f9f7 372 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* STM32 High-density, XL-density and Connectivity line devices */
<> 144:ef7eb2e8f9f7 376 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
<> 144:ef7eb2e8f9f7 377 || defined(STM32F101xG) || defined(STM32F103xG) \
<> 144:ef7eb2e8f9f7 378 || defined(STM32F105xC) || defined(STM32F107xC)
AnnaBridge 165:e614a9f1c9e2 379 #define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */
AnnaBridge 165:e614a9f1c9e2 380 #define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */
AnnaBridge 165:e614a9f1c9e2 381 #define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */
AnnaBridge 165:e614a9f1c9e2 382 #define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */
AnnaBridge 165:e614a9f1c9e2 383 #define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */
AnnaBridge 165:e614a9f1c9e2 384 #define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */
AnnaBridge 165:e614a9f1c9e2 385 #define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */
AnnaBridge 165:e614a9f1c9e2 386 #define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */
AnnaBridge 165:e614a9f1c9e2 387 #define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */
AnnaBridge 165:e614a9f1c9e2 388 #define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */
AnnaBridge 165:e614a9f1c9e2 389 #define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */
AnnaBridge 165:e614a9f1c9e2 390 #define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */
AnnaBridge 165:e614a9f1c9e2 391 #define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */
AnnaBridge 165:e614a9f1c9e2 392 #define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */
AnnaBridge 165:e614a9f1c9e2 393 #define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */
AnnaBridge 165:e614a9f1c9e2 394 #define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */
AnnaBridge 165:e614a9f1c9e2 395 #define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */
AnnaBridge 165:e614a9f1c9e2 396 #define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */
AnnaBridge 165:e614a9f1c9e2 397 #define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */
AnnaBridge 165:e614a9f1c9e2 398 #define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */
AnnaBridge 165:e614a9f1c9e2 399 #define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */
AnnaBridge 165:e614a9f1c9e2 400 #define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */
AnnaBridge 165:e614a9f1c9e2 401 #define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */
AnnaBridge 165:e614a9f1c9e2 402 #define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */
AnnaBridge 165:e614a9f1c9e2 403 #define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */
AnnaBridge 165:e614a9f1c9e2 404 #define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */
AnnaBridge 165:e614a9f1c9e2 405 #define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */
AnnaBridge 165:e614a9f1c9e2 406 #define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */
AnnaBridge 165:e614a9f1c9e2 407 #define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */
AnnaBridge 165:e614a9f1c9e2 408 #define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */
AnnaBridge 165:e614a9f1c9e2 409 #define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */
AnnaBridge 165:e614a9f1c9e2 410 #define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */
AnnaBridge 165:e614a9f1c9e2 411 #define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */
AnnaBridge 165:e614a9f1c9e2 412 #define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */
<> 144:ef7eb2e8f9f7 413 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
<> 144:ef7eb2e8f9f7 414 /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 415 /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 416
AnnaBridge 165:e614a9f1c9e2 417 #define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Low Density */
<> 144:ef7eb2e8f9f7 420 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
AnnaBridge 165:e614a9f1c9e2 421 #define OB_WRP_PAGES0TO31MASK 0x000000FFU
<> 144:ef7eb2e8f9f7 422 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Medium Density */
<> 144:ef7eb2e8f9f7 425 #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
AnnaBridge 165:e614a9f1c9e2 426 #define OB_WRP_PAGES0TO31MASK 0x000000FFU
AnnaBridge 165:e614a9f1c9e2 427 #define OB_WRP_PAGES32TO63MASK 0x0000FF00U
AnnaBridge 165:e614a9f1c9e2 428 #define OB_WRP_PAGES64TO95MASK 0x00FF0000U
AnnaBridge 165:e614a9f1c9e2 429 #define OB_WRP_PAGES96TO127MASK 0xFF000000U
<> 144:ef7eb2e8f9f7 430 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* High Density */
<> 144:ef7eb2e8f9f7 433 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
AnnaBridge 165:e614a9f1c9e2 434 #define OB_WRP_PAGES0TO15MASK 0x000000FFU
AnnaBridge 165:e614a9f1c9e2 435 #define OB_WRP_PAGES16TO31MASK 0x0000FF00U
AnnaBridge 165:e614a9f1c9e2 436 #define OB_WRP_PAGES32TO47MASK 0x00FF0000U
AnnaBridge 165:e614a9f1c9e2 437 #define OB_WRP_PAGES48TO255MASK 0xFF000000U
<> 144:ef7eb2e8f9f7 438 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* XL Density */
<> 144:ef7eb2e8f9f7 441 #if defined(STM32F101xG) || defined(STM32F103xG)
AnnaBridge 165:e614a9f1c9e2 442 #define OB_WRP_PAGES0TO15MASK 0x000000FFU
AnnaBridge 165:e614a9f1c9e2 443 #define OB_WRP_PAGES16TO31MASK 0x0000FF00U
AnnaBridge 165:e614a9f1c9e2 444 #define OB_WRP_PAGES32TO47MASK 0x00FF0000U
AnnaBridge 165:e614a9f1c9e2 445 #define OB_WRP_PAGES48TO511MASK 0xFF000000U
<> 144:ef7eb2e8f9f7 446 #endif /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Connectivity line devices */
<> 144:ef7eb2e8f9f7 449 #if defined(STM32F105xC) || defined(STM32F107xC)
AnnaBridge 165:e614a9f1c9e2 450 #define OB_WRP_PAGES0TO15MASK 0x000000FFU
AnnaBridge 165:e614a9f1c9e2 451 #define OB_WRP_PAGES16TO31MASK 0x0000FF00U
AnnaBridge 165:e614a9f1c9e2 452 #define OB_WRP_PAGES32TO47MASK 0x00FF0000U
AnnaBridge 165:e614a9f1c9e2 453 #define OB_WRP_PAGES48TO127MASK 0xFF000000U
<> 144:ef7eb2e8f9f7 454 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @}
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
<> 144:ef7eb2e8f9f7 461 * @{
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 #define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
<> 144:ef7eb2e8f9f7 464 #define OB_RDP_LEVEL_1 ((uint8_t)0x00)
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
<> 144:ef7eb2e8f9f7 470 * @{
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 #define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
<> 144:ef7eb2e8f9f7 473 #define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
<> 144:ef7eb2e8f9f7 474 /**
<> 144:ef7eb2e8f9f7 475 * @}
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
<> 144:ef7eb2e8f9f7 479 * @{
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 #define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 482 #define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 483 /**
<> 144:ef7eb2e8f9f7 484 * @}
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
<> 144:ef7eb2e8f9f7 488 * @{
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 #define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 491 #define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 497 /** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
<> 144:ef7eb2e8f9f7 498 * @{
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 #define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
<> 144:ef7eb2e8f9f7 501 #define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */
<> 144:ef7eb2e8f9f7 502 /**
<> 144:ef7eb2e8f9f7 503 * @}
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 #endif /* FLASH_BANK2_END */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
<> 144:ef7eb2e8f9f7 508 * @{
<> 144:ef7eb2e8f9f7 509 */
AnnaBridge 165:e614a9f1c9e2 510 #define OB_DATA_ADDRESS_DATA0 0x1FFFF804U
AnnaBridge 165:e614a9f1c9e2 511 #define OB_DATA_ADDRESS_DATA1 0x1FFFF806U
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @}
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /**
<> 144:ef7eb2e8f9f7 517 * @}
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /** @addtogroup FLASHEx_Constants
<> 144:ef7eb2e8f9f7 521 * @{
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /** @defgroup FLASH_Flag_definition Flag definition
<> 144:ef7eb2e8f9f7 525 * @brief Flag definition
<> 144:ef7eb2e8f9f7 526 * @{
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 529 #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */
<> 144:ef7eb2e8f9f7 530 #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */
<> 144:ef7eb2e8f9f7 531 #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */
<> 144:ef7eb2e8f9f7 532 #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */
<> 144:ef7eb2e8f9f7 535 #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */
<> 144:ef7eb2e8f9f7 536 #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
<> 144:ef7eb2e8f9f7 537 #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
<> 144:ef7eb2e8f9f7 538
AnnaBridge 165:e614a9f1c9e2 539 #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */
AnnaBridge 165:e614a9f1c9e2 540 #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */
AnnaBridge 165:e614a9f1c9e2 541 #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */
AnnaBridge 165:e614a9f1c9e2 542 #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 #else
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
<> 144:ef7eb2e8f9f7 547 #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
<> 144:ef7eb2e8f9f7 548 #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */
<> 144:ef7eb2e8f9f7 549 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 #endif
AnnaBridge 165:e614a9f1c9e2 552 #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
<> 144:ef7eb2e8f9f7 553 /**
<> 144:ef7eb2e8f9f7 554 * @}
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /** @defgroup FLASH_Interrupt_definition Interrupt definition
<> 144:ef7eb2e8f9f7 558 * @brief FLASH Interrupt definition
<> 144:ef7eb2e8f9f7 559 * @{
<> 144:ef7eb2e8f9f7 560 */
<> 144:ef7eb2e8f9f7 561 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 562 #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 563 #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 566 #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
<> 144:ef7eb2e8f9f7 567
AnnaBridge 165:e614a9f1c9e2 568 #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */
AnnaBridge 165:e614a9f1c9e2 569 #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #else
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
<> 144:ef7eb2e8f9f7 574 #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #endif
<> 144:ef7eb2e8f9f7 577 /**
<> 144:ef7eb2e8f9f7 578 * @}
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @}
<> 144:ef7eb2e8f9f7 583 */
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @}
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 591 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
<> 144:ef7eb2e8f9f7 592 * @{
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /** @defgroup FLASH_Interrupt Interrupt
<> 144:ef7eb2e8f9f7 596 * @brief macros to handle FLASH interrupts
<> 144:ef7eb2e8f9f7 597 * @{
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 #if defined(FLASH_BANK2_END)
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @brief Enable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 603 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 604 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 605 * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
<> 144:ef7eb2e8f9f7 606 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
<> 144:ef7eb2e8f9f7 607 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
<> 144:ef7eb2e8f9f7 608 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
<> 144:ef7eb2e8f9f7 609 * @retval none
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
<> 144:ef7eb2e8f9f7 612 /* Enable Bank1 IT */ \
AnnaBridge 165:e614a9f1c9e2 613 SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
<> 144:ef7eb2e8f9f7 614 /* Enable Bank2 IT */ \
AnnaBridge 165:e614a9f1c9e2 615 SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
AnnaBridge 165:e614a9f1c9e2 616 } while(0U)
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @brief Disable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 620 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 621 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 622 * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
<> 144:ef7eb2e8f9f7 623 * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
<> 144:ef7eb2e8f9f7 624 * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
<> 144:ef7eb2e8f9f7 625 * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
<> 144:ef7eb2e8f9f7 626 * @retval none
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
<> 144:ef7eb2e8f9f7 629 /* Disable Bank1 IT */ \
AnnaBridge 165:e614a9f1c9e2 630 CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
<> 144:ef7eb2e8f9f7 631 /* Disable Bank2 IT */ \
AnnaBridge 165:e614a9f1c9e2 632 CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
AnnaBridge 165:e614a9f1c9e2 633 } while(0U)
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /**
<> 144:ef7eb2e8f9f7 636 * @brief Get the specified FLASH flag status.
<> 144:ef7eb2e8f9f7 637 * @param __FLAG__ specifies the FLASH flag to check.
<> 144:ef7eb2e8f9f7 638 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 639 * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
<> 144:ef7eb2e8f9f7 640 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
<> 144:ef7eb2e8f9f7 641 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
<> 144:ef7eb2e8f9f7 642 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
<> 144:ef7eb2e8f9f7 643 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
<> 144:ef7eb2e8f9f7 644 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
<> 144:ef7eb2e8f9f7 645 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
<> 144:ef7eb2e8f9f7 646 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
<> 144:ef7eb2e8f9f7 647 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 648 * @retval The new state of __FLAG__ (SET or RESET).
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
<> 144:ef7eb2e8f9f7 651 (FLASH->OBR & FLASH_OBR_OPTERR) : \
<> 144:ef7eb2e8f9f7 652 ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
<> 144:ef7eb2e8f9f7 653 (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
AnnaBridge 165:e614a9f1c9e2 654 (FLASH->SR2 & ((__FLAG__) >> 16U))))
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /**
<> 144:ef7eb2e8f9f7 657 * @brief Clear the specified FLASH flag.
<> 144:ef7eb2e8f9f7 658 * @param __FLAG__ specifies the FLASH flags to clear.
<> 144:ef7eb2e8f9f7 659 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 660 * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
<> 144:ef7eb2e8f9f7 661 * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
<> 144:ef7eb2e8f9f7 662 * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
<> 144:ef7eb2e8f9f7 663 * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
<> 144:ef7eb2e8f9f7 664 * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
<> 144:ef7eb2e8f9f7 665 * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
<> 144:ef7eb2e8f9f7 666 * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
<> 144:ef7eb2e8f9f7 667 * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
<> 144:ef7eb2e8f9f7 668 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 669 * @retval none
<> 144:ef7eb2e8f9f7 670 */
<> 144:ef7eb2e8f9f7 671 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
<> 144:ef7eb2e8f9f7 672 /* Clear FLASH_FLAG_OPTVERR flag */ \
<> 144:ef7eb2e8f9f7 673 if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
<> 144:ef7eb2e8f9f7 674 { \
<> 144:ef7eb2e8f9f7 675 CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
<> 144:ef7eb2e8f9f7 676 } \
<> 144:ef7eb2e8f9f7 677 else { \
<> 144:ef7eb2e8f9f7 678 /* Clear Flag in Bank1 */ \
<> 144:ef7eb2e8f9f7 679 if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
<> 144:ef7eb2e8f9f7 680 { \
<> 144:ef7eb2e8f9f7 681 FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
<> 144:ef7eb2e8f9f7 682 } \
<> 144:ef7eb2e8f9f7 683 /* Clear Flag in Bank2 */ \
AnnaBridge 165:e614a9f1c9e2 684 if (((__FLAG__) >> 16U) != RESET) \
<> 144:ef7eb2e8f9f7 685 { \
AnnaBridge 165:e614a9f1c9e2 686 FLASH->SR2 = ((__FLAG__) >> 16U); \
<> 144:ef7eb2e8f9f7 687 } \
<> 144:ef7eb2e8f9f7 688 } \
AnnaBridge 165:e614a9f1c9e2 689 } while(0U)
<> 144:ef7eb2e8f9f7 690 #else
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @brief Enable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 693 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 694 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 695 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
<> 144:ef7eb2e8f9f7 696 * @arg @ref FLASH_IT_ERR Error Interrupt
<> 144:ef7eb2e8f9f7 697 * @retval none
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @brief Disable the specified FLASH interrupt.
<> 144:ef7eb2e8f9f7 703 * @param __INTERRUPT__ FLASH interrupt
<> 144:ef7eb2e8f9f7 704 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 705 * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
<> 144:ef7eb2e8f9f7 706 * @arg @ref FLASH_IT_ERR Error Interrupt
<> 144:ef7eb2e8f9f7 707 * @retval none
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /**
<> 144:ef7eb2e8f9f7 712 * @brief Get the specified FLASH flag status.
<> 144:ef7eb2e8f9f7 713 * @param __FLAG__ specifies the FLASH flag to check.
<> 144:ef7eb2e8f9f7 714 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 715 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
<> 144:ef7eb2e8f9f7 716 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
<> 144:ef7eb2e8f9f7 717 * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
<> 144:ef7eb2e8f9f7 718 * @arg @ref FLASH_FLAG_BSY FLASH Busy flag
<> 144:ef7eb2e8f9f7 719 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 720 * @retval The new state of __FLAG__ (SET or RESET).
<> 144:ef7eb2e8f9f7 721 */
<> 144:ef7eb2e8f9f7 722 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
<> 144:ef7eb2e8f9f7 723 (FLASH->OBR & FLASH_OBR_OPTERR) : \
<> 144:ef7eb2e8f9f7 724 (FLASH->SR & (__FLAG__)))
<> 144:ef7eb2e8f9f7 725 /**
<> 144:ef7eb2e8f9f7 726 * @brief Clear the specified FLASH flag.
<> 144:ef7eb2e8f9f7 727 * @param __FLAG__ specifies the FLASH flags to clear.
<> 144:ef7eb2e8f9f7 728 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 729 * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
<> 144:ef7eb2e8f9f7 730 * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
<> 144:ef7eb2e8f9f7 731 * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
<> 144:ef7eb2e8f9f7 732 * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
<> 144:ef7eb2e8f9f7 733 * @retval none
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
<> 144:ef7eb2e8f9f7 736 /* Clear FLASH_FLAG_OPTVERR flag */ \
<> 144:ef7eb2e8f9f7 737 if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
<> 144:ef7eb2e8f9f7 738 { \
<> 144:ef7eb2e8f9f7 739 CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
<> 144:ef7eb2e8f9f7 740 } \
<> 144:ef7eb2e8f9f7 741 else { \
<> 144:ef7eb2e8f9f7 742 /* Clear Flag in Bank1 */ \
<> 144:ef7eb2e8f9f7 743 FLASH->SR = (__FLAG__); \
<> 144:ef7eb2e8f9f7 744 } \
AnnaBridge 165:e614a9f1c9e2 745 } while(0U)
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 #endif
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /**
<> 144:ef7eb2e8f9f7 750 * @}
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /**
<> 144:ef7eb2e8f9f7 754 * @}
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 758 /** @addtogroup FLASHEx_Exported_Functions
<> 144:ef7eb2e8f9f7 759 * @{
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 763 * @{
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 766 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
<> 144:ef7eb2e8f9f7 767 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @}
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /** @addtogroup FLASHEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 774 * @{
<> 144:ef7eb2e8f9f7 775 */
<> 144:ef7eb2e8f9f7 776 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 777 HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
<> 144:ef7eb2e8f9f7 778 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 779 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 780 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
<> 144:ef7eb2e8f9f7 781 /**
<> 144:ef7eb2e8f9f7 782 * @}
<> 144:ef7eb2e8f9f7 783 */
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /**
<> 144:ef7eb2e8f9f7 786 * @}
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /**
<> 144:ef7eb2e8f9f7 790 * @}
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /**
<> 144:ef7eb2e8f9f7 794 * @}
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798 #endif
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 #endif /* __STM32F1xx_HAL_FLASH_EX_H */
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/