mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_NUC472/mbed_overrides.c@187:0387e8f68319, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:40:20 2018 +0100
Revision:
187:0387e8f68319
Parent:
targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbed_overrides.c@172:7d866c31b3c5 
mbed-dev library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015-2016 Nuvoton
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18 #include "analogin_api.h"
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 void mbed_sdk_init(void)
<> 144:ef7eb2e8f9f7 21 {
<> 144:ef7eb2e8f9f7 22 // NOTE: Support singleton semantics to be called from other init functions
<> 144:ef7eb2e8f9f7 23 static int inited = 0;
<> 144:ef7eb2e8f9f7 24 if (inited) {
<> 144:ef7eb2e8f9f7 25 return;
<> 144:ef7eb2e8f9f7 26 }
<> 144:ef7eb2e8f9f7 27 inited = 1;
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 30 /* Init System Clock */
<> 144:ef7eb2e8f9f7 31 /*---------------------------------------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 32 /* Unlock protected registers */
<> 144:ef7eb2e8f9f7 33 SYS_UnlockReg();
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 /* Enable External XTAL (4~24 MHz) */
<> 144:ef7eb2e8f9f7 36 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
<> 144:ef7eb2e8f9f7 37 /* Enable LIRC for lp_ticker */
<> 144:ef7eb2e8f9f7 38 CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
<> 144:ef7eb2e8f9f7 39 /* Enable LXT for RTC */
<> 144:ef7eb2e8f9f7 40 CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Waiting for External XTAL (4~24 MHz) ready */
<> 144:ef7eb2e8f9f7 43 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
<> 144:ef7eb2e8f9f7 44 /* Waiting for LIRC ready */
<> 144:ef7eb2e8f9f7 45 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
<> 144:ef7eb2e8f9f7 46 /* Waiting for LXT ready */
<> 144:ef7eb2e8f9f7 47 CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Switch HCLK clock source to HXT */
<> 144:ef7eb2e8f9f7 50 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /* Set PLL to power down mode and PLLSTB bit in CLKSTATUS register will be cleared by hardware.*/
<> 144:ef7eb2e8f9f7 53 CLK->PLLCTL|= CLK_PLLCTL_PD_Msk;
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Set PLL frequency */
<> 144:ef7eb2e8f9f7 56 CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Waiting for clock ready */
<> 144:ef7eb2e8f9f7 59 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Switch HCLK clock source to PLL */
<> 144:ef7eb2e8f9f7 62 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* Enable IP clock */
<> 144:ef7eb2e8f9f7 65 //CLK_EnableModuleClock(UART0_MODULE);
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /* Select IP clock source */
<> 144:ef7eb2e8f9f7 68 //CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_HXT,CLK_CLKDIV0_UART(1));
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 #if DEVICE_ANALOGIN
<> 144:ef7eb2e8f9f7 71 /* Vref connect to AVDD */
<> 144:ef7eb2e8f9f7 72 SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
<> 153:fa9ff456f731 73 /* Switch ADC0 to EADC mode */
<> 153:fa9ff456f731 74 SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_ADCMODESEL_Msk) | SYS_VREFCTL_ADCMODESEL_EADC;
<> 144:ef7eb2e8f9f7 75 #endif
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* Update System Core Clock */
<> 144:ef7eb2e8f9f7 78 /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
<> 144:ef7eb2e8f9f7 79 SystemCoreClockUpdate();
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* Lock protected registers */
<> 144:ef7eb2e8f9f7 82 SYS_LockReg();
<> 144:ef7eb2e8f9f7 83 }