mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Maxim/TARGET_MAX32625/device/spis_regs.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_SPIS_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_SPIS_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t gen_ctrl; /* 0x0000 SPI Slave General Control Register */
<> 150:02e0a0aed4ec 66 __IO uint32_t fifo_ctrl; /* 0x0004 SPI Slave FIFO Control Register */
<> 150:02e0a0aed4ec 67 __IO uint32_t fifo_stat; /* 0x0008 SPI Slave FIFO Status Register */
<> 150:02e0a0aed4ec 68 __IO uint32_t intfl; /* 0x000C SPI Slave Interrupt Flags */
<> 150:02e0a0aed4ec 69 __IO uint32_t inten; /* 0x0010 SPI Slave Interrupt Enable/Disable Settings */
<> 150:02e0a0aed4ec 70 } mxc_spis_regs_t;
<> 150:02e0a0aed4ec 71
<> 150:02e0a0aed4ec 72
<> 150:02e0a0aed4ec 73 /* Offset Register Description
<> 150:02e0a0aed4ec 74 ============= ============================================================================ */
<> 150:02e0a0aed4ec 75 typedef struct {
<> 150:02e0a0aed4ec 76 union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */
<> 150:02e0a0aed4ec 77 __IO uint8_t tx_8[2048];
<> 150:02e0a0aed4ec 78 __IO uint16_t tx_16[1024];
<> 150:02e0a0aed4ec 79 __IO uint32_t tx_32[512];
<> 150:02e0a0aed4ec 80 };
<> 150:02e0a0aed4ec 81 union { /* 0x0800-0x0FFC FIFO Read Space for Results Data */
<> 150:02e0a0aed4ec 82 __IO uint8_t rx_8[2048];
<> 150:02e0a0aed4ec 83 __IO uint16_t rx_16[1024];
<> 150:02e0a0aed4ec 84 __IO uint32_t rx_32[512];
<> 150:02e0a0aed4ec 85 };
<> 150:02e0a0aed4ec 86 } mxc_spis_fifo_regs_t;
<> 150:02e0a0aed4ec 87
<> 150:02e0a0aed4ec 88
<> 150:02e0a0aed4ec 89 /*
<> 150:02e0a0aed4ec 90 Register offsets for module SPIS.
<> 150:02e0a0aed4ec 91 */
<> 150:02e0a0aed4ec 92
<> 150:02e0a0aed4ec 93 #define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 94 #define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 95 #define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 96 #define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 97 #define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 98 #define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 99 #define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
<> 150:02e0a0aed4ec 100
<> 150:02e0a0aed4ec 101
<> 150:02e0a0aed4ec 102 /*
<> 150:02e0a0aed4ec 103 Field positions and masks for module SPIS.
<> 150:02e0a0aed4ec 104 */
<> 150:02e0a0aed4ec 105
<> 150:02e0a0aed4ec 106 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0
<> 150:02e0a0aed4ec 107 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS))
<> 150:02e0a0aed4ec 108 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1
<> 150:02e0a0aed4ec 109 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 110 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2
<> 150:02e0a0aed4ec 111 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 112 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4
<> 150:02e0a0aed4ec 113 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS))
<> 150:02e0a0aed4ec 114 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16
<> 150:02e0a0aed4ec 115 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS))
<> 150:02e0a0aed4ec 116 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20
<> 150:02e0a0aed4ec 117 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS))
<> 150:02e0a0aed4ec 118
<> 150:02e0a0aed4ec 119 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
<> 150:02e0a0aed4ec 120 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
<> 150:02e0a0aed4ec 121 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8
<> 150:02e0a0aed4ec 122 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
<> 150:02e0a0aed4ec 123
<> 150:02e0a0aed4ec 124 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0
<> 150:02e0a0aed4ec 125 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS))
<> 150:02e0a0aed4ec 126 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8
<> 150:02e0a0aed4ec 127 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS))
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129 #define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0
<> 150:02e0a0aed4ec 130 #define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS))
<> 150:02e0a0aed4ec 131 #define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1
<> 150:02e0a0aed4ec 132 #define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS))
<> 150:02e0a0aed4ec 133 #define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2
<> 150:02e0a0aed4ec 134 #define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS))
<> 150:02e0a0aed4ec 135 #define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3
<> 150:02e0a0aed4ec 136 #define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS))
<> 150:02e0a0aed4ec 137 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4
<> 150:02e0a0aed4ec 138 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS))
<> 150:02e0a0aed4ec 139 #define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5
<> 150:02e0a0aed4ec 140 #define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS))
<> 150:02e0a0aed4ec 141 #define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6
<> 150:02e0a0aed4ec 142 #define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS))
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144 #define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0
<> 150:02e0a0aed4ec 145 #define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS))
<> 150:02e0a0aed4ec 146 #define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1
<> 150:02e0a0aed4ec 147 #define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS))
<> 150:02e0a0aed4ec 148 #define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2
<> 150:02e0a0aed4ec 149 #define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS))
<> 150:02e0a0aed4ec 150 #define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3
<> 150:02e0a0aed4ec 151 #define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS))
<> 150:02e0a0aed4ec 152 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4
<> 150:02e0a0aed4ec 153 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS))
<> 150:02e0a0aed4ec 154 #define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5
<> 150:02e0a0aed4ec 155 #define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS))
<> 150:02e0a0aed4ec 156 #define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6
<> 150:02e0a0aed4ec 157 #define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS))
<> 150:02e0a0aed4ec 158
<> 150:02e0a0aed4ec 159
<> 150:02e0a0aed4ec 160 #ifdef __cplusplus
<> 150:02e0a0aed4ec 161 }
<> 150:02e0a0aed4ec 162 #endif
<> 150:02e0a0aed4ec 163
<> 150:02e0a0aed4ec 164 #endif /* _MXC_SPIS_REGS_H_ */
<> 150:02e0a0aed4ec 165