Maxim Ibragimov / mbed-dev

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Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

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targets/TARGET_NXP/TARGET_LPC11XX_11CXX/sleep.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
160:d5399cc887bb 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18 #include "mbed_interface.h"
<> 144:ef7eb2e8f9f7 19
<> 160:d5399cc887bb 20 void hal_sleep(void) {
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 // PCON[DPDEN] set to sleep
<> 144:ef7eb2e8f9f7 23 LPC_PMU->PCON = 0x0;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 // SRC[SLEEPDEEP] set to 0 = sleep
<> 144:ef7eb2e8f9f7 26 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 // wait for interrupt
<> 144:ef7eb2e8f9f7 29 __WFI();
<> 144:ef7eb2e8f9f7 30 }
<> 144:ef7eb2e8f9f7 31
<> 160:d5399cc887bb 32 void hal_deepsleep(void) {
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 // PCON[DPDEN] set to deepsleep
<> 144:ef7eb2e8f9f7 35 LPC_PMU->PCON = 0;
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 // SRC[SLEEPDEEP] set to 1 = deep sleep
<> 144:ef7eb2e8f9f7 38 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 //According to user manual it is kinda picky about reserved bits, so we follow that nicely
<> 144:ef7eb2e8f9f7 41 //Keep WDOSC and BOD in same state as they are now during deepsleep
<> 144:ef7eb2e8f9f7 42 LPC_SYSCON->PDSLEEPCFG = 0x000018B7 | (LPC_SYSCON->PDRUNCFG & (PDRUNCFG_WDTOSC_PD | PDRUNCFG_BOD_PD));
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 // Power up same as before powerdown
<> 144:ef7eb2e8f9f7 45 LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 // wait for interrupt
<> 144:ef7eb2e8f9f7 48 __WFI();
<> 144:ef7eb2e8f9f7 49 }