Maxim Ibragimov / mbed-dev

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Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

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targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
165:e614a9f1c9e2 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /*******************************************************************************
<> 157:ff67d9f36b67 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 3 *
<> 157:ff67d9f36b67 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 5 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 6 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 9 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 10 *
<> 157:ff67d9f36b67 11 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 12 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 13 *
<> 157:ff67d9f36b67 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 21 *
<> 157:ff67d9f36b67 22 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 24 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 28 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 30 * ownership rights.
<> 157:ff67d9f36b67 31 *******************************************************************************
<> 157:ff67d9f36b67 32 */
<> 157:ff67d9f36b67 33
<> 157:ff67d9f36b67 34 #include <stddef.h>
<> 157:ff67d9f36b67 35 #include "cmsis.h"
<> 157:ff67d9f36b67 36 #include "gpio_irq_api.h"
<> 157:ff67d9f36b67 37 #include "mbed_error.h"
<> 157:ff67d9f36b67 38
<> 157:ff67d9f36b67 39 static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}};
<> 157:ff67d9f36b67 40 static gpio_irq_handler irq_handler;
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 static void handle_irq(unsigned int port)
<> 157:ff67d9f36b67 43 {
<> 157:ff67d9f36b67 44 uint32_t intfl, in_val;
<> 157:ff67d9f36b67 45 uint32_t mask;
<> 157:ff67d9f36b67 46 unsigned int pin;
<> 157:ff67d9f36b67 47
<> 157:ff67d9f36b67 48 /* Read pin state */
<> 157:ff67d9f36b67 49 in_val = MXC_GPIO->in_val[port];
<> 157:ff67d9f36b67 50
<> 157:ff67d9f36b67 51 /* Read interrupts */
<> 157:ff67d9f36b67 52 intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54 mask = 1;
<> 157:ff67d9f36b67 55
<> 157:ff67d9f36b67 56 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
<> 157:ff67d9f36b67 57 if (intfl & mask) {
<> 157:ff67d9f36b67 58 MXC_GPIO->intfl[port] = mask; /* clear interrupt */
<> 157:ff67d9f36b67 59 gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL;
<> 157:ff67d9f36b67 60 gpio_irq_t *obj = objs[port][pin];
<> 157:ff67d9f36b67 61 if (obj && obj->id) {
<> 157:ff67d9f36b67 62 if ((event == IRQ_RISE) && obj->rise_en) {
<> 157:ff67d9f36b67 63 irq_handler(obj->id, IRQ_RISE);
<> 157:ff67d9f36b67 64 } else if ((event == IRQ_FALL) && obj->fall_en) {
<> 157:ff67d9f36b67 65 irq_handler(obj->id, IRQ_FALL);
<> 157:ff67d9f36b67 66 }
<> 157:ff67d9f36b67 67 }
<> 157:ff67d9f36b67 68 }
<> 157:ff67d9f36b67 69 mask <<= 1;
<> 157:ff67d9f36b67 70 }
<> 157:ff67d9f36b67 71 }
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73 void gpio_irq_0(void) { handle_irq(0); }
<> 157:ff67d9f36b67 74 void gpio_irq_1(void) { handle_irq(1); }
<> 157:ff67d9f36b67 75 void gpio_irq_2(void) { handle_irq(2); }
<> 157:ff67d9f36b67 76 void gpio_irq_3(void) { handle_irq(3); }
<> 157:ff67d9f36b67 77 void gpio_irq_4(void) { handle_irq(4); }
<> 157:ff67d9f36b67 78 void gpio_irq_5(void) { handle_irq(5); }
<> 157:ff67d9f36b67 79 void gpio_irq_6(void) { handle_irq(6); }
<> 157:ff67d9f36b67 80 void gpio_irq_7(void) { handle_irq(7); }
<> 157:ff67d9f36b67 81 void gpio_irq_8(void) { handle_irq(8); }
<> 157:ff67d9f36b67 82
<> 157:ff67d9f36b67 83 int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
<> 157:ff67d9f36b67 84 {
<> 157:ff67d9f36b67 85 if (name == NC) {
<> 157:ff67d9f36b67 86 return -1;
<> 157:ff67d9f36b67 87 }
<> 157:ff67d9f36b67 88
<> 157:ff67d9f36b67 89 uint8_t port = PINNAME_TO_PORT(name);
<> 157:ff67d9f36b67 90 uint8_t pin = PINNAME_TO_PIN(name);
<> 157:ff67d9f36b67 91
<> 157:ff67d9f36b67 92 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
<> 157:ff67d9f36b67 93 return 1;
<> 157:ff67d9f36b67 94 }
<> 157:ff67d9f36b67 95
<> 157:ff67d9f36b67 96 obj->port = port;
<> 157:ff67d9f36b67 97 obj->pin = pin;
<> 157:ff67d9f36b67 98 obj->id = id;
<> 157:ff67d9f36b67 99 objs[port][pin] = obj;
<> 157:ff67d9f36b67 100
<> 157:ff67d9f36b67 101 /* register handlers */
<> 157:ff67d9f36b67 102 irq_handler = handler;
AnnaBridge 165:e614a9f1c9e2 103 NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
AnnaBridge 165:e614a9f1c9e2 104 NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
AnnaBridge 165:e614a9f1c9e2 105 NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
AnnaBridge 165:e614a9f1c9e2 106 NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
AnnaBridge 165:e614a9f1c9e2 107 NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
AnnaBridge 165:e614a9f1c9e2 108 NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
AnnaBridge 165:e614a9f1c9e2 109 NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
AnnaBridge 165:e614a9f1c9e2 110 NVIC_SetVector(GPIO_P7_IRQn, (uint32_t)gpio_irq_7);
AnnaBridge 165:e614a9f1c9e2 111 NVIC_SetVector(GPIO_P8_IRQn, (uint32_t)gpio_irq_8);
<> 157:ff67d9f36b67 112
<> 157:ff67d9f36b67 113 /* disable the interrupt locally */
<> 157:ff67d9f36b67 114 MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
<> 157:ff67d9f36b67 115
<> 157:ff67d9f36b67 116 /* clear a pending request */
<> 157:ff67d9f36b67 117 MXC_GPIO->intfl[port] = 1 << pin;
<> 157:ff67d9f36b67 118
<> 157:ff67d9f36b67 119 /* enable the requested interrupt */
<> 157:ff67d9f36b67 120 MXC_GPIO->inten[port] |= (1 << pin);
<> 157:ff67d9f36b67 121 NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
<> 157:ff67d9f36b67 122
<> 157:ff67d9f36b67 123 return 0;
<> 157:ff67d9f36b67 124 }
<> 157:ff67d9f36b67 125
<> 157:ff67d9f36b67 126 void gpio_irq_free(gpio_irq_t *obj)
<> 157:ff67d9f36b67 127 {
<> 157:ff67d9f36b67 128 /* disable interrupt */
<> 157:ff67d9f36b67 129 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 157:ff67d9f36b67 130 MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 157:ff67d9f36b67 131 objs[obj->port][obj->pin] = NULL;
<> 157:ff67d9f36b67 132 }
<> 157:ff67d9f36b67 133
<> 157:ff67d9f36b67 134 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 157:ff67d9f36b67 135 {
<> 157:ff67d9f36b67 136 if (event == IRQ_FALL) {
<> 157:ff67d9f36b67 137 obj->fall_en = enable;
<> 157:ff67d9f36b67 138 } else if (event == IRQ_RISE) {
<> 157:ff67d9f36b67 139 obj->rise_en = enable;
<> 157:ff67d9f36b67 140 }
<> 157:ff67d9f36b67 141
<> 157:ff67d9f36b67 142 if (obj->fall_en && obj->rise_en) {
<> 157:ff67d9f36b67 143 MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 157:ff67d9f36b67 144 } else if (obj->fall_en) {
<> 157:ff67d9f36b67 145 uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
<> 157:ff67d9f36b67 146 int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 157:ff67d9f36b67 147 int_mode |= (MXC_V_GPIO_INT_MODE_FALLING_EDGE << (obj->pin*4));
<> 157:ff67d9f36b67 148 MXC_GPIO->int_mode[obj->port] = int_mode;
<> 157:ff67d9f36b67 149 } else if (obj->rise_en) {
<> 157:ff67d9f36b67 150 uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
<> 157:ff67d9f36b67 151 int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 157:ff67d9f36b67 152 int_mode |= (MXC_V_GPIO_INT_MODE_RISING_EDGE << (obj->pin*4));
<> 157:ff67d9f36b67 153 MXC_GPIO->int_mode[obj->port] = int_mode;
<> 157:ff67d9f36b67 154 } else {
<> 157:ff67d9f36b67 155 MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
<> 157:ff67d9f36b67 156 }
<> 157:ff67d9f36b67 157 }
<> 157:ff67d9f36b67 158
<> 157:ff67d9f36b67 159 void gpio_irq_enable(gpio_irq_t *obj)
<> 157:ff67d9f36b67 160 {
<> 157:ff67d9f36b67 161 MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
<> 157:ff67d9f36b67 162 }
<> 157:ff67d9f36b67 163
<> 157:ff67d9f36b67 164 void gpio_irq_disable(gpio_irq_t *obj)
<> 157:ff67d9f36b67 165 {
<> 157:ff67d9f36b67 166 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 157:ff67d9f36b67 167 }
<> 157:ff67d9f36b67 168
<> 157:ff67d9f36b67 169 gpio_irq_t *gpio_irq_get_obj(PinName name)
<> 157:ff67d9f36b67 170 {
<> 157:ff67d9f36b67 171 if (name == NC) {
<> 157:ff67d9f36b67 172 return NULL;
<> 157:ff67d9f36b67 173 }
<> 157:ff67d9f36b67 174
<> 157:ff67d9f36b67 175 unsigned int port = PINNAME_TO_PORT(name);
<> 157:ff67d9f36b67 176 unsigned int pin = PINNAME_TO_PIN(name);
<> 157:ff67d9f36b67 177
<> 157:ff67d9f36b67 178 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
<> 157:ff67d9f36b67 179 return NULL;
<> 157:ff67d9f36b67 180 }
<> 157:ff67d9f36b67 181
<> 157:ff67d9f36b67 182 return objs[port][pin];
<> 157:ff67d9f36b67 183 }