marcus chiou
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mbed-src
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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_acmp.h@636:cb7d56e6ff53, 2015-10-27 (annotated)
- Committer:
- marcusC
- Date:
- Tue Oct 27 07:54:54 2015 +0000
- Revision:
- 636:cb7d56e6ff53
- Parent:
- 525:c320967f86b9
Changed for DELTA_DFCM_NNN40; Do not initialize flash at mbed_sdk_init()
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 525:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 2 | * @file efm32hg_acmp.h |
| mbed_official | 525:c320967f86b9 | 3 | * @brief EFM32HG_ACMP register and bit field definitions |
| mbed_official | 525:c320967f86b9 | 4 | * @version 3.20.12 |
| mbed_official | 525:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 6 | * @section License |
| mbed_official | 525:c320967f86b9 | 7 | * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 525:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 9 | * |
| mbed_official | 525:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 525:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 525:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 525:c320967f86b9 | 13 | * |
| mbed_official | 525:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 525:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 525:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 525:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 525:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 525:c320967f86b9 | 19 | * |
| mbed_official | 525:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 525:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 525:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 525:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 525:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 525:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 525:c320967f86b9 | 26 | * |
| mbed_official | 525:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 525:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 525:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 525:c320967f86b9 | 30 | * |
| mbed_official | 525:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 33 | * @defgroup EFM32HG_ACMP |
| mbed_official | 525:c320967f86b9 | 34 | * @{ |
| mbed_official | 525:c320967f86b9 | 35 | * @brief EFM32HG_ACMP Register Declaration |
| mbed_official | 525:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 37 | typedef struct |
| mbed_official | 525:c320967f86b9 | 38 | { |
| mbed_official | 525:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 525:c320967f86b9 | 40 | __IO uint32_t INPUTSEL; /**< Input Selection Register */ |
| mbed_official | 525:c320967f86b9 | 41 | __I uint32_t STATUS; /**< Status Register */ |
| mbed_official | 525:c320967f86b9 | 42 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 525:c320967f86b9 | 43 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 525:c320967f86b9 | 44 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 525:c320967f86b9 | 45 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 525:c320967f86b9 | 46 | __IO uint32_t ROUTE; /**< I/O Routing Register */ |
| mbed_official | 525:c320967f86b9 | 47 | } ACMP_TypeDef; /** @} */ |
| mbed_official | 525:c320967f86b9 | 48 | |
| mbed_official | 525:c320967f86b9 | 49 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 50 | * @defgroup EFM32HG_ACMP_BitFields |
| mbed_official | 525:c320967f86b9 | 51 | * @{ |
| mbed_official | 525:c320967f86b9 | 52 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 53 | |
| mbed_official | 525:c320967f86b9 | 54 | /* Bit fields for ACMP CTRL */ |
| mbed_official | 525:c320967f86b9 | 55 | #define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 56 | #define _ACMP_CTRL_MASK 0xCF03077FUL /**< Mask for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 57 | #define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */ |
| mbed_official | 525:c320967f86b9 | 58 | #define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */ |
| mbed_official | 525:c320967f86b9 | 59 | #define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ |
| mbed_official | 525:c320967f86b9 | 60 | #define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 61 | #define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 62 | #define ACMP_CTRL_MUXEN (0x1UL << 1) /**< Input Mux Enable */ |
| mbed_official | 525:c320967f86b9 | 63 | #define _ACMP_CTRL_MUXEN_SHIFT 1 /**< Shift value for ACMP_MUXEN */ |
| mbed_official | 525:c320967f86b9 | 64 | #define _ACMP_CTRL_MUXEN_MASK 0x2UL /**< Bit mask for ACMP_MUXEN */ |
| mbed_official | 525:c320967f86b9 | 65 | #define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 66 | #define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 67 | #define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */ |
| mbed_official | 525:c320967f86b9 | 68 | #define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */ |
| mbed_official | 525:c320967f86b9 | 69 | #define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */ |
| mbed_official | 525:c320967f86b9 | 70 | #define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 71 | #define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 72 | #define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 73 | #define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 74 | #define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 75 | #define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 76 | #define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */ |
| mbed_official | 525:c320967f86b9 | 77 | #define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */ |
| mbed_official | 525:c320967f86b9 | 78 | #define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */ |
| mbed_official | 525:c320967f86b9 | 79 | #define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 80 | #define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 81 | #define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 82 | #define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 83 | #define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 84 | #define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 85 | #define _ACMP_CTRL_HYSTSEL_SHIFT 4 /**< Shift value for ACMP_HYSTSEL */ |
| mbed_official | 525:c320967f86b9 | 86 | #define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /**< Bit mask for ACMP_HYSTSEL */ |
| mbed_official | 525:c320967f86b9 | 87 | #define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 88 | #define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 89 | #define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 90 | #define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 91 | #define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 92 | #define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 93 | #define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 94 | #define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 95 | #define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 96 | #define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 97 | #define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) /**< Shifted mode HYST0 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 98 | #define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) /**< Shifted mode HYST1 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 99 | #define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) /**< Shifted mode HYST2 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 100 | #define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) /**< Shifted mode HYST3 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 101 | #define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) /**< Shifted mode HYST4 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 102 | #define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) /**< Shifted mode HYST5 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 103 | #define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) /**< Shifted mode HYST6 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 104 | #define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) /**< Shifted mode HYST7 for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 105 | #define _ACMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for ACMP_WARMTIME */ |
| mbed_official | 525:c320967f86b9 | 106 | #define _ACMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for ACMP_WARMTIME */ |
| mbed_official | 525:c320967f86b9 | 107 | #define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 108 | #define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 109 | #define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 110 | #define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 111 | #define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 112 | #define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 113 | #define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 114 | #define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 115 | #define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 116 | #define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 117 | #define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 118 | #define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 119 | #define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 120 | #define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 121 | #define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 122 | #define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 123 | #define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 124 | #define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 125 | #define ACMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */ |
| mbed_official | 525:c320967f86b9 | 126 | #define _ACMP_CTRL_IRISE_SHIFT 16 /**< Shift value for ACMP_IRISE */ |
| mbed_official | 525:c320967f86b9 | 127 | #define _ACMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for ACMP_IRISE */ |
| mbed_official | 525:c320967f86b9 | 128 | #define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 129 | #define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 130 | #define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 131 | #define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 132 | #define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) /**< Shifted mode DISABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 133 | #define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) /**< Shifted mode ENABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 134 | #define ACMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */ |
| mbed_official | 525:c320967f86b9 | 135 | #define _ACMP_CTRL_IFALL_SHIFT 17 /**< Shift value for ACMP_IFALL */ |
| mbed_official | 525:c320967f86b9 | 136 | #define _ACMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for ACMP_IFALL */ |
| mbed_official | 525:c320967f86b9 | 137 | #define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 138 | #define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 139 | #define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 140 | #define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 141 | #define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) /**< Shifted mode DISABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 142 | #define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) /**< Shifted mode ENABLED for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 143 | #define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 144 | #define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for ACMP_BIASPROG */ |
| mbed_official | 525:c320967f86b9 | 145 | #define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 146 | #define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 147 | #define ACMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */ |
| mbed_official | 525:c320967f86b9 | 148 | #define _ACMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for ACMP_HALFBIAS */ |
| mbed_official | 525:c320967f86b9 | 149 | #define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for ACMP_HALFBIAS */ |
| mbed_official | 525:c320967f86b9 | 150 | #define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 151 | #define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 152 | #define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */ |
| mbed_official | 525:c320967f86b9 | 153 | #define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */ |
| mbed_official | 525:c320967f86b9 | 154 | #define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */ |
| mbed_official | 525:c320967f86b9 | 155 | #define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 156 | #define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */ |
| mbed_official | 525:c320967f86b9 | 157 | |
| mbed_official | 525:c320967f86b9 | 158 | /* Bit fields for ACMP INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 159 | #define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /**< Default value for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 160 | #define _ACMP_INPUTSEL_MASK 0x31013FF7UL /**< Mask for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 161 | #define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ |
| mbed_official | 525:c320967f86b9 | 162 | #define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /**< Bit mask for ACMP_POSSEL */ |
| mbed_official | 525:c320967f86b9 | 163 | #define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 164 | #define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 165 | #define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 166 | #define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 167 | #define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 168 | #define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 169 | #define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 170 | #define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 171 | #define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 172 | #define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 173 | #define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) /**< Shifted mode CH0 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 174 | #define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) /**< Shifted mode CH1 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 175 | #define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) /**< Shifted mode CH2 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 176 | #define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) /**< Shifted mode CH3 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 177 | #define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) /**< Shifted mode CH4 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 178 | #define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) /**< Shifted mode CH5 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 179 | #define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) /**< Shifted mode CH6 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 180 | #define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) /**< Shifted mode CH7 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 181 | #define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /**< Shift value for ACMP_NEGSEL */ |
| mbed_official | 525:c320967f86b9 | 182 | #define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /**< Bit mask for ACMP_NEGSEL */ |
| mbed_official | 525:c320967f86b9 | 183 | #define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 184 | #define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 185 | #define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 186 | #define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 187 | #define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 188 | #define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 189 | #define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 190 | #define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 191 | #define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /**< Mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 192 | #define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL /**< Mode 1V25 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 193 | #define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL /**< Mode 2V5 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 194 | #define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL /**< Mode VDD for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 195 | #define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /**< Mode CAPSENSE for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 196 | #define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) /**< Shifted mode CH0 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 197 | #define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) /**< Shifted mode CH1 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 198 | #define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) /**< Shifted mode CH2 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 199 | #define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) /**< Shifted mode CH3 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 200 | #define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) /**< Shifted mode CH4 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 201 | #define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) /**< Shifted mode CH5 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 202 | #define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) /**< Shifted mode CH6 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 203 | #define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) /**< Shifted mode CH7 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 204 | #define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 205 | #define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) /**< Shifted mode 1V25 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 206 | #define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) /**< Shifted mode 2V5 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 207 | #define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) /**< Shifted mode VDD for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 208 | #define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 209 | #define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /**< Shift value for ACMP_VDDLEVEL */ |
| mbed_official | 525:c320967f86b9 | 210 | #define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /**< Bit mask for ACMP_VDDLEVEL */ |
| mbed_official | 525:c320967f86b9 | 211 | #define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 212 | #define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 213 | #define ACMP_INPUTSEL_LPREF (0x1UL << 16) /**< Low Power Reference Mode */ |
| mbed_official | 525:c320967f86b9 | 214 | #define _ACMP_INPUTSEL_LPREF_SHIFT 16 /**< Shift value for ACMP_LPREF */ |
| mbed_official | 525:c320967f86b9 | 215 | #define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /**< Bit mask for ACMP_LPREF */ |
| mbed_official | 525:c320967f86b9 | 216 | #define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 217 | #define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 218 | #define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) /**< Capacitive Sense Mode Internal Resistor Enable */ |
| mbed_official | 525:c320967f86b9 | 219 | #define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /**< Shift value for ACMP_CSRESEN */ |
| mbed_official | 525:c320967f86b9 | 220 | #define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /**< Bit mask for ACMP_CSRESEN */ |
| mbed_official | 525:c320967f86b9 | 221 | #define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 222 | #define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 223 | #define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ |
| mbed_official | 525:c320967f86b9 | 224 | #define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /**< Bit mask for ACMP_CSRESSEL */ |
| mbed_official | 525:c320967f86b9 | 225 | #define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 226 | #define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 227 | #define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 228 | #define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 229 | #define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 230 | #define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 231 | #define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 232 | #define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 233 | #define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 234 | #define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */ |
| mbed_official | 525:c320967f86b9 | 235 | |
| mbed_official | 525:c320967f86b9 | 236 | /* Bit fields for ACMP STATUS */ |
| mbed_official | 525:c320967f86b9 | 237 | #define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 238 | #define _ACMP_STATUS_MASK 0x00000003UL /**< Mask for ACMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 239 | #define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */ |
| mbed_official | 525:c320967f86b9 | 240 | #define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */ |
| mbed_official | 525:c320967f86b9 | 241 | #define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */ |
| mbed_official | 525:c320967f86b9 | 242 | #define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 243 | #define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 244 | #define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */ |
| mbed_official | 525:c320967f86b9 | 245 | #define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */ |
| mbed_official | 525:c320967f86b9 | 246 | #define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */ |
| mbed_official | 525:c320967f86b9 | 247 | #define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 248 | #define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */ |
| mbed_official | 525:c320967f86b9 | 249 | |
| mbed_official | 525:c320967f86b9 | 250 | /* Bit fields for ACMP IEN */ |
| mbed_official | 525:c320967f86b9 | 251 | #define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 252 | #define _ACMP_IEN_MASK 0x00000003UL /**< Mask for ACMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 253 | #define ACMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 254 | #define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 255 | #define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 256 | #define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 257 | #define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 258 | #define ACMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 259 | #define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 260 | #define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 261 | #define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 262 | #define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ |
| mbed_official | 525:c320967f86b9 | 263 | |
| mbed_official | 525:c320967f86b9 | 264 | /* Bit fields for ACMP IF */ |
| mbed_official | 525:c320967f86b9 | 265 | #define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ |
| mbed_official | 525:c320967f86b9 | 266 | #define _ACMP_IF_MASK 0x00000003UL /**< Mask for ACMP_IF */ |
| mbed_official | 525:c320967f86b9 | 267 | #define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 268 | #define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 269 | #define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 270 | #define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ |
| mbed_official | 525:c320967f86b9 | 271 | #define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ |
| mbed_official | 525:c320967f86b9 | 272 | #define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 273 | #define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 274 | #define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 275 | #define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ |
| mbed_official | 525:c320967f86b9 | 276 | #define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ |
| mbed_official | 525:c320967f86b9 | 277 | |
| mbed_official | 525:c320967f86b9 | 278 | /* Bit fields for ACMP IFS */ |
| mbed_official | 525:c320967f86b9 | 279 | #define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 280 | #define _ACMP_IFS_MASK 0x00000003UL /**< Mask for ACMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 281 | #define ACMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 282 | #define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 283 | #define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 284 | #define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 285 | #define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 286 | #define ACMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 287 | #define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 288 | #define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 289 | #define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 290 | #define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */ |
| mbed_official | 525:c320967f86b9 | 291 | |
| mbed_official | 525:c320967f86b9 | 292 | /* Bit fields for ACMP IFC */ |
| mbed_official | 525:c320967f86b9 | 293 | #define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 294 | #define _ACMP_IFC_MASK 0x00000003UL /**< Mask for ACMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 295 | #define ACMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 296 | #define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 297 | #define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */ |
| mbed_official | 525:c320967f86b9 | 298 | #define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 299 | #define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 300 | #define ACMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 301 | #define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 302 | #define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */ |
| mbed_official | 525:c320967f86b9 | 303 | #define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 304 | #define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */ |
| mbed_official | 525:c320967f86b9 | 305 | |
| mbed_official | 525:c320967f86b9 | 306 | /* Bit fields for ACMP ROUTE */ |
| mbed_official | 525:c320967f86b9 | 307 | #define _ACMP_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 308 | #define _ACMP_ROUTE_MASK 0x00000701UL /**< Mask for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 309 | #define ACMP_ROUTE_ACMPPEN (0x1UL << 0) /**< ACMP Output Pin Enable */ |
| mbed_official | 525:c320967f86b9 | 310 | #define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /**< Shift value for ACMP_ACMPPEN */ |
| mbed_official | 525:c320967f86b9 | 311 | #define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /**< Bit mask for ACMP_ACMPPEN */ |
| mbed_official | 525:c320967f86b9 | 312 | #define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 313 | #define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 314 | #define _ACMP_ROUTE_LOCATION_SHIFT 8 /**< Shift value for ACMP_LOCATION */ |
| mbed_official | 525:c320967f86b9 | 315 | #define _ACMP_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for ACMP_LOCATION */ |
| mbed_official | 525:c320967f86b9 | 316 | #define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 317 | #define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 318 | #define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 319 | #define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 320 | #define _ACMP_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 321 | #define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 322 | #define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 323 | #define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 324 | #define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 325 | #define ACMP_ROUTE_LOCATION_LOC3 (_ACMP_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for ACMP_ROUTE */ |
| mbed_official | 525:c320967f86b9 | 326 | |
| mbed_official | 525:c320967f86b9 | 327 | /** @} End of group EFM32HG_ACMP */ |
| mbed_official | 525:c320967f86b9 | 328 | |
| mbed_official | 525:c320967f86b9 | 329 |