marcus chiou
/
mbed-src
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mbed official
Revision 447:78d5dca142f0, committed 2015-01-19
- Comitter:
- mbed_official
- Date:
- Mon Jan 19 13:00:08 2015 +0000
- Parent:
- 446:b421ac8a7b41
- Child:
- 448:f58c94c7c4b6
- Commit message:
- Synchronized with git revision befdc7ae6b8b3fdc35eddd21160f1921204eac98
Full URL: https://github.com/mbedmicro/mbed/commit/befdc7ae6b8b3fdc35eddd21160f1921204eac98/
LPC1114 - remove reset pin name to protect people. [LPC824] I2C pin names were crossed
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct Mon Jan 19 13:00:08 2015 +0000
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/startup_LPC11xx.s Mon Jan 19 13:00:08 2015 +0000 @@ -0,0 +1,325 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x + + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/LPC11U37.sct Mon Jan 19 13:00:08 2015 +0000
@@ -0,0 +1,20 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (128K)
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
+ .ANY (IOHANDLER_RAM)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_ARM_STD/TARGET_LPC11U37H_401/startup_LPC11xx.s Mon Jan 19 13:00:08 2015 +0000 @@ -0,0 +1,308 @@ +;/***************************************************************************** +; * @file: startup_LPC11xx.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the NXP LPC11xx Device Series +; * @version: V1.0 +; * @date: 25. Nov. 2008 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2008 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U3x + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; for LPC11Uxx (With USB) + DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx + DCD FLEX_INT1_IRQHandler + DCD FLEX_INT2_IRQHandler + DCD FLEX_INT3_IRQHandler + DCD FLEX_INT4_IRQHandler + DCD FLEX_INT5_IRQHandler + DCD FLEX_INT6_IRQHandler + DCD FLEX_INT7_IRQHandler + DCD GINT0_IRQHandler + DCD GINT1_IRQHandler ; PIO0 (0:7) + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD Reserved_IRQHandler + DCD SSP1_IRQHandler ; SSP1 + DCD I2C_IRQHandler ; I2C + DCD TIMER16_0_IRQHandler ; 16-bit Timer0 + DCD TIMER16_1_IRQHandler ; 16-bit Timer1 + DCD TIMER32_0_IRQHandler ; 32-bit Timer0 + DCD TIMER32_1_IRQHandler ; 32-bit Timer1 + DCD SSP0_IRQHandler ; SSP0 + DCD UART_IRQHandler ; UART + DCD USB_IRQHandler ; USB IRQ + DCD USB_FIQHandler ; USB FIQ + DCD ADC_IRQHandler ; A/D Converter + DCD WDT_IRQHandler ; Watchdog timer + DCD BOD_IRQHandler ; Brown Out Detect + DCD FMC_IRQHandler ; IP2111 Flash Memory Controller + DCD Reserved_IRQHandler ; Reserved + DCD Reserved_IRQHandler ; Reserved + DCD USBWakeup_IRQHandler ; USB wake up + DCD Reserved_IRQHandler ; Reserved + + ;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + DCD 0xFFFFFFFF ; Datafill + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled +; for particular peripheral. +;NMI_Handler PROC +; EXPORT NMI_Handler [WEAK] +; B . +; ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC +; for LPC11Uxx (With USB) + EXPORT NMI_Handler [WEAK] + EXPORT FLEX_INT0_IRQHandler [WEAK] + EXPORT FLEX_INT1_IRQHandler [WEAK] + EXPORT FLEX_INT2_IRQHandler [WEAK] + EXPORT FLEX_INT3_IRQHandler [WEAK] + EXPORT FLEX_INT4_IRQHandler [WEAK] + EXPORT FLEX_INT5_IRQHandler [WEAK] + EXPORT FLEX_INT6_IRQHandler [WEAK] + EXPORT FLEX_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT TIMER16_0_IRQHandler [WEAK] + EXPORT TIMER16_1_IRQHandler [WEAK] + EXPORT TIMER32_0_IRQHandler [WEAK] + EXPORT TIMER32_1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT UART_IRQHandler [WEAK] + + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT USBWakeup_IRQHandler [WEAK] + +NMI_Handler +FLEX_INT0_IRQHandler +FLEX_INT1_IRQHandler +FLEX_INT2_IRQHandler +FLEX_INT3_IRQHandler +FLEX_INT4_IRQHandler +FLEX_INT5_IRQHandler +FLEX_INT6_IRQHandler +FLEX_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +SSP1_IRQHandler +I2C_IRQHandler +TIMER16_0_IRQHandler +TIMER16_1_IRQHandler +TIMER32_0_IRQHandler +TIMER32_1_IRQHandler +SSP0_IRQHandler +UART_IRQHandler +USB_IRQHandler +USB_FIQHandler +ADC_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +FMC_IRQHandler +USBWakeup_IRQHandler + + B . + + ENDP + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_ARM/TARGET_LPC11U37H_401/LPC11U37.ld Mon Jan 19 13:00:08 2015 +0000
@@ -0,0 +1,152 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
+ RAMIO (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800
+ USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld Mon Jan 19 13:00:08 2015 +0000
@@ -0,0 +1,157 @@
+/* mbed - LPC11U35 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
+ RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
+ RamIo1 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2k */
+ RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash32 = 0x0 + 0x10000;
+ __top_RamLoc8 = 0x10000000 + 0x1F40;
+ __top_RamIo1 = 0x20000000 + 0x800;
+ __top_RamUsb2 = 0x20004000 + 0x800;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+ *(.text.ResetISR)
+ . = 0x200;
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash32
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash32
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash32
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2 AT>MFlash32
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc8
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc8 AT>MFlash32
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamUsb2*)
+ . = ALIGN(4) ;
+ } > RamUsb2
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ __end__ = .;
+ } > RamLoc8
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc8 - 0);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h Mon Jan 19 13:00:08 2015 +0000
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ PWM_1 = 0,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11
+} PWMName;
+
+#define STDIO_UART_TX UART_TX
+#define STDIO_UART_RX UART_RX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c Mon Jan 19 13:00:08 2015 +0000
@@ -0,0 +1,117 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+ {P0_11, ADC0_0, 0x02},
+ {P0_12, ADC0_1, 0x02},
+ {P0_13, ADC0_2, 0x02},
+ {P0_14, ADC0_3, 0x02},
+ {P0_15, ADC0_4, 0x02},
+ {P0_16, ADC0_5, 0x01},
+ {P0_22, ADC0_6, 0x01},
+ {P0_23, ADC0_7, 0x01},
+ {NC , NC , 0 }
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ {P0_5, I2C_0, 1},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {P0_4, I2C_0, 1},
+ {NC , NC, 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+ {P0_19, UART_0, 1},
+ {P1_13, UART_0, 3},
+ {P1_27, UART_0, 2},
+ { NC , NC , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {P0_18, UART_0, 1},
+ {P1_14, UART_0, 3},
+ {P1_26, UART_0, 2},
+ {NC , NC , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+ {P0_6 , SPI_0, 0x02},
+ {P0_10, SPI_0, 0x02},
+ {P1_29, SPI_0, 0x01},
+ {P1_15, SPI_1, 0x03},
+ {P1_20, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {P0_9 , SPI_0, 0x01},
+ {P0_21, SPI_1, 0x02},
+ {P1_22, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {P0_8 , SPI_0, 0x01},
+ {P0_22, SPI_1, 0x03},
+ {P1_21, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {P0_2 , SPI_0, 0x01},
+ {P1_19, SPI_1, 0x02},
+ {P1_23, SPI_1, 0x02},
+ {NC , NC , 0}
+};
+
+/************PWM***************/
+/* To have a PWM where we can change both the period and the duty cycle,
+ * we need an entire timer. With the following conventions:
+ * * MR3 is used for the PWM period
+ * * MR0, MR1, MR2 are used for the duty cycle
+ */
+const PinMap PinMap_PWM[] = {
+ /* CT16B0 */
+ {P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
+ {P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
+ {P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
+
+ /* CT16B1 */
+ {P0_21, PWM_4, 1}, /* MR0 */
+ {P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
+
+ /* CT32B0 */
+ {P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
+ {P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
+ {P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
+
+ /* CT32B1 */
+ {P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
+ {P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
+ {P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
+
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PinNames.h Mon Jan 19 13:00:08 2015 +0000
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC11U Pin Names
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+ P0_6 = 6,
+ P0_7 = 7,
+ P0_8 = 8,
+ P0_9 = 9,
+ P0_10 = 10,
+ P0_11 = 11,
+ P0_12 = 12,
+ P0_13 = 13,
+ P0_14 = 14,
+ P0_15 = 15,
+ P0_16 = 16,
+ P0_17 = 17,
+ P0_18 = 18,
+ P0_19 = 19,
+ P0_20 = 20,
+ P0_21 = 21,
+ P0_22 = 22,
+ P0_23 = 23,
+ P0_24 = 24,
+ P0_25 = 25,
+ P0_26 = 26,
+ P0_27 = 27,
+
+ P1_0 = 32,
+ P1_1 = 33,
+ P1_2 = 34,
+ P1_3 = 35,
+ P1_4 = 36,
+ P1_5 = 37,
+ P1_6 = 38,
+ P1_7 = 39,
+ P1_8 = 40,
+ P1_9 = 41,
+ P1_10 = 42,
+ P1_11 = 43,
+ P1_12 = 44,
+ P1_13 = 45,
+ P1_14 = 46,
+ P1_15 = 47,
+ P1_16 = 48,
+ P1_17 = 49,
+ P1_18 = 50,
+ P1_19 = 51,
+ P1_20 = 52,
+ P1_21 = 53,
+ P1_22 = 54,
+ P1_23 = 55,
+ P1_24 = 56,
+ P1_25 = 57,
+ P1_26 = 58,
+ P1_27 = 59,
+ P1_28 = 60,
+ P1_29 = 61,
+
+ P1_31 = 63,
+
+ // LED Names
+ LED1 = P1_24,
+ LED2 = P1_25,
+ LED3 = P1_26,
+ LED4 = P0_0,
+ LED5 = P1_3,
+ LED6 = P1_2,
+ LED7 = P1_1,
+ LED8 = P1_0,
+
+ // BTN Names
+ BTN1 = P0_16,
+ BTN2 = P0_1,
+
+ // UART
+ UART_TX = P0_19,
+ UART_RX = P0_18,
+
+ // Arduino Shield Receptacles Names
+ D0 = P0_18,
+ D1 = P0_19,
+ D2 = P1_17,
+ D3 = P1_24,
+ D4 = P1_5,
+ D5 = P0_1,
+ D6 = P1_27,
+ D7 = P0_7,
+ D8 = P0_2,
+ D9 = P1_25,
+ D10= P1_23,
+ D11= P0_21,
+ D12= P0_22,
+ D13= P1_15,
+ D14= P0_5,
+ D15= P0_4,
+
+ A0 = P0_11,
+ A1 = P0_12,
+ A2 = P0_13,
+ A3 = P0_16,
+ A4 = P0_5, // same port as SDA
+ A5 = P0_4, // same port as SCL
+
+ SDA= P0_5, // same port as A4
+ SCL= P0_4, // same port as A5
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ CHANNEL0 = FLEX_INT0_IRQn,
+ CHANNEL1 = FLEX_INT1_IRQn,
+ CHANNEL2 = FLEX_INT2_IRQn,
+ CHANNEL3 = FLEX_INT3_IRQn,
+ CHANNEL4 = FLEX_INT4_IRQn,
+ CHANNEL5 = FLEX_INT5_IRQn,
+ CHANNEL6 = FLEX_INT6_IRQn,
+ CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4,
+ PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h Mon Jan 19 13:00:08 2015 +0000 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- a/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h Sat Jan 17 10:30:07 2015 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/PinNames.h Mon Jan 19 13:00:08 2015 +0000
@@ -78,7 +78,7 @@
P3_5 = (3 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x48,
// mbed DIP Pin Names (CQ board)
- p4 = P0_0,
+// p4 = P0_0,
p5 = P0_9,
p6 = P0_8,
p7 = P0_6,
@@ -114,7 +114,7 @@
USBRX = P1_6,
// mbed DIP Pin Names (LPCXpresso LPC1114)
- xp4 = P0_0,
+// xp4 = P0_0,
xp5 = P0_9,
xp6 = P0_8,
xp7 = P2_11,
@@ -173,7 +173,7 @@
dp16 = P1_7,
dp17 = P1_8,
dp18 = P1_9,
- dp23 = P0_0,
+// dp23 = P0_0,
dp24 = P0_1,
dp25 = P0_2,
dp26 = P0_3,
@@ -194,7 +194,7 @@
dip16 = P1_7,
dip17 = P1_8,
dip18 = P1_9,
- dip23 = P0_0,
+// dip23 = P0_0,
dip24 = P0_1,
dip25 = P0_2,
dip26 = P0_3,
--- a/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h Sat Jan 17 10:30:07 2015 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h Mon Jan 19 13:00:08 2015 +0000
@@ -30,7 +30,7 @@
#define MBED_UART0 P0_7, P0_18
#define MBED_UARTUSB USBTX, USBRX
-#define MBED_I2C0 P0_10, P0_11
+#define MBED_I2C0 P0_11, P0_10
typedef enum {
ADC_0 = 0,
--- a/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h Sat Jan 17 10:30:07 2015 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h Mon Jan 19 13:00:08 2015 +0000
@@ -102,10 +102,10 @@
USBRX = P0_18,
// I2C pins
- SDA = P0_10,
- SCL = P0_11,
- I2C_SDA = P0_10,
- I2C_SCL = P0_11,
+ SCL = P0_10,
+ SDA = P0_11,
+ I2C_SCL = P0_10,
+ I2C_SDA = P0_11,
// Not connected
NC = (int)0xFFFFFFFF,
--- a/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h Sat Jan 17 10:30:07 2015 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h Mon Jan 19 13:00:08 2015 +0000
@@ -30,7 +30,7 @@
#define MBED_UART0 P0_7, P0_18
#define MBED_UARTUSB USBTX, USBRX
-#define MBED_I2C0 P0_10, P0_11
+#define MBED_I2C0 P0_11, P0_10
typedef enum {
ADC_0 = 0,
--- a/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h Sat Jan 17 10:30:07 2015 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h Mon Jan 19 13:00:08 2015 +0000
@@ -102,10 +102,10 @@
USBRX = P0_18,
// I2C pins
- SDA = P0_10,
- SCL = P0_11,
- I2C_SDA = P0_10,
- I2C_SCL = P0_11,
+ SCL = P0_10,
+ SDA = P0_11,
+ I2C_SCL = P0_10,
+ I2C_SDA = P0_11,
// Not connected
NC = (int)0xFFFFFFFF,