mbed library sources
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Diff: targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h
- Revision:
- 613:bc40b8d2aec4
- Parent:
- 532:fe11edbda85c
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h Tue Aug 18 15:00:09 2015 +0100 +++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/stm32f429xx.h Thu Aug 20 10:45:13 2015 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f429xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 + * @version V2.3.2 + * @date 26-June-2015 * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File. * * This file contains: @@ -1060,12 +1060,11 @@ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */ #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */ @@ -6112,7 +6111,7 @@ /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) -#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) +#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /******************** Bits definition for RTC_WUTR register *****************/ #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) @@ -6517,7 +6516,7 @@ #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */ #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */ #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */ -#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */ +#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */ /****************** Bit definition for SAI_xCLRFR register ******************/ #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */