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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

Committer:: mbed_official
Date:: Thu Aug 20 10:45:13 2015 +0100
Revision:: 613:bc40b8d2aec4
Parent:: 532:fe11edbda85c

Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade

Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/

Nordic: update application start address in GCC linker script

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User	Revision	Line number	New contents of line
mbed_official	235:685d5f11838f	1	/**
mbed_official	235:685d5f11838f	2	******************************************************************************
mbed_official	235:685d5f11838f	3	* @file stm32f4xx_hal_rcc.h
mbed_official	235:685d5f11838f	4	* @author MCD Application Team
mbed_official	613:bc40b8d2aec4	5	* @version V1.3.2
mbed_official	613:bc40b8d2aec4	6	* @date 26-June-2015
mbed_official	235:685d5f11838f	7	* @brief Header file of RCC HAL module.
mbed_official	235:685d5f11838f	8	******************************************************************************
mbed_official	235:685d5f11838f	9	* @attention
mbed_official	235:685d5f11838f	10	*
mbed_official	532:fe11edbda85c	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	235:685d5f11838f	12	*
mbed_official	235:685d5f11838f	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	235:685d5f11838f	14	* are permitted provided that the following conditions are met:
mbed_official	235:685d5f11838f	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	235:685d5f11838f	16	* this list of conditions and the following disclaimer.
mbed_official	235:685d5f11838f	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	235:685d5f11838f	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	235:685d5f11838f	19	* and/or other materials provided with the distribution.
mbed_official	235:685d5f11838f	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	235:685d5f11838f	21	* may be used to endorse or promote products derived from this software
mbed_official	235:685d5f11838f	22	* without specific prior written permission.
mbed_official	235:685d5f11838f	23	*
mbed_official	235:685d5f11838f	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	235:685d5f11838f	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	235:685d5f11838f	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	235:685d5f11838f	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	235:685d5f11838f	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	235:685d5f11838f	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	235:685d5f11838f	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	235:685d5f11838f	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	235:685d5f11838f	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	235:685d5f11838f	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	235:685d5f11838f	34	*
mbed_official	235:685d5f11838f	35	******************************************************************************
mbed_official	235:685d5f11838f	36	*/
mbed_official	235:685d5f11838f	37
mbed_official	235:685d5f11838f	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	235:685d5f11838f	39	#ifndef __STM32F4xx_HAL_RCC_H
mbed_official	235:685d5f11838f	40	#define __STM32F4xx_HAL_RCC_H
mbed_official	235:685d5f11838f	41
mbed_official	235:685d5f11838f	42	#ifdef __cplusplus
mbed_official	235:685d5f11838f	43	extern "C" {
mbed_official	235:685d5f11838f	44	#endif
mbed_official	235:685d5f11838f	45
mbed_official	235:685d5f11838f	46	/* Includes ------------------------------------------------------------------*/
mbed_official	235:685d5f11838f	47	#include "stm32f4xx_hal_def.h"
mbed_official	235:685d5f11838f	48
mbed_official	532:fe11edbda85c	49	/* Include RCC HAL Extended module */
mbed_official	532:fe11edbda85c	50	/* (include on top of file since RCC structures are defined in extended file) */
mbed_official	532:fe11edbda85c	51	#include "stm32f4xx_hal_rcc_ex.h"
mbed_official	532:fe11edbda85c	52
mbed_official	235:685d5f11838f	53	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	235:685d5f11838f	54	* @{
mbed_official	235:685d5f11838f	55	*/
mbed_official	235:685d5f11838f	56
mbed_official	532:fe11edbda85c	57	/** @addtogroup RCC
mbed_official	235:685d5f11838f	58	* @{
mbed_official	235:685d5f11838f	59	*/
mbed_official	235:685d5f11838f	60
mbed_official	532:fe11edbda85c	61	/* Exported types ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	62	/** @defgroup RCC_Exported_Types RCC Exported Types
mbed_official	532:fe11edbda85c	63	* @{
mbed_official	235:685d5f11838f	64	*/
mbed_official	532:fe11edbda85c	65
mbed_official	235:685d5f11838f	66	/**
mbed_official	235:685d5f11838f	67	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	235:685d5f11838f	68	*/
mbed_official	235:685d5f11838f	69	typedef struct
mbed_official	235:685d5f11838f	70	{
mbed_official	235:685d5f11838f	71	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	235:685d5f11838f	72	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	235:685d5f11838f	73
mbed_official	235:685d5f11838f	74	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	235:685d5f11838f	75	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	235:685d5f11838f	76
mbed_official	235:685d5f11838f	77	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	235:685d5f11838f	78	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	235:685d5f11838f	79
mbed_official	235:685d5f11838f	80	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	235:685d5f11838f	81	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	235:685d5f11838f	82
mbed_official	235:685d5f11838f	83	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	235:685d5f11838f	84	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	235:685d5f11838f	85
mbed_official	235:685d5f11838f	86	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	235:685d5f11838f	87	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	235:685d5f11838f	88
mbed_official	235:685d5f11838f	89	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	235:685d5f11838f	90
mbed_official	235:685d5f11838f	91	}RCC_OscInitTypeDef;
mbed_official	235:685d5f11838f	92
mbed_official	235:685d5f11838f	93	/**
mbed_official	235:685d5f11838f	94	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	235:685d5f11838f	95	*/
mbed_official	235:685d5f11838f	96	typedef struct
mbed_official	235:685d5f11838f	97	{
mbed_official	235:685d5f11838f	98	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	235:685d5f11838f	99	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	235:685d5f11838f	100
mbed_official	235:685d5f11838f	101	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	235:685d5f11838f	102	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	235:685d5f11838f	103
mbed_official	235:685d5f11838f	104	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	235:685d5f11838f	105	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	235:685d5f11838f	106
mbed_official	235:685d5f11838f	107	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	235:685d5f11838f	108	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	235:685d5f11838f	109
mbed_official	235:685d5f11838f	110	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	235:685d5f11838f	111	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	235:685d5f11838f	112
mbed_official	235:685d5f11838f	113	}RCC_ClkInitTypeDef;
mbed_official	235:685d5f11838f	114
mbed_official	235:685d5f11838f	115	/**
mbed_official	235:685d5f11838f	116	* @}
mbed_official	235:685d5f11838f	117	*/
mbed_official	235:685d5f11838f	118
mbed_official	532:fe11edbda85c	119	/* Exported constants --------------------------------------------------------*/
mbed_official	532:fe11edbda85c	120	/** @defgroup RCC_Exported_Constants RCC Exported Constants
mbed_official	532:fe11edbda85c	121	* @{
mbed_official	532:fe11edbda85c	122	*/
mbed_official	532:fe11edbda85c	123
mbed_official	532:fe11edbda85c	124	/** @defgroup RCC_Oscillator_Type Oscillator Type
mbed_official	235:685d5f11838f	125	* @{
mbed_official	235:685d5f11838f	126	*/
mbed_official	235:685d5f11838f	127	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	128	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	129	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	130	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	131	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	132	/**
mbed_official	235:685d5f11838f	133	* @}
mbed_official	235:685d5f11838f	134	*/
mbed_official	235:685d5f11838f	135
mbed_official	532:fe11edbda85c	136	/** @defgroup RCC_HSE_Config HSE Config
mbed_official	235:685d5f11838f	137	* @{
mbed_official	235:685d5f11838f	138	*/
mbed_official	235:685d5f11838f	139	#define RCC_HSE_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	140	#define RCC_HSE_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	141	#define RCC_HSE_BYPASS ((uint8_t)0x05)
mbed_official	235:685d5f11838f	142	/**
mbed_official	235:685d5f11838f	143	* @}
mbed_official	235:685d5f11838f	144	*/
mbed_official	235:685d5f11838f	145
mbed_official	532:fe11edbda85c	146	/** @defgroup RCC_LSE_Config LSE Config
mbed_official	235:685d5f11838f	147	* @{
mbed_official	235:685d5f11838f	148	*/
mbed_official	235:685d5f11838f	149	#define RCC_LSE_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	150	#define RCC_LSE_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	151	#define RCC_LSE_BYPASS ((uint8_t)0x05)
mbed_official	235:685d5f11838f	152	/**
mbed_official	235:685d5f11838f	153	* @}
mbed_official	235:685d5f11838f	154	*/
mbed_official	235:685d5f11838f	155
mbed_official	532:fe11edbda85c	156	/** @defgroup RCC_HSI_Config HSI Config
mbed_official	235:685d5f11838f	157	* @{
mbed_official	235:685d5f11838f	158	*/
mbed_official	235:685d5f11838f	159	#define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	160	#define RCC_HSI_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	161	/**
mbed_official	235:685d5f11838f	162	* @}
mbed_official	235:685d5f11838f	163	*/
mbed_official	235:685d5f11838f	164
mbed_official	532:fe11edbda85c	165	/** @defgroup RCC_LSI_Config LSI Config
mbed_official	235:685d5f11838f	166	* @{
mbed_official	235:685d5f11838f	167	*/
mbed_official	235:685d5f11838f	168	#define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official	235:685d5f11838f	169	#define RCC_LSI_ON ((uint8_t)0x01)
mbed_official	235:685d5f11838f	170	/**
mbed_official	235:685d5f11838f	171	* @}
mbed_official	235:685d5f11838f	172	*/
mbed_official	235:685d5f11838f	173
mbed_official	532:fe11edbda85c	174	/** @defgroup RCC_PLL_Config PLL Config
mbed_official	235:685d5f11838f	175	* @{
mbed_official	235:685d5f11838f	176	*/
mbed_official	235:685d5f11838f	177	#define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official	235:685d5f11838f	178	#define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official	235:685d5f11838f	179	#define RCC_PLL_ON ((uint8_t)0x02)
mbed_official	235:685d5f11838f	180	/**
mbed_official	235:685d5f11838f	181	* @}
mbed_official	235:685d5f11838f	182	*/
mbed_official	235:685d5f11838f	183
mbed_official	532:fe11edbda85c	184	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
mbed_official	235:685d5f11838f	185	* @{
mbed_official	235:685d5f11838f	186	*/
mbed_official	235:685d5f11838f	187	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	188	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	189	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
mbed_official	235:685d5f11838f	190	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	191	/**
mbed_official	235:685d5f11838f	192	* @}
mbed_official	235:685d5f11838f	193	*/
mbed_official	235:685d5f11838f	194
mbed_official	532:fe11edbda85c	195	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
mbed_official	235:685d5f11838f	196	* @{
mbed_official	235:685d5f11838f	197	*/
mbed_official	235:685d5f11838f	198	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
mbed_official	235:685d5f11838f	199	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
mbed_official	235:685d5f11838f	200	/**
mbed_official	235:685d5f11838f	201	* @}
mbed_official	235:685d5f11838f	202	*/
mbed_official	235:685d5f11838f	203
mbed_official	532:fe11edbda85c	204	/** @defgroup RCC_System_Clock_Type System Clock Type
mbed_official	235:685d5f11838f	205	* @{
mbed_official	235:685d5f11838f	206	*/
mbed_official	235:685d5f11838f	207	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	208	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	235:685d5f11838f	209	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	235:685d5f11838f	210	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official	235:685d5f11838f	211	/**
mbed_official	235:685d5f11838f	212	* @}
mbed_official	235:685d5f11838f	213	*/
mbed_official	235:685d5f11838f	214
mbed_official	532:fe11edbda85c	215	/** @defgroup RCC_System_Clock_Source System Clock Source
mbed_official	235:685d5f11838f	216	* @{
mbed_official	235:685d5f11838f	217	*/
mbed_official	235:685d5f11838f	218	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official	235:685d5f11838f	219	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official	235:685d5f11838f	220	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official	532:fe11edbda85c	221	#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1))
mbed_official	235:685d5f11838f	222	/**
mbed_official	235:685d5f11838f	223	* @}
mbed_official	532:fe11edbda85c	224	*/
mbed_official	235:685d5f11838f	225
mbed_official	532:fe11edbda85c	226	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
mbed_official	532:fe11edbda85c	227	* @{
mbed_official	532:fe11edbda85c	228	*/
mbed_official	532:fe11edbda85c	229	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
mbed_official	532:fe11edbda85c	230	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
mbed_official	532:fe11edbda85c	231	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
mbed_official	532:fe11edbda85c	232	#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1)) /!< PLLR used as system clock /
mbed_official	532:fe11edbda85c	233	/**
mbed_official	532:fe11edbda85c	234	* @}
mbed_official	532:fe11edbda85c	235	*/
mbed_official	532:fe11edbda85c	236
mbed_official	532:fe11edbda85c	237	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
mbed_official	235:685d5f11838f	238	* @{
mbed_official	235:685d5f11838f	239	*/
mbed_official	235:685d5f11838f	240	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official	235:685d5f11838f	241	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official	235:685d5f11838f	242	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official	235:685d5f11838f	243	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official	235:685d5f11838f	244	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official	235:685d5f11838f	245	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official	235:685d5f11838f	246	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official	235:685d5f11838f	247	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official	235:685d5f11838f	248	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official	235:685d5f11838f	249	/**
mbed_official	235:685d5f11838f	250	* @}
mbed_official	235:685d5f11838f	251	*/
mbed_official	235:685d5f11838f	252
mbed_official	532:fe11edbda85c	253	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
mbed_official	235:685d5f11838f	254	* @{
mbed_official	235:685d5f11838f	255	*/
mbed_official	235:685d5f11838f	256	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
mbed_official	235:685d5f11838f	257	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
mbed_official	235:685d5f11838f	258	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
mbed_official	235:685d5f11838f	259	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
mbed_official	235:685d5f11838f	260	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
mbed_official	235:685d5f11838f	261	/**
mbed_official	235:685d5f11838f	262	* @}
mbed_official	235:685d5f11838f	263	*/
mbed_official	235:685d5f11838f	264
mbed_official	532:fe11edbda85c	265	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
mbed_official	235:685d5f11838f	266	* @{
mbed_official	235:685d5f11838f	267	*/
mbed_official	235:685d5f11838f	268	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
mbed_official	235:685d5f11838f	269	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
mbed_official	235:685d5f11838f	270	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
mbed_official	235:685d5f11838f	271	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
mbed_official	235:685d5f11838f	272	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
mbed_official	235:685d5f11838f	273	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
mbed_official	235:685d5f11838f	274	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
mbed_official	235:685d5f11838f	275	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
mbed_official	235:685d5f11838f	276	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
mbed_official	235:685d5f11838f	277	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
mbed_official	235:685d5f11838f	278	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
mbed_official	235:685d5f11838f	279	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
mbed_official	235:685d5f11838f	280	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
mbed_official	235:685d5f11838f	281	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
mbed_official	235:685d5f11838f	282	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
mbed_official	235:685d5f11838f	283	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
mbed_official	235:685d5f11838f	284	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
mbed_official	235:685d5f11838f	285	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
mbed_official	235:685d5f11838f	286	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
mbed_official	235:685d5f11838f	287	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
mbed_official	235:685d5f11838f	288	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
mbed_official	235:685d5f11838f	289	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
mbed_official	235:685d5f11838f	290	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
mbed_official	235:685d5f11838f	291	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
mbed_official	235:685d5f11838f	292	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
mbed_official	235:685d5f11838f	293	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
mbed_official	235:685d5f11838f	294	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
mbed_official	235:685d5f11838f	295	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
mbed_official	235:685d5f11838f	296	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
mbed_official	235:685d5f11838f	297	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
mbed_official	235:685d5f11838f	298	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
mbed_official	235:685d5f11838f	299	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
mbed_official	235:685d5f11838f	300	/**
mbed_official	235:685d5f11838f	301	* @}
mbed_official	235:685d5f11838f	302	*/
mbed_official	235:685d5f11838f	303
mbed_official	532:fe11edbda85c	304	/** @defgroup RCC_I2S_Clock_Source I2S Clock Source
mbed_official	235:685d5f11838f	305	* @{
mbed_official	235:685d5f11838f	306	*/
mbed_official	235:685d5f11838f	307	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	308	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	309	/**
mbed_official	235:685d5f11838f	310	* @}
mbed_official	235:685d5f11838f	311	*/
mbed_official	235:685d5f11838f	312
mbed_official	532:fe11edbda85c	313	/** @defgroup RCC_MCO_Index MCO Index
mbed_official	235:685d5f11838f	314	* @{
mbed_official	235:685d5f11838f	315	*/
mbed_official	235:685d5f11838f	316	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	317	#define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official	235:685d5f11838f	318	/**
mbed_official	235:685d5f11838f	319	* @}
mbed_official	235:685d5f11838f	320	*/
mbed_official	235:685d5f11838f	321
mbed_official	532:fe11edbda85c	322	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
mbed_official	235:685d5f11838f	323	* @{
mbed_official	235:685d5f11838f	324	*/
mbed_official	235:685d5f11838f	325	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	326	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
mbed_official	235:685d5f11838f	327	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
mbed_official	235:685d5f11838f	328	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
mbed_official	235:685d5f11838f	329	/**
mbed_official	235:685d5f11838f	330	* @}
mbed_official	235:685d5f11838f	331	*/
mbed_official	235:685d5f11838f	332
mbed_official	532:fe11edbda85c	333	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
mbed_official	235:685d5f11838f	334	* @{
mbed_official	235:685d5f11838f	335	*/
mbed_official	235:685d5f11838f	336	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	337	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
mbed_official	235:685d5f11838f	338	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
mbed_official	235:685d5f11838f	339	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
mbed_official	235:685d5f11838f	340	/**
mbed_official	235:685d5f11838f	341	* @}
mbed_official	235:685d5f11838f	342	*/
mbed_official	235:685d5f11838f	343
mbed_official	532:fe11edbda85c	344	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
mbed_official	235:685d5f11838f	345	* @{
mbed_official	235:685d5f11838f	346	*/
mbed_official	235:685d5f11838f	347	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
mbed_official	235:685d5f11838f	348	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
mbed_official	235:685d5f11838f	349	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
mbed_official	235:685d5f11838f	350	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
mbed_official	235:685d5f11838f	351	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
mbed_official	235:685d5f11838f	352	/**
mbed_official	235:685d5f11838f	353	* @}
mbed_official	235:685d5f11838f	354	*/
mbed_official	235:685d5f11838f	355
mbed_official	532:fe11edbda85c	356	/** @defgroup RCC_Interrupt Interrupts
mbed_official	235:685d5f11838f	357	* @{
mbed_official	235:685d5f11838f	358	*/
mbed_official	235:685d5f11838f	359	#define RCC_IT_LSIRDY ((uint8_t)0x01)
mbed_official	235:685d5f11838f	360	#define RCC_IT_LSERDY ((uint8_t)0x02)
mbed_official	235:685d5f11838f	361	#define RCC_IT_HSIRDY ((uint8_t)0x04)
mbed_official	235:685d5f11838f	362	#define RCC_IT_HSERDY ((uint8_t)0x08)
mbed_official	235:685d5f11838f	363	#define RCC_IT_PLLRDY ((uint8_t)0x10)
mbed_official	235:685d5f11838f	364	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
mbed_official	235:685d5f11838f	365	#define RCC_IT_CSS ((uint8_t)0x80)
mbed_official	235:685d5f11838f	366	/**
mbed_official	235:685d5f11838f	367	* @}
mbed_official	235:685d5f11838f	368	*/
mbed_official	235:685d5f11838f	369
mbed_official	532:fe11edbda85c	370	/** @defgroup RCC_Flag Flags
mbed_official	235:685d5f11838f	371	* Elements values convention: 0XXYYYYYb
mbed_official	235:685d5f11838f	372	* - YYYYY : Flag position in the register
mbed_official	235:685d5f11838f	373	* - 0XX : Register index
mbed_official	235:685d5f11838f	374	* - 01: CR register
mbed_official	235:685d5f11838f	375	* - 10: BDCR register
mbed_official	235:685d5f11838f	376	* - 11: CSR register
mbed_official	235:685d5f11838f	377	* @{
mbed_official	235:685d5f11838f	378	*/
mbed_official	235:685d5f11838f	379	/* Flags in the CR register */
mbed_official	235:685d5f11838f	380	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
mbed_official	235:685d5f11838f	381	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
mbed_official	235:685d5f11838f	382	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
mbed_official	235:685d5f11838f	383	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
mbed_official	235:685d5f11838f	384
mbed_official	235:685d5f11838f	385	/* Flags in the BDCR register */
mbed_official	235:685d5f11838f	386	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
mbed_official	235:685d5f11838f	387
mbed_official	235:685d5f11838f	388	/* Flags in the CSR register */
mbed_official	235:685d5f11838f	389	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
mbed_official	235:685d5f11838f	390	#define RCC_FLAG_BORRST ((uint8_t)0x79)
mbed_official	235:685d5f11838f	391	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
mbed_official	235:685d5f11838f	392	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
mbed_official	235:685d5f11838f	393	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
mbed_official	235:685d5f11838f	394	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
mbed_official	235:685d5f11838f	395	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
mbed_official	235:685d5f11838f	396	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
mbed_official	235:685d5f11838f	397	/**
mbed_official	235:685d5f11838f	398	* @}
mbed_official	235:685d5f11838f	399	*/
mbed_official	235:685d5f11838f	400
mbed_official	235:685d5f11838f	401	/**
mbed_official	235:685d5f11838f	402	* @}
mbed_official	532:fe11edbda85c	403	*/
mbed_official	532:fe11edbda85c	404
mbed_official	235:685d5f11838f	405	/* Exported macro ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	406	/** @defgroup RCC_Exported_Macros RCC Exported Macros
mbed_official	532:fe11edbda85c	407	* @{
mbed_official	532:fe11edbda85c	408	*/
mbed_official	235:685d5f11838f	409
mbed_official	532:fe11edbda85c	410	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
mbed_official	532:fe11edbda85c	411	* @brief Enable or disable the AHB1 peripheral clock.
mbed_official	235:685d5f11838f	412	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	413	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	414	* using it.
mbed_official	532:fe11edbda85c	415	* @{
mbed_official	235:685d5f11838f	416	*/
mbed_official	532:fe11edbda85c	417	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	418	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	419	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
mbed_official	532:fe11edbda85c	420	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	421	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
mbed_official	532:fe11edbda85c	422	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	423	} while(0)
mbed_official	532:fe11edbda85c	424	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	425	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	426	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
mbed_official	532:fe11edbda85c	427	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	428	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
mbed_official	532:fe11edbda85c	429	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	430	} while(0)
mbed_official	532:fe11edbda85c	431	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	432	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	433	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
mbed_official	532:fe11edbda85c	434	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	435	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
mbed_official	532:fe11edbda85c	436	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	437	} while(0)
mbed_official	532:fe11edbda85c	438	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	439	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	440	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
mbed_official	532:fe11edbda85c	441	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	442	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
mbed_official	532:fe11edbda85c	443	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	444	} while(0)
mbed_official	532:fe11edbda85c	445	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	446	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	447	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
mbed_official	532:fe11edbda85c	448	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	449	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
mbed_official	532:fe11edbda85c	450	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	451	} while(0)
mbed_official	532:fe11edbda85c	452	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	453	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	454	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
mbed_official	532:fe11edbda85c	455	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	456	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
mbed_official	532:fe11edbda85c	457	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	458	} while(0)
mbed_official	532:fe11edbda85c	459	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	460	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	461	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
mbed_official	532:fe11edbda85c	462	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	463	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
mbed_official	532:fe11edbda85c	464	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	465	} while(0)
mbed_official	532:fe11edbda85c	466	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	467	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	468	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
mbed_official	532:fe11edbda85c	469	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	470	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
mbed_official	532:fe11edbda85c	471	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	472	} while(0)
mbed_official	532:fe11edbda85c	473	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	474	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	475	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
mbed_official	532:fe11edbda85c	476	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	477	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
mbed_official	532:fe11edbda85c	478	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	479	} while(0)
mbed_official	532:fe11edbda85c	480	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	481	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	482	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
mbed_official	532:fe11edbda85c	483	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	484	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
mbed_official	532:fe11edbda85c	485	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	486	} while(0)
mbed_official	532:fe11edbda85c	487	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	488	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	489	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
mbed_official	532:fe11edbda85c	490	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	491	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
mbed_official	532:fe11edbda85c	492	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	493	} while(0)
mbed_official	235:685d5f11838f	494
mbed_official	532:fe11edbda85c	495	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
mbed_official	532:fe11edbda85c	496	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
mbed_official	532:fe11edbda85c	497	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
mbed_official	532:fe11edbda85c	498	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
mbed_official	532:fe11edbda85c	499	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
mbed_official	532:fe11edbda85c	500	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
mbed_official	532:fe11edbda85c	501	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
mbed_official	532:fe11edbda85c	502	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
mbed_official	532:fe11edbda85c	503	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
mbed_official	532:fe11edbda85c	504	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
mbed_official	532:fe11edbda85c	505	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
mbed_official	235:685d5f11838f	506
mbed_official	532:fe11edbda85c	507	/**
mbed_official	532:fe11edbda85c	508	* @}
mbed_official	532:fe11edbda85c	509	*/
mbed_official	532:fe11edbda85c	510
mbed_official	532:fe11edbda85c	511	/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
mbed_official	532:fe11edbda85c	512	* @brief Enable or disable the AHB2 peripheral clock.
mbed_official	235:685d5f11838f	513	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	514	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	515	* using it.
mbed_official	532:fe11edbda85c	516	* @{
mbed_official	235:685d5f11838f	517	*/
mbed_official	532:fe11edbda85c	518	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
mbed_official	532:fe11edbda85c	519	__HAL_RCC_SYSCFG_CLK_ENABLE();\
mbed_official	532:fe11edbda85c	520	}while(0)
mbed_official	235:685d5f11838f	521
mbed_official	532:fe11edbda85c	522	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
mbed_official	532:fe11edbda85c	523	__HAL_RCC_SYSCFG_CLK_DISABLE();\
mbed_official	532:fe11edbda85c	524	}while(0)
mbed_official	235:685d5f11838f	525
mbed_official	532:fe11edbda85c	526	#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_RNGEN))
mbed_official	532:fe11edbda85c	527	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
mbed_official	235:685d5f11838f	528
mbed_official	532:fe11edbda85c	529	/**
mbed_official	532:fe11edbda85c	530	* @}
mbed_official	532:fe11edbda85c	531	*/
mbed_official	532:fe11edbda85c	532
mbed_official	532:fe11edbda85c	533	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
mbed_official	532:fe11edbda85c	534	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	235:685d5f11838f	535	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	536	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	537	* using it.
mbed_official	532:fe11edbda85c	538	* @{
mbed_official	235:685d5f11838f	539	*/
mbed_official	532:fe11edbda85c	540	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	541	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	542	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official	532:fe11edbda85c	543	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	544	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
mbed_official	532:fe11edbda85c	545	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	546	} while(0)
mbed_official	532:fe11edbda85c	547	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	548	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	549	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official	532:fe11edbda85c	550	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	551	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
mbed_official	532:fe11edbda85c	552	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	553	} while(0)
mbed_official	532:fe11edbda85c	554	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	555	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	556	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
mbed_official	532:fe11edbda85c	557	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	558	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
mbed_official	532:fe11edbda85c	559	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	560	} while(0)
mbed_official	532:fe11edbda85c	561	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	562	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	563	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official	532:fe11edbda85c	564	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	565	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official	532:fe11edbda85c	566	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	567	} while(0)
mbed_official	532:fe11edbda85c	568	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	569	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	570	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
mbed_official	532:fe11edbda85c	571	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	572	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
mbed_official	532:fe11edbda85c	573	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	574	} while(0)
mbed_official	532:fe11edbda85c	575	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	576	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	577	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official	532:fe11edbda85c	578	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	579	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official	532:fe11edbda85c	580	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	581	} while(0)
mbed_official	532:fe11edbda85c	582	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	583	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	584	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official	532:fe11edbda85c	585	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	586	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official	532:fe11edbda85c	587	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	588	} while(0)
mbed_official	532:fe11edbda85c	589	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	590	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	591	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official	532:fe11edbda85c	592	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	593	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
mbed_official	532:fe11edbda85c	594	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	595	} while(0)
mbed_official	532:fe11edbda85c	596	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	597	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	598	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official	532:fe11edbda85c	599	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	600	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
mbed_official	532:fe11edbda85c	601	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	602	} while(0)
mbed_official	532:fe11edbda85c	603	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	604	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	605	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official	532:fe11edbda85c	606	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	607	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official	532:fe11edbda85c	608	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	609	} while(0)
mbed_official	532:fe11edbda85c	610	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	611	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	612	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
mbed_official	532:fe11edbda85c	613	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	614	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
mbed_official	532:fe11edbda85c	615	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	616	} while(0)
mbed_official	532:fe11edbda85c	617	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	618	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	619	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
mbed_official	532:fe11edbda85c	620	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	621	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
mbed_official	532:fe11edbda85c	622	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	623	} while(0)
mbed_official	532:fe11edbda85c	624	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	532:fe11edbda85c	625	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	532:fe11edbda85c	626	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	532:fe11edbda85c	627	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official	532:fe11edbda85c	628	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	532:fe11edbda85c	629	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	532:fe11edbda85c	630	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	532:fe11edbda85c	631	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	532:fe11edbda85c	632	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official	532:fe11edbda85c	633	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	532:fe11edbda85c	634	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
mbed_official	532:fe11edbda85c	635	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official	532:fe11edbda85c	636	/**
mbed_official	532:fe11edbda85c	637	* @}
mbed_official	532:fe11edbda85c	638	*/
mbed_official	235:685d5f11838f	639
mbed_official	532:fe11edbda85c	640	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
mbed_official	532:fe11edbda85c	641	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	235:685d5f11838f	642	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	235:685d5f11838f	643	* is disabled and the application software has to enable this clock before
mbed_official	235:685d5f11838f	644	* using it.
mbed_official	532:fe11edbda85c	645	* @{
mbed_official	235:685d5f11838f	646	*/
mbed_official	532:fe11edbda85c	647	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	648	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	649	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official	532:fe11edbda85c	650	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	651	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
mbed_official	532:fe11edbda85c	652	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	653	} while(0)
mbed_official	532:fe11edbda85c	654	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	655	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	656	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official	532:fe11edbda85c	657	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	658	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
mbed_official	532:fe11edbda85c	659	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	660	} while(0)
mbed_official	532:fe11edbda85c	661	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	662	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	663	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
mbed_official	532:fe11edbda85c	664	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	665	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
mbed_official	532:fe11edbda85c	666	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	667	} while(0)
mbed_official	532:fe11edbda85c	668	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	669	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	670	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official	532:fe11edbda85c	671	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	672	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
mbed_official	532:fe11edbda85c	673	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	674	} while(0)
mbed_official	532:fe11edbda85c	675	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	676	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	677	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
mbed_official	532:fe11edbda85c	678	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	679	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
mbed_official	532:fe11edbda85c	680	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	681	} while(0)
mbed_official	532:fe11edbda85c	682	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	683	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official	532:fe11edbda85c	685	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
mbed_official	532:fe11edbda85c	687	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	688	} while(0)
mbed_official	532:fe11edbda85c	689	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	690	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	691	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
mbed_official	532:fe11edbda85c	692	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	693	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
mbed_official	532:fe11edbda85c	694	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	695	} while(0)
mbed_official	532:fe11edbda85c	696	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	697	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	698	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
mbed_official	532:fe11edbda85c	699	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	700	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
mbed_official	532:fe11edbda85c	701	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	702	} while(0)
mbed_official	532:fe11edbda85c	703	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	704	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	705	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
mbed_official	532:fe11edbda85c	706	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	707	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
mbed_official	532:fe11edbda85c	708	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	709	} while(0)
mbed_official	532:fe11edbda85c	710	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	711	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	712	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
mbed_official	532:fe11edbda85c	713	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	714	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
mbed_official	532:fe11edbda85c	715	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	716	} while(0)
mbed_official	532:fe11edbda85c	717	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
mbed_official	532:fe11edbda85c	718	__IO uint32_t tmpreg; \
mbed_official	532:fe11edbda85c	719	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
mbed_official	532:fe11edbda85c	720	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	532:fe11edbda85c	721	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
mbed_official	532:fe11edbda85c	722	UNUSED(tmpreg); \
mbed_official	532:fe11edbda85c	723	} while(0)
mbed_official	235:685d5f11838f	724
mbed_official	532:fe11edbda85c	725	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	532:fe11edbda85c	726	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official	532:fe11edbda85c	727	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official	532:fe11edbda85c	728	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	532:fe11edbda85c	729	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
mbed_official	532:fe11edbda85c	730	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	532:fe11edbda85c	731	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
mbed_official	532:fe11edbda85c	732	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
mbed_official	532:fe11edbda85c	733	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
mbed_official	532:fe11edbda85c	734	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
mbed_official	532:fe11edbda85c	735	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
mbed_official	532:fe11edbda85c	736	/**
mbed_official	532:fe11edbda85c	737	* @}
mbed_official	532:fe11edbda85c	738	*/
mbed_official	235:685d5f11838f	739
mbed_official	532:fe11edbda85c	740	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
mbed_official	532:fe11edbda85c	741	* @brief Force or release AHB1 peripheral reset.
mbed_official	532:fe11edbda85c	742	* @{
mbed_official	235:685d5f11838f	743	*/
mbed_official	532:fe11edbda85c	744	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
mbed_official	532:fe11edbda85c	745	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
mbed_official	532:fe11edbda85c	746	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
mbed_official	532:fe11edbda85c	747	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
mbed_official	532:fe11edbda85c	748	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
mbed_official	532:fe11edbda85c	749	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
mbed_official	532:fe11edbda85c	750	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
mbed_official	532:fe11edbda85c	751	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
mbed_official	532:fe11edbda85c	752	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
mbed_official	532:fe11edbda85c	753	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
mbed_official	235:685d5f11838f	754
mbed_official	532:fe11edbda85c	755	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
mbed_official	532:fe11edbda85c	756	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
mbed_official	532:fe11edbda85c	757	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
mbed_official	532:fe11edbda85c	758	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
mbed_official	532:fe11edbda85c	759	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
mbed_official	532:fe11edbda85c	760	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
mbed_official	532:fe11edbda85c	761	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official	532:fe11edbda85c	762	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official	532:fe11edbda85c	763	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
mbed_official	532:fe11edbda85c	764	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official	532:fe11edbda85c	765	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
mbed_official	532:fe11edbda85c	766	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
mbed_official	532:fe11edbda85c	767	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
mbed_official	532:fe11edbda85c	768	/**
mbed_official	532:fe11edbda85c	769	* @}
mbed_official	532:fe11edbda85c	770	*/
mbed_official	235:685d5f11838f	771
mbed_official	532:fe11edbda85c	772	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
mbed_official	532:fe11edbda85c	773	* @brief Force or release AHB2 peripheral reset.
mbed_official	532:fe11edbda85c	774	* @{
mbed_official	235:685d5f11838f	775	*/
mbed_official	532:fe11edbda85c	776	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
mbed_official	532:fe11edbda85c	777	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
mbed_official	532:fe11edbda85c	778
mbed_official	532:fe11edbda85c	779	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
mbed_official	532:fe11edbda85c	780	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
mbed_official	532:fe11edbda85c	781
mbed_official	532:fe11edbda85c	782	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
mbed_official	532:fe11edbda85c	783	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
mbed_official	532:fe11edbda85c	784	/**
mbed_official	532:fe11edbda85c	785	* @}
mbed_official	532:fe11edbda85c	786	*/
mbed_official	532:fe11edbda85c	787
mbed_official	532:fe11edbda85c	788	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
mbed_official	532:fe11edbda85c	789	* @brief Force or release APB1 peripheral reset.
mbed_official	532:fe11edbda85c	790	* @{
mbed_official	532:fe11edbda85c	791	*/
mbed_official	532:fe11edbda85c	792	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	532:fe11edbda85c	793	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	532:fe11edbda85c	794	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	532:fe11edbda85c	795	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	532:fe11edbda85c	796	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
mbed_official	532:fe11edbda85c	797	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	532:fe11edbda85c	798	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	532:fe11edbda85c	799	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	532:fe11edbda85c	800	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	532:fe11edbda85c	801	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	532:fe11edbda85c	802	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	532:fe11edbda85c	803	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
mbed_official	532:fe11edbda85c	804	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	235:685d5f11838f	805
mbed_official	532:fe11edbda85c	806	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	532:fe11edbda85c	807	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	532:fe11edbda85c	808	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	532:fe11edbda85c	809	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	532:fe11edbda85c	810	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official	532:fe11edbda85c	811	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official	532:fe11edbda85c	812	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	532:fe11edbda85c	813	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	532:fe11edbda85c	814	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	532:fe11edbda85c	815	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official	532:fe11edbda85c	816	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	532:fe11edbda85c	817	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
mbed_official	532:fe11edbda85c	818	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official	532:fe11edbda85c	819	/**
mbed_official	532:fe11edbda85c	820	* @}
mbed_official	532:fe11edbda85c	821	*/
mbed_official	235:685d5f11838f	822
mbed_official	532:fe11edbda85c	823	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
mbed_official	532:fe11edbda85c	824	* @brief Force or release APB2 peripheral reset.
mbed_official	532:fe11edbda85c	825	* @{
mbed_official	235:685d5f11838f	826	*/
mbed_official	532:fe11edbda85c	827	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	532:fe11edbda85c	828	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	532:fe11edbda85c	829	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	532:fe11edbda85c	830	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
mbed_official	532:fe11edbda85c	831	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
mbed_official	532:fe11edbda85c	832	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
mbed_official	532:fe11edbda85c	833	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	532:fe11edbda85c	834	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
mbed_official	532:fe11edbda85c	835	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	532:fe11edbda85c	836	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
mbed_official	532:fe11edbda85c	837	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
mbed_official	532:fe11edbda85c	838	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
mbed_official	235:685d5f11838f	839
mbed_official	532:fe11edbda85c	840	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	532:fe11edbda85c	841	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	532:fe11edbda85c	842	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official	532:fe11edbda85c	843	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official	532:fe11edbda85c	844	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
mbed_official	532:fe11edbda85c	845	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
mbed_official	532:fe11edbda85c	846	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	532:fe11edbda85c	847	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
mbed_official	532:fe11edbda85c	848	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
mbed_official	532:fe11edbda85c	849	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
mbed_official	532:fe11edbda85c	850	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
mbed_official	532:fe11edbda85c	851	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
mbed_official	532:fe11edbda85c	852	/**
mbed_official	532:fe11edbda85c	853	* @}
mbed_official	532:fe11edbda85c	854	*/
mbed_official	235:685d5f11838f	855
mbed_official	532:fe11edbda85c	856	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
mbed_official	532:fe11edbda85c	857	* @brief Force or release AHB3 peripheral reset.
mbed_official	532:fe11edbda85c	858	* @{
mbed_official	532:fe11edbda85c	859	*/
mbed_official	532:fe11edbda85c	860	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
mbed_official	532:fe11edbda85c	861	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
mbed_official	532:fe11edbda85c	862	/**
mbed_official	532:fe11edbda85c	863	* @}
mbed_official	532:fe11edbda85c	864	*/
mbed_official	235:685d5f11838f	865
mbed_official	532:fe11edbda85c	866	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
mbed_official	532:fe11edbda85c	867	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	868	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	869	* power consumption.
mbed_official	532:fe11edbda85c	870	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	871	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	872	* @{
mbed_official	235:685d5f11838f	873	*/
mbed_official	532:fe11edbda85c	874	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
mbed_official	532:fe11edbda85c	875	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
mbed_official	532:fe11edbda85c	876	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
mbed_official	532:fe11edbda85c	877	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
mbed_official	532:fe11edbda85c	878	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
mbed_official	532:fe11edbda85c	879	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
mbed_official	532:fe11edbda85c	880	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
mbed_official	532:fe11edbda85c	881	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
mbed_official	532:fe11edbda85c	882	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
mbed_official	532:fe11edbda85c	883	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official	532:fe11edbda85c	884	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
mbed_official	532:fe11edbda85c	885	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
mbed_official	235:685d5f11838f	886
mbed_official	532:fe11edbda85c	887	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
mbed_official	532:fe11edbda85c	888	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
mbed_official	532:fe11edbda85c	889	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
mbed_official	532:fe11edbda85c	890	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
mbed_official	532:fe11edbda85c	891	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
mbed_official	532:fe11edbda85c	892	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
mbed_official	532:fe11edbda85c	893	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
mbed_official	532:fe11edbda85c	894	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
mbed_official	532:fe11edbda85c	895	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
mbed_official	532:fe11edbda85c	896	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
mbed_official	532:fe11edbda85c	897	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
mbed_official	532:fe11edbda85c	898	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
mbed_official	532:fe11edbda85c	899	/**
mbed_official	532:fe11edbda85c	900	* @}
mbed_official	532:fe11edbda85c	901	*/
mbed_official	235:685d5f11838f	902
mbed_official	532:fe11edbda85c	903	/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
mbed_official	532:fe11edbda85c	904	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	905	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	906	* power consumption.
mbed_official	532:fe11edbda85c	907	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	908	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	909	* @{
mbed_official	235:685d5f11838f	910	*/
mbed_official	532:fe11edbda85c	911	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
mbed_official	235:685d5f11838f	912
mbed_official	532:fe11edbda85c	913	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
mbed_official	235:685d5f11838f	914
mbed_official	532:fe11edbda85c	915	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
mbed_official	532:fe11edbda85c	916	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
mbed_official	532:fe11edbda85c	917	/**
mbed_official	532:fe11edbda85c	918	* @}
mbed_official	532:fe11edbda85c	919	*/
mbed_official	235:685d5f11838f	920
mbed_official	532:fe11edbda85c	921	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
mbed_official	532:fe11edbda85c	922	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	923	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	924	* power consumption.
mbed_official	532:fe11edbda85c	925	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	926	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	927	* @{
mbed_official	235:685d5f11838f	928	*/
mbed_official	532:fe11edbda85c	929	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
mbed_official	532:fe11edbda85c	930	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
mbed_official	532:fe11edbda85c	931	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
mbed_official	532:fe11edbda85c	932	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
mbed_official	532:fe11edbda85c	933	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
mbed_official	532:fe11edbda85c	934	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
mbed_official	532:fe11edbda85c	935	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
mbed_official	532:fe11edbda85c	936	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
mbed_official	532:fe11edbda85c	937	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
mbed_official	532:fe11edbda85c	938	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
mbed_official	532:fe11edbda85c	939	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
mbed_official	532:fe11edbda85c	940	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
mbed_official	235:685d5f11838f	941
mbed_official	532:fe11edbda85c	942	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
mbed_official	532:fe11edbda85c	943	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
mbed_official	532:fe11edbda85c	944	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
mbed_official	532:fe11edbda85c	945	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
mbed_official	532:fe11edbda85c	946	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
mbed_official	532:fe11edbda85c	947	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
mbed_official	532:fe11edbda85c	948	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
mbed_official	532:fe11edbda85c	949	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
mbed_official	532:fe11edbda85c	950	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
mbed_official	532:fe11edbda85c	951	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
mbed_official	532:fe11edbda85c	952	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
mbed_official	532:fe11edbda85c	953	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
mbed_official	532:fe11edbda85c	954	/**
mbed_official	532:fe11edbda85c	955	* @}
mbed_official	532:fe11edbda85c	956	*/
mbed_official	235:685d5f11838f	957
mbed_official	532:fe11edbda85c	958	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
mbed_official	532:fe11edbda85c	959	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	235:685d5f11838f	960	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	235:685d5f11838f	961	* power consumption.
mbed_official	532:fe11edbda85c	962	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
mbed_official	235:685d5f11838f	963	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	532:fe11edbda85c	964	* @{
mbed_official	235:685d5f11838f	965	*/
mbed_official	532:fe11edbda85c	966	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
mbed_official	532:fe11edbda85c	967	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
mbed_official	532:fe11edbda85c	968	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
mbed_official	532:fe11edbda85c	969	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
mbed_official	532:fe11edbda85c	970	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
mbed_official	532:fe11edbda85c	971	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
mbed_official	532:fe11edbda85c	972	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
mbed_official	532:fe11edbda85c	973	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	532:fe11edbda85c	974	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
mbed_official	532:fe11edbda85c	975	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
mbed_official	532:fe11edbda85c	976	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
mbed_official	235:685d5f11838f	977
mbed_official	532:fe11edbda85c	978	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
mbed_official	532:fe11edbda85c	979	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
mbed_official	532:fe11edbda85c	980	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
mbed_official	532:fe11edbda85c	981	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
mbed_official	532:fe11edbda85c	982	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
mbed_official	532:fe11edbda85c	983	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
mbed_official	532:fe11edbda85c	984	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
mbed_official	532:fe11edbda85c	985	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
mbed_official	532:fe11edbda85c	986	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
mbed_official	532:fe11edbda85c	987	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
mbed_official	532:fe11edbda85c	988	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
mbed_official	532:fe11edbda85c	989	/**
mbed_official	532:fe11edbda85c	990	* @}
mbed_official	532:fe11edbda85c	991	*/
mbed_official	235:685d5f11838f	992
mbed_official	532:fe11edbda85c	993	/** @defgroup RCC_HSI_Configuration HSI Configuration
mbed_official	532:fe11edbda85c	994	* @{
mbed_official	532:fe11edbda85c	995	*/
mbed_official	532:fe11edbda85c	996
mbed_official	235:685d5f11838f	997	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	235:685d5f11838f	998	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	999	* It is used (enabled by hardware) as system clock source after startup
mbed_official	532:fe11edbda85c	1000	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
mbed_official	235:685d5f11838f	1001	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	235:685d5f11838f	1002	* Security System CSS is enabled).
mbed_official	235:685d5f11838f	1003	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	235:685d5f11838f	1004	* you have to select another source of the system clock then stop the HSI.
mbed_official	235:685d5f11838f	1005	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	235:685d5f11838f	1006	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	235:685d5f11838f	1007	* system clock source.
mbed_official	235:685d5f11838f	1008	* This parameter can be: ENABLE or DISABLE.
mbed_official	235:685d5f11838f	1009	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	235:685d5f11838f	1010	* clock cycles.
mbed_official	235:685d5f11838f	1011	*/
mbed_official	532:fe11edbda85c	1012	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
mbed_official	532:fe11edbda85c	1013	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
mbed_official	235:685d5f11838f	1014
mbed_official	235:685d5f11838f	1015	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	235:685d5f11838f	1016	* @note The calibration is used to compensate for the variations in voltage
mbed_official	235:685d5f11838f	1017	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	235:685d5f11838f	1018	* @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official	235:685d5f11838f	1019	* This parameter must be a number between 0 and 0x1F.
mbed_official	235:685d5f11838f	1020	*/
mbed_official	235:685d5f11838f	1021	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
mbed_official	235:685d5f11838f	1022	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
mbed_official	532:fe11edbda85c	1023	/**
mbed_official	532:fe11edbda85c	1024	* @}
mbed_official	532:fe11edbda85c	1025	*/
mbed_official	532:fe11edbda85c	1026
mbed_official	532:fe11edbda85c	1027	/** @defgroup RCC_LSI_Configuration LSI Configuration
mbed_official	532:fe11edbda85c	1028	* @{
mbed_official	532:fe11edbda85c	1029	*/
mbed_official	235:685d5f11838f	1030
mbed_official	235:685d5f11838f	1031	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	235:685d5f11838f	1032	* @note After enabling the LSI, the application software should wait on
mbed_official	235:685d5f11838f	1033	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	235:685d5f11838f	1034	* be used to clock the IWDG and/or the RTC.
mbed_official	235:685d5f11838f	1035	* @note LSI can not be disabled if the IWDG is running.
mbed_official	235:685d5f11838f	1036	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	235:685d5f11838f	1037	* clock cycles.
mbed_official	235:685d5f11838f	1038	*/
mbed_official	532:fe11edbda85c	1039	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
mbed_official	532:fe11edbda85c	1040	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
mbed_official	532:fe11edbda85c	1041	/**
mbed_official	532:fe11edbda85c	1042	* @}
mbed_official	532:fe11edbda85c	1043	*/
mbed_official	532:fe11edbda85c	1044
mbed_official	532:fe11edbda85c	1045	/** @defgroup RCC_HSE_Configuration HSE Configuration
mbed_official	532:fe11edbda85c	1046	* @{
mbed_official	532:fe11edbda85c	1047	*/
mbed_official	235:685d5f11838f	1048
mbed_official	235:685d5f11838f	1049	/**
mbed_official	235:685d5f11838f	1050	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	532:fe11edbda85c	1051	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
mbed_official	532:fe11edbda85c	1052	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
mbed_official	235:685d5f11838f	1053	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	235:685d5f11838f	1054	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	235:685d5f11838f	1055	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	235:685d5f11838f	1056	* @note HSE state can not be changed if it is used directly or through the
mbed_official	235:685d5f11838f	1057	* PLL as system clock. In this case, you have to select another source
mbed_official	235:685d5f11838f	1058	* of the system clock then change the HSE state (ex. disable it).
mbed_official	235:685d5f11838f	1059	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	1060	* @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official	235:685d5f11838f	1061	* was previously enabled you have to enable it again after calling this
mbed_official	235:685d5f11838f	1062	* function.
mbed_official	235:685d5f11838f	1063	* @param __STATE__: specifies the new state of the HSE.
mbed_official	235:685d5f11838f	1064	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1065	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	235:685d5f11838f	1066	* 6 HSE oscillator clock cycles.
mbed_official	235:685d5f11838f	1067	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official	235:685d5f11838f	1068	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official	235:685d5f11838f	1069	*/
mbed_official	532:fe11edbda85c	1070	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__))
mbed_official	532:fe11edbda85c	1071	/**
mbed_official	532:fe11edbda85c	1072	* @}
mbed_official	532:fe11edbda85c	1073	*/
mbed_official	532:fe11edbda85c	1074
mbed_official	532:fe11edbda85c	1075	/** @defgroup RCC_LSE_Configuration LSE Configuration
mbed_official	532:fe11edbda85c	1076	* @{
mbed_official	532:fe11edbda85c	1077	*/
mbed_official	235:685d5f11838f	1078
mbed_official	235:685d5f11838f	1079	/**
mbed_official	235:685d5f11838f	1080	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	532:fe11edbda85c	1081	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
mbed_official	532:fe11edbda85c	1082	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
mbed_official	235:685d5f11838f	1083	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	235:685d5f11838f	1084	* this domain after reset, you have to enable write access using
mbed_official	235:685d5f11838f	1085	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	235:685d5f11838f	1086	* (to be done once after reset).
mbed_official	235:685d5f11838f	1087	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	235:685d5f11838f	1088	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	235:685d5f11838f	1089	* is stable and can be used to clock the RTC.
mbed_official	235:685d5f11838f	1090	* @param __STATE__: specifies the new state of the LSE.
mbed_official	235:685d5f11838f	1091	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1092	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	235:685d5f11838f	1093	* 6 LSE oscillator clock cycles.
mbed_official	235:685d5f11838f	1094	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	235:685d5f11838f	1095	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	235:685d5f11838f	1096	*/
mbed_official	532:fe11edbda85c	1097	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
mbed_official	532:fe11edbda85c	1098
mbed_official	532:fe11edbda85c	1099	/**
mbed_official	532:fe11edbda85c	1100	* @}
mbed_official	532:fe11edbda85c	1101	*/
mbed_official	235:685d5f11838f	1102
mbed_official	532:fe11edbda85c	1103	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
mbed_official	532:fe11edbda85c	1104	* @{
mbed_official	532:fe11edbda85c	1105	*/
mbed_official	532:fe11edbda85c	1106
mbed_official	532:fe11edbda85c	1107	/** @brief Macros to enable or disable the RTC clock.
mbed_official	235:685d5f11838f	1108	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	235:685d5f11838f	1109	*/
mbed_official	532:fe11edbda85c	1110	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
mbed_official	532:fe11edbda85c	1111	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
mbed_official	235:685d5f11838f	1112
mbed_official	235:685d5f11838f	1113	/** @brief Macros to configure the RTC clock (RTCCLK).
mbed_official	235:685d5f11838f	1114	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	235:685d5f11838f	1115	* access is denied to this domain after reset, you have to enable write
mbed_official	235:685d5f11838f	1116	* access using the Power Backup Access macro before to configure
mbed_official	235:685d5f11838f	1117	* the RTC clock source (to be done once after reset).
mbed_official	235:685d5f11838f	1118	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	235:685d5f11838f	1119	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
mbed_official	235:685d5f11838f	1120	* a Power On Reset (POR).
mbed_official	235:685d5f11838f	1121	* @param __RTCCLKSource__: specifies the RTC clock source.
mbed_official	235:685d5f11838f	1122	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1123	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
mbed_official	235:685d5f11838f	1124	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
mbed_official	235:685d5f11838f	1125	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
mbed_official	235:685d5f11838f	1126	* as RTC clock, where x:[2,31]
mbed_official	235:685d5f11838f	1127	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	532:fe11edbda85c	1128	* work in STOP and STANDBY modes, and can be used as wake-up source.
mbed_official	235:685d5f11838f	1129	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	235:685d5f11838f	1130	* cannot be used in STOP and STANDBY modes.
mbed_official	235:685d5f11838f	1131	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	235:685d5f11838f	1132	* RTC clock source).
mbed_official	235:685d5f11838f	1133	*/
mbed_official	235:685d5f11838f	1134	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
mbed_official	235:685d5f11838f	1135	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
mbed_official	235:685d5f11838f	1136
mbed_official	235:685d5f11838f	1137	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
mbed_official	235:685d5f11838f	1138	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
mbed_official	235:685d5f11838f	1139	} while (0)
mbed_official	235:685d5f11838f	1140
mbed_official	235:685d5f11838f	1141	/** @brief Macros to force or release the Backup domain reset.
mbed_official	235:685d5f11838f	1142	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	235:685d5f11838f	1143	* and the RTC clock source selection in RCC_CSR register.
mbed_official	235:685d5f11838f	1144	* @note The BKPSRAM is not affected by this reset.
mbed_official	235:685d5f11838f	1145	*/
mbed_official	532:fe11edbda85c	1146	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
mbed_official	532:fe11edbda85c	1147	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
mbed_official	532:fe11edbda85c	1148	/**
mbed_official	532:fe11edbda85c	1149	* @}
mbed_official	532:fe11edbda85c	1150	*/
mbed_official	532:fe11edbda85c	1151
mbed_official	532:fe11edbda85c	1152	/** @defgroup RCC_PLL_Configuration PLL Configuration
mbed_official	532:fe11edbda85c	1153	* @{
mbed_official	532:fe11edbda85c	1154	*/
mbed_official	235:685d5f11838f	1155
mbed_official	235:685d5f11838f	1156	/** @brief Macros to enable or disable the main PLL.
mbed_official	235:685d5f11838f	1157	* @note After enabling the main PLL, the application software should wait on
mbed_official	235:685d5f11838f	1158	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	235:685d5f11838f	1159	* be used as system clock source.
mbed_official	235:685d5f11838f	1160	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	235:685d5f11838f	1161	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	1162	*/
mbed_official	532:fe11edbda85c	1163	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
mbed_official	532:fe11edbda85c	1164	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
mbed_official	532:fe11edbda85c	1165	/**
mbed_official	532:fe11edbda85c	1166	* @}
mbed_official	532:fe11edbda85c	1167	*/
mbed_official	235:685d5f11838f	1168
mbed_official	532:fe11edbda85c	1169	/** @brief Macro to configure the PLL clock source.
mbed_official	235:685d5f11838f	1170	* @note This function must be used only when the main PLL is disabled.
mbed_official	532:fe11edbda85c	1171	* @param __PLLSOURCE__: specifies the PLL entry clock source.
mbed_official	235:685d5f11838f	1172	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1173	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	235:685d5f11838f	1174	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	532:fe11edbda85c	1175	*
mbed_official	532:fe11edbda85c	1176	*/
mbed_official	532:fe11edbda85c	1177	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
mbed_official	532:fe11edbda85c	1178
mbed_official	532:fe11edbda85c	1179	/** @brief Macro to configure the PLL multiplication factor.
mbed_official	532:fe11edbda85c	1180	* @note This function must be used only when the main PLL is disabled.
mbed_official	235:685d5f11838f	1181	* @param __PLLM__: specifies the division factor for PLL VCO input clock
mbed_official	235:685d5f11838f	1182	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official	235:685d5f11838f	1183	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
mbed_official	235:685d5f11838f	1184	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official	235:685d5f11838f	1185	* of 2 MHz to limit PLL jitter.
mbed_official	532:fe11edbda85c	1186	*
mbed_official	235:685d5f11838f	1187	*/
mbed_official	532:fe11edbda85c	1188	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
mbed_official	532:fe11edbda85c	1189
mbed_official	532:fe11edbda85c	1190	/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
mbed_official	532:fe11edbda85c	1191	* @{
mbed_official	235:685d5f11838f	1192	*/
mbed_official	235:685d5f11838f	1193
mbed_official	235:685d5f11838f	1194	/** @brief Macros to enable or disable the PLLI2S.
mbed_official	235:685d5f11838f	1195	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	235:685d5f11838f	1196	*/
mbed_official	532:fe11edbda85c	1197	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
mbed_official	532:fe11edbda85c	1198	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
mbed_official	532:fe11edbda85c	1199	/**
mbed_official	532:fe11edbda85c	1200	* @}
mbed_official	532:fe11edbda85c	1201	*/
mbed_official	235:685d5f11838f	1202
mbed_official	532:fe11edbda85c	1203	/** @defgroup RCC_Get_Clock_source Get Clock source
mbed_official	532:fe11edbda85c	1204	* @{
mbed_official	235:685d5f11838f	1205	*/
mbed_official	532:fe11edbda85c	1206	/**
mbed_official	532:fe11edbda85c	1207	* @brief Macro to configure the system clock source.
mbed_official	532:fe11edbda85c	1208	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
mbed_official	532:fe11edbda85c	1209	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	1210	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
mbed_official	532:fe11edbda85c	1211	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
mbed_official	532:fe11edbda85c	1212	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
mbed_official	532:fe11edbda85c	1213	* - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
mbed_official	532:fe11edbda85c	1214	*/
mbed_official	532:fe11edbda85c	1215	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
mbed_official	235:685d5f11838f	1216
mbed_official	235:685d5f11838f	1217	/** @brief Macro to get the clock source used as system clock.
mbed_official	235:685d5f11838f	1218	* @retval The clock source used as system clock. The returned value can be one
mbed_official	235:685d5f11838f	1219	* of the following:
mbed_official	532:fe11edbda85c	1220	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
mbed_official	532:fe11edbda85c	1221	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
mbed_official	532:fe11edbda85c	1222	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
mbed_official	532:fe11edbda85c	1223	* - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
mbed_official	235:685d5f11838f	1224	*/
mbed_official	235:685d5f11838f	1225	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	235:685d5f11838f	1226
mbed_official	235:685d5f11838f	1227	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	235:685d5f11838f	1228	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	235:685d5f11838f	1229	* of the following:
mbed_official	235:685d5f11838f	1230	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	235:685d5f11838f	1231	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	235:685d5f11838f	1232	*/
mbed_official	235:685d5f11838f	1233	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
mbed_official	532:fe11edbda85c	1234	/**
mbed_official	532:fe11edbda85c	1235	* @}
mbed_official	532:fe11edbda85c	1236	*/
mbed_official	532:fe11edbda85c	1237
mbed_official	532:fe11edbda85c	1238	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
mbed_official	532:fe11edbda85c	1239	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	532:fe11edbda85c	1240	* @{
mbed_official	532:fe11edbda85c	1241	*/
mbed_official	235:685d5f11838f	1242
mbed_official	235:685d5f11838f	1243	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
mbed_official	235:685d5f11838f	1244	* the selected interrupts).
mbed_official	235:685d5f11838f	1245	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	235:685d5f11838f	1246	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1247	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1248	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1249	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1250	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1251	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1252	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1253	*/
mbed_official	532:fe11edbda85c	1254	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
mbed_official	235:685d5f11838f	1255
mbed_official	235:685d5f11838f	1256	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
mbed_official	235:685d5f11838f	1257	* the selected interrupts).
mbed_official	235:685d5f11838f	1258	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	235:685d5f11838f	1259	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1260	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1261	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1262	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1263	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1264	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1265	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1266	*/
mbed_official	532:fe11edbda85c	1267	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official	235:685d5f11838f	1268
mbed_official	235:685d5f11838f	1269	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official	235:685d5f11838f	1270	* bits to clear the selected interrupt pending bits.
mbed_official	235:685d5f11838f	1271	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	235:685d5f11838f	1272	* This parameter can be any combination of the following values:
mbed_official	235:685d5f11838f	1273	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1274	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1275	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1276	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1277	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1278	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1279	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	235:685d5f11838f	1280	*/
mbed_official	532:fe11edbda85c	1281	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
mbed_official	235:685d5f11838f	1282
mbed_official	235:685d5f11838f	1283	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	235:685d5f11838f	1284	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	235:685d5f11838f	1285	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1286	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
mbed_official	235:685d5f11838f	1287	* @arg RCC_IT_LSERDY: LSE ready interrupt.
mbed_official	235:685d5f11838f	1288	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
mbed_official	235:685d5f11838f	1289	* @arg RCC_IT_HSERDY: HSE ready interrupt.
mbed_official	235:685d5f11838f	1290	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
mbed_official	235:685d5f11838f	1291	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
mbed_official	235:685d5f11838f	1292	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	235:685d5f11838f	1293	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	235:685d5f11838f	1294	*/
mbed_official	235:685d5f11838f	1295	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	235:685d5f11838f	1296
mbed_official	235:685d5f11838f	1297	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official	235:685d5f11838f	1298	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
mbed_official	235:685d5f11838f	1299	*/
mbed_official	235:685d5f11838f	1300	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	235:685d5f11838f	1301
mbed_official	235:685d5f11838f	1302	/** @brief Check RCC flag is set or not.
mbed_official	235:685d5f11838f	1303	* @param __FLAG__: specifies the flag to check.
mbed_official	235:685d5f11838f	1304	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1305	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
mbed_official	235:685d5f11838f	1306	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
mbed_official	235:685d5f11838f	1307	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
mbed_official	235:685d5f11838f	1308	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
mbed_official	235:685d5f11838f	1309	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
mbed_official	235:685d5f11838f	1310	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
mbed_official	235:685d5f11838f	1311	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
mbed_official	235:685d5f11838f	1312	* @arg RCC_FLAG_PINRST: Pin reset.
mbed_official	235:685d5f11838f	1313	* @arg RCC_FLAG_PORRST: POR/PDR reset.
mbed_official	235:685d5f11838f	1314	* @arg RCC_FLAG_SFTRST: Software reset.
mbed_official	235:685d5f11838f	1315	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
mbed_official	235:685d5f11838f	1316	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
mbed_official	235:685d5f11838f	1317	* @arg RCC_FLAG_LPWRRST: Low Power reset.
mbed_official	235:685d5f11838f	1318	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	235:685d5f11838f	1319	*/
mbed_official	235:685d5f11838f	1320	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	235:685d5f11838f	1321	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
mbed_official	235:685d5f11838f	1322
mbed_official	532:fe11edbda85c	1323	/**
mbed_official	532:fe11edbda85c	1324	* @}
mbed_official	532:fe11edbda85c	1325	*/
mbed_official	532:fe11edbda85c	1326
mbed_official	532:fe11edbda85c	1327	/**
mbed_official	532:fe11edbda85c	1328	* @}
mbed_official	532:fe11edbda85c	1329	*/
mbed_official	235:685d5f11838f	1330
mbed_official	235:685d5f11838f	1331	/* Exported functions --------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1332	/** @addtogroup RCC_Exported_Functions
mbed_official	532:fe11edbda85c	1333	* @{
mbed_official	532:fe11edbda85c	1334	*/
mbed_official	532:fe11edbda85c	1335
mbed_official	532:fe11edbda85c	1336	/** @addtogroup RCC_Exported_Functions_Group1
mbed_official	532:fe11edbda85c	1337	* @{
mbed_official	532:fe11edbda85c	1338	*/
mbed_official	235:685d5f11838f	1339	/* Initialization and de-initialization functions ******************************/
mbed_official	235:685d5f11838f	1340	void HAL_RCC_DeInit(void);
mbed_official	235:685d5f11838f	1341	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	235:685d5f11838f	1342	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	532:fe11edbda85c	1343	/**
mbed_official	532:fe11edbda85c	1344	* @}
mbed_official	532:fe11edbda85c	1345	*/
mbed_official	235:685d5f11838f	1346
mbed_official	532:fe11edbda85c	1347	/** @addtogroup RCC_Exported_Functions_Group2
mbed_official	532:fe11edbda85c	1348	* @{
mbed_official	532:fe11edbda85c	1349	*/
mbed_official	235:685d5f11838f	1350	/* Peripheral Control functions ************************************************/
mbed_official	235:685d5f11838f	1351	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	235:685d5f11838f	1352	void HAL_RCC_EnableCSS(void);
mbed_official	235:685d5f11838f	1353	void HAL_RCC_DisableCSS(void);
mbed_official	235:685d5f11838f	1354	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	235:685d5f11838f	1355	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	235:685d5f11838f	1356	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	235:685d5f11838f	1357	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	235:685d5f11838f	1358	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	235:685d5f11838f	1359	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	235:685d5f11838f	1360
mbed_official	235:685d5f11838f	1361	/* CSS NMI IRQ handler */
mbed_official	235:685d5f11838f	1362	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	235:685d5f11838f	1363
mbed_official	235:685d5f11838f	1364	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	532:fe11edbda85c	1365	void HAL_RCC_CSSCallback(void);
mbed_official	532:fe11edbda85c	1366
mbed_official	532:fe11edbda85c	1367	/**
mbed_official	532:fe11edbda85c	1368	* @}
mbed_official	532:fe11edbda85c	1369	*/
mbed_official	532:fe11edbda85c	1370
mbed_official	532:fe11edbda85c	1371	/**
mbed_official	532:fe11edbda85c	1372	* @}
mbed_official	532:fe11edbda85c	1373	*/
mbed_official	532:fe11edbda85c	1374
mbed_official	532:fe11edbda85c	1375	/* Private types -------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1376	/* Private variables ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1377	/* Private constants ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1378	/** @defgroup RCC_Private_Constants RCC Private Constants
mbed_official	532:fe11edbda85c	1379	* @{
mbed_official	532:fe11edbda85c	1380	*/
mbed_official	532:fe11edbda85c	1381
mbed_official	532:fe11edbda85c	1382	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
mbed_official	532:fe11edbda85c	1383	* @brief RCC registers bit address in the alias region
mbed_official	532:fe11edbda85c	1384	* @{
mbed_official	532:fe11edbda85c	1385	*/
mbed_official	532:fe11edbda85c	1386	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	532:fe11edbda85c	1387	/* --- CR Register ---*/
mbed_official	532:fe11edbda85c	1388	/* Alias word address of HSION bit */
mbed_official	532:fe11edbda85c	1389	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	532:fe11edbda85c	1390	#define RCC_HSION_BIT_NUMBER 0x00
mbed_official	532:fe11edbda85c	1391	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1392	/* Alias word address of CSSON bit */
mbed_official	532:fe11edbda85c	1393	#define RCC_CSSON_BIT_NUMBER 0x13
mbed_official	532:fe11edbda85c	1394	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1395	/* Alias word address of PLLON bit */
mbed_official	532:fe11edbda85c	1396	#define RCC_PLLON_BIT_NUMBER 0x18
mbed_official	532:fe11edbda85c	1397	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1398	/* Alias word address of PLLI2SON bit */
mbed_official	532:fe11edbda85c	1399	#define RCC_PLLI2SON_BIT_NUMBER 0x1A
mbed_official	532:fe11edbda85c	1400	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1401
mbed_official	532:fe11edbda85c	1402	/* --- CFGR Register ---*/
mbed_official	532:fe11edbda85c	1403	/* Alias word address of I2SSRC bit */
mbed_official	532:fe11edbda85c	1404	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
mbed_official	532:fe11edbda85c	1405	#define RCC_I2SSRC_BIT_NUMBER 0x17
mbed_official	532:fe11edbda85c	1406	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1407
mbed_official	532:fe11edbda85c	1408	/* --- BDCR Register ---*/
mbed_official	532:fe11edbda85c	1409	/* Alias word address of RTCEN bit */
mbed_official	532:fe11edbda85c	1410	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
mbed_official	532:fe11edbda85c	1411	#define RCC_RTCEN_BIT_NUMBER 0x0F
mbed_official	532:fe11edbda85c	1412	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1413	/* Alias word address of BDRST bit */
mbed_official	532:fe11edbda85c	1414	#define RCC_BDRST_BIT_NUMBER 0x10
mbed_official	532:fe11edbda85c	1415	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1416
mbed_official	532:fe11edbda85c	1417	/* --- CSR Register ---*/
mbed_official	532:fe11edbda85c	1418	/* Alias word address of LSION bit */
mbed_official	532:fe11edbda85c	1419	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
mbed_official	532:fe11edbda85c	1420	#define RCC_LSION_BIT_NUMBER 0x00
mbed_official	532:fe11edbda85c	1421	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
mbed_official	532:fe11edbda85c	1422
mbed_official	532:fe11edbda85c	1423	/* CR register byte 3 (Bits[23:16]) base address */
mbed_official	532:fe11edbda85c	1424	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
mbed_official	532:fe11edbda85c	1425
mbed_official	532:fe11edbda85c	1426	/* CIR register byte 2 (Bits[15:8]) base address */
mbed_official	532:fe11edbda85c	1427	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
mbed_official	532:fe11edbda85c	1428
mbed_official	532:fe11edbda85c	1429	/* CIR register byte 3 (Bits[23:16]) base address */
mbed_official	532:fe11edbda85c	1430	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
mbed_official	532:fe11edbda85c	1431
mbed_official	532:fe11edbda85c	1432	/* BDCR register base address */
mbed_official	532:fe11edbda85c	1433	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
mbed_official	532:fe11edbda85c	1434
mbed_official	532:fe11edbda85c	1435	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
mbed_official	532:fe11edbda85c	1436	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
mbed_official	532:fe11edbda85c	1437
mbed_official	532:fe11edbda85c	1438	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	532:fe11edbda85c	1439	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	532:fe11edbda85c	1440	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	532:fe11edbda85c	1441
mbed_official	532:fe11edbda85c	1442	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
mbed_official	532:fe11edbda85c	1443	#define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
mbed_official	532:fe11edbda85c	1444	/**
mbed_official	532:fe11edbda85c	1445	* @}
mbed_official	532:fe11edbda85c	1446	*/
mbed_official	532:fe11edbda85c	1447
mbed_official	532:fe11edbda85c	1448	/**
mbed_official	532:fe11edbda85c	1449	* @}
mbed_official	532:fe11edbda85c	1450	*/
mbed_official	532:fe11edbda85c	1451
mbed_official	532:fe11edbda85c	1452	/* Private macros ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1453	/** @addtogroup RCC_Private_Macros RCC Private Macros
mbed_official	532:fe11edbda85c	1454	* @{
mbed_official	532:fe11edbda85c	1455	*/
mbed_official	532:fe11edbda85c	1456
mbed_official	532:fe11edbda85c	1457	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
mbed_official	532:fe11edbda85c	1458	* @{
mbed_official	532:fe11edbda85c	1459	*/
mbed_official	532:fe11edbda85c	1460	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
mbed_official	532:fe11edbda85c	1461
mbed_official	532:fe11edbda85c	1462	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
mbed_official	532:fe11edbda85c	1463	((HSE) == RCC_HSE_BYPASS))
mbed_official	532:fe11edbda85c	1464
mbed_official	532:fe11edbda85c	1465	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
mbed_official	532:fe11edbda85c	1466	((LSE) == RCC_LSE_BYPASS))
mbed_official	532:fe11edbda85c	1467
mbed_official	532:fe11edbda85c	1468	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
mbed_official	532:fe11edbda85c	1469
mbed_official	532:fe11edbda85c	1470	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
mbed_official	532:fe11edbda85c	1471
mbed_official	532:fe11edbda85c	1472	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
mbed_official	532:fe11edbda85c	1473
mbed_official	532:fe11edbda85c	1474	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	532:fe11edbda85c	1475	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	532:fe11edbda85c	1476
mbed_official	532:fe11edbda85c	1477	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	532:fe11edbda85c	1478	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	532:fe11edbda85c	1479	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
mbed_official	532:fe11edbda85c	1480	((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
mbed_official	532:fe11edbda85c	1481
mbed_official	532:fe11edbda85c	1482	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
mbed_official	532:fe11edbda85c	1483
mbed_official	532:fe11edbda85c	1484	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official	532:fe11edbda85c	1485
mbed_official	532:fe11edbda85c	1486	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
mbed_official	532:fe11edbda85c	1487
mbed_official	532:fe11edbda85c	1488	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
mbed_official	532:fe11edbda85c	1489
mbed_official	532:fe11edbda85c	1490	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	532:fe11edbda85c	1491	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	532:fe11edbda85c	1492	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	532:fe11edbda85c	1493	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	532:fe11edbda85c	1494	((HCLK) == RCC_SYSCLK_DIV512))
mbed_official	532:fe11edbda85c	1495
mbed_official	532:fe11edbda85c	1496	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
mbed_official	532:fe11edbda85c	1497
mbed_official	532:fe11edbda85c	1498	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
mbed_official	532:fe11edbda85c	1499	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
mbed_official	532:fe11edbda85c	1500	((PCLK) == RCC_HCLK_DIV16))
mbed_official	532:fe11edbda85c	1501
mbed_official	532:fe11edbda85c	1502	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
mbed_official	532:fe11edbda85c	1503
mbed_official	532:fe11edbda85c	1504	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
mbed_official	532:fe11edbda85c	1505	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
mbed_official	532:fe11edbda85c	1506
mbed_official	532:fe11edbda85c	1507	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
mbed_official	532:fe11edbda85c	1508	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
mbed_official	532:fe11edbda85c	1509
mbed_official	532:fe11edbda85c	1510	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
mbed_official	532:fe11edbda85c	1511	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
mbed_official	532:fe11edbda85c	1512	((DIV) == RCC_MCODIV_5))
mbed_official	532:fe11edbda85c	1513	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
mbed_official	532:fe11edbda85c	1514
mbed_official	532:fe11edbda85c	1515	/**
mbed_official	532:fe11edbda85c	1516	* @}
mbed_official	532:fe11edbda85c	1517	*/
mbed_official	532:fe11edbda85c	1518
mbed_official	532:fe11edbda85c	1519	/**
mbed_official	532:fe11edbda85c	1520	* @}
mbed_official	532:fe11edbda85c	1521	*/
mbed_official	235:685d5f11838f	1522
mbed_official	235:685d5f11838f	1523	/**
mbed_official	235:685d5f11838f	1524	* @}
mbed_official	235:685d5f11838f	1525	*/
mbed_official	235:685d5f11838f	1526
mbed_official	235:685d5f11838f	1527	/**
mbed_official	235:685d5f11838f	1528	* @}
mbed_official	235:685d5f11838f	1529	*/
mbed_official	235:685d5f11838f	1530
mbed_official	235:685d5f11838f	1531	#ifdef __cplusplus
mbed_official	235:685d5f11838f	1532	}
mbed_official	235:685d5f11838f	1533	#endif
mbed_official	235:685d5f11838f	1534
mbed_official	235:685d5f11838f	1535	#endif /* __STM32F4xx_HAL_RCC_H */
mbed_official	235:685d5f11838f	1536
mbed_official	235:685d5f11838f	1537	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	27 Oct 2015
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Commits:	637
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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h@613:bc40b8d2aec4, 2015-08-20 (annotated)

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