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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_i2s_ex.c@613:bc40b8d2aec4, 2015-08-20 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Aug 20 10:45:13 2015 +0100
- Revision:
- 613:bc40b8d2aec4
- Parent:
- 532:fe11edbda85c
Synchronized with git revision 92ca8c7b60a283b6bb60eb65b183dac1599f0ade
Full URL: https://github.com/mbedmicro/mbed/commit/92ca8c7b60a283b6bb60eb65b183dac1599f0ade/
Nordic: update application start address in GCC linker script
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 87:085cde657901 | 1 | /** |
| mbed_official | 87:085cde657901 | 2 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 3 | * @file stm32f4xx_hal_i2s_ex.c |
| mbed_official | 87:085cde657901 | 4 | * @author MCD Application Team |
| mbed_official | 613:bc40b8d2aec4 | 5 | * @version V1.3.2 |
| mbed_official | 613:bc40b8d2aec4 | 6 | * @date 26-June-2015 |
| mbed_official | 87:085cde657901 | 7 | * @brief I2S HAL module driver. |
| mbed_official | 87:085cde657901 | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 87:085cde657901 | 9 | * functionalities of I2S extension peripheral: |
| mbed_official | 87:085cde657901 | 10 | * + Extension features Functions |
| mbed_official | 87:085cde657901 | 11 | * |
| mbed_official | 87:085cde657901 | 12 | @verbatim |
| mbed_official | 87:085cde657901 | 13 | ============================================================================== |
| mbed_official | 87:085cde657901 | 14 | ##### I2S Extension features ##### |
| mbed_official | 87:085cde657901 | 15 | ============================================================================== |
| mbed_official | 87:085cde657901 | 16 | [..] |
| mbed_official | 87:085cde657901 | 17 | (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving |
| mbed_official | 87:085cde657901 | 18 | data simultaneously using two data lines. Each SPI peripheral has an extended block |
| mbed_official | 226:b062af740e40 | 19 | called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3). |
| mbed_official | 87:085cde657901 | 20 | (#) The extension block is not a full SPI IP, it is used only as I2S slave to |
| mbed_official | 87:085cde657901 | 21 | implement full duplex mode. The extension block uses the same clock sources |
| mbed_official | 87:085cde657901 | 22 | as its master. |
| mbed_official | 87:085cde657901 | 23 | |
| mbed_official | 87:085cde657901 | 24 | (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers. |
| mbed_official | 87:085cde657901 | 25 | |
| mbed_official | 226:b062af740e40 | 26 | [..] |
| mbed_official | 226:b062af740e40 | 27 | (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where |
| mbed_official | 87:085cde657901 | 28 | I2Sx can be I2S2 or I2S3. |
| mbed_official | 87:085cde657901 | 29 | |
| mbed_official | 87:085cde657901 | 30 | ##### How to use this driver ##### |
| mbed_official | 87:085cde657901 | 31 | =============================================================================== |
| mbed_official | 87:085cde657901 | 32 | [..] |
| mbed_official | 226:b062af740e40 | 33 | Three operation modes are available within this driver : |
| mbed_official | 87:085cde657901 | 34 | |
| mbed_official | 87:085cde657901 | 35 | *** Polling mode IO operation *** |
| mbed_official | 87:085cde657901 | 36 | ================================= |
| mbed_official | 87:085cde657901 | 37 | [..] |
| mbed_official | 87:085cde657901 | 38 | (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive() |
| mbed_official | 87:085cde657901 | 39 | |
| mbed_official | 87:085cde657901 | 40 | *** Interrupt mode IO operation *** |
| mbed_official | 87:085cde657901 | 41 | =================================== |
| mbed_official | 87:085cde657901 | 42 | [..] |
| mbed_official | 87:085cde657901 | 43 | (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT() |
| mbed_official | 87:085cde657901 | 44 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 45 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
| mbed_official | 87:085cde657901 | 46 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 47 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
| mbed_official | 87:085cde657901 | 48 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 49 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
| mbed_official | 87:085cde657901 | 50 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 51 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
| mbed_official | 87:085cde657901 | 52 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
| mbed_official | 87:085cde657901 | 53 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
| mbed_official | 87:085cde657901 | 54 | |
| mbed_official | 87:085cde657901 | 55 | *** DMA mode IO operation *** |
| mbed_official | 87:085cde657901 | 56 | ============================== |
| mbed_official | 87:085cde657901 | 57 | [..] |
| mbed_official | 87:085cde657901 | 58 | (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA() |
| mbed_official | 87:085cde657901 | 59 | (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 60 | add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback |
| mbed_official | 87:085cde657901 | 61 | (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 62 | add his own code by customization of function pointer HAL_I2S_TxCpltCallback |
| mbed_official | 87:085cde657901 | 63 | (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 64 | add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback |
| mbed_official | 87:085cde657901 | 65 | (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can |
| mbed_official | 87:085cde657901 | 66 | add his own code by customization of function pointer HAL_I2S_RxCpltCallback |
| mbed_official | 87:085cde657901 | 67 | (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can |
| mbed_official | 87:085cde657901 | 68 | add his own code by customization of function pointer HAL_I2S_ErrorCallback |
| mbed_official | 87:085cde657901 | 69 | (+) Pause the DMA Transfer using HAL_I2S_DMAPause() |
| mbed_official | 87:085cde657901 | 70 | (+) Resume the DMA Transfer using HAL_I2S_DMAResume() |
| mbed_official | 87:085cde657901 | 71 | (+) Stop the DMA Transfer using HAL_I2S_DMAStop() |
| mbed_official | 87:085cde657901 | 72 | |
| mbed_official | 87:085cde657901 | 73 | @endverbatim |
| mbed_official | 87:085cde657901 | 74 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 75 | * @attention |
| mbed_official | 87:085cde657901 | 76 | * |
| mbed_official | 532:fe11edbda85c | 77 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 87:085cde657901 | 78 | * |
| mbed_official | 87:085cde657901 | 79 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 87:085cde657901 | 80 | * are permitted provided that the following conditions are met: |
| mbed_official | 87:085cde657901 | 81 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 87:085cde657901 | 82 | * this list of conditions and the following disclaimer. |
| mbed_official | 87:085cde657901 | 83 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 87:085cde657901 | 84 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 87:085cde657901 | 85 | * and/or other materials provided with the distribution. |
| mbed_official | 87:085cde657901 | 86 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 87:085cde657901 | 87 | * may be used to endorse or promote products derived from this software |
| mbed_official | 87:085cde657901 | 88 | * without specific prior written permission. |
| mbed_official | 87:085cde657901 | 89 | * |
| mbed_official | 87:085cde657901 | 90 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 87:085cde657901 | 91 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 87:085cde657901 | 92 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 87:085cde657901 | 93 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 87:085cde657901 | 94 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 87:085cde657901 | 95 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 87:085cde657901 | 96 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 87:085cde657901 | 97 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 87:085cde657901 | 98 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 87:085cde657901 | 99 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 87:085cde657901 | 100 | * |
| mbed_official | 87:085cde657901 | 101 | ****************************************************************************** |
| mbed_official | 87:085cde657901 | 102 | */ |
| mbed_official | 87:085cde657901 | 103 | |
| mbed_official | 87:085cde657901 | 104 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 105 | #include "stm32f4xx_hal.h" |
| mbed_official | 87:085cde657901 | 106 | |
| mbed_official | 87:085cde657901 | 107 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 87:085cde657901 | 108 | * @{ |
| mbed_official | 87:085cde657901 | 109 | */ |
| mbed_official | 87:085cde657901 | 110 | |
| mbed_official | 532:fe11edbda85c | 111 | /** @defgroup I2SEx I2SEx |
| mbed_official | 87:085cde657901 | 112 | * @brief I2S HAL module driver |
| mbed_official | 87:085cde657901 | 113 | * @{ |
| mbed_official | 87:085cde657901 | 114 | */ |
| mbed_official | 87:085cde657901 | 115 | |
| mbed_official | 87:085cde657901 | 116 | #ifdef HAL_I2S_MODULE_ENABLED |
| mbed_official | 87:085cde657901 | 117 | |
| mbed_official | 532:fe11edbda85c | 118 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| mbed_official | 532:fe11edbda85c | 119 | defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
| mbed_official | 532:fe11edbda85c | 120 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| mbed_official | 532:fe11edbda85c | 121 | |
| mbed_official | 87:085cde657901 | 122 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 123 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 124 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 125 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 126 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 87:085cde657901 | 127 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 128 | /** @addtogroup I2SEx_Private_Functions |
| mbed_official | 532:fe11edbda85c | 129 | * @{ |
| mbed_official | 532:fe11edbda85c | 130 | */ |
| mbed_official | 532:fe11edbda85c | 131 | /** |
| mbed_official | 532:fe11edbda85c | 132 | * @} |
| mbed_official | 532:fe11edbda85c | 133 | */ |
| mbed_official | 87:085cde657901 | 134 | |
| mbed_official | 532:fe11edbda85c | 135 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 136 | /** @defgroup I2SEx_Exported_Functions I2S Exported Functions |
| mbed_official | 87:085cde657901 | 137 | * @{ |
| mbed_official | 87:085cde657901 | 138 | */ |
| mbed_official | 87:085cde657901 | 139 | |
| mbed_official | 87:085cde657901 | 140 | /** @defgroup I2SEx_Group1 Extension features functions |
| mbed_official | 87:085cde657901 | 141 | * @brief Extension features functions |
| mbed_official | 87:085cde657901 | 142 | * |
| mbed_official | 87:085cde657901 | 143 | @verbatim |
| mbed_official | 87:085cde657901 | 144 | =============================================================================== |
| mbed_official | 87:085cde657901 | 145 | ##### Extension features Functions ##### |
| mbed_official | 87:085cde657901 | 146 | =============================================================================== |
| mbed_official | 87:085cde657901 | 147 | [..] |
| mbed_official | 87:085cde657901 | 148 | This subsection provides a set of functions allowing to manage the I2S data |
| mbed_official | 87:085cde657901 | 149 | transfers. |
| mbed_official | 87:085cde657901 | 150 | |
| mbed_official | 226:b062af740e40 | 151 | (#) There are two modes of transfer: |
| mbed_official | 87:085cde657901 | 152 | (++) Blocking mode : The communication is performed in the polling mode. |
| mbed_official | 87:085cde657901 | 153 | The status of all data processing is returned by the same function |
| mbed_official | 87:085cde657901 | 154 | after finishing transfer. |
| mbed_official | 87:085cde657901 | 155 | (++) No-Blocking mode : The communication is performed using Interrupts |
| mbed_official | 87:085cde657901 | 156 | or DMA. These functions return the status of the transfer startup. |
| mbed_official | 87:085cde657901 | 157 | The end of the data processing will be indicated through the |
| mbed_official | 87:085cde657901 | 158 | dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when |
| mbed_official | 87:085cde657901 | 159 | using DMA mode. |
| mbed_official | 87:085cde657901 | 160 | |
| mbed_official | 87:085cde657901 | 161 | (#) Blocking mode functions are : |
| mbed_official | 87:085cde657901 | 162 | (++) HAL_I2S_TransmitReceive() |
| mbed_official | 87:085cde657901 | 163 | |
| mbed_official | 87:085cde657901 | 164 | (#) No-Blocking mode functions with Interrupt are : |
| mbed_official | 87:085cde657901 | 165 | (++) HAL_I2S_TransmitReceive_IT() |
| mbed_official | 87:085cde657901 | 166 | |
| mbed_official | 87:085cde657901 | 167 | (#) No-Blocking mode functions with DMA are : |
| mbed_official | 87:085cde657901 | 168 | (++) HAL_I2S_TransmitReceive_DMA() |
| mbed_official | 87:085cde657901 | 169 | |
| mbed_official | 226:b062af740e40 | 170 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
| mbed_official | 87:085cde657901 | 171 | (++) HAL_I2S_TxCpltCallback() |
| mbed_official | 87:085cde657901 | 172 | (++) HAL_I2S_RxCpltCallback() |
| mbed_official | 87:085cde657901 | 173 | (++) HAL_I2S_ErrorCallback() |
| mbed_official | 87:085cde657901 | 174 | |
| mbed_official | 87:085cde657901 | 175 | @endverbatim |
| mbed_official | 87:085cde657901 | 176 | * @{ |
| mbed_official | 87:085cde657901 | 177 | */ |
| mbed_official | 532:fe11edbda85c | 178 | /** |
| mbed_official | 532:fe11edbda85c | 179 | * @brief Initializes the I2S according to the specified parameters |
| mbed_official | 532:fe11edbda85c | 180 | * in the I2S_InitTypeDef and create the associated handle. |
| mbed_official | 532:fe11edbda85c | 181 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 182 | * the configuration information for I2S module |
| mbed_official | 532:fe11edbda85c | 183 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 184 | */ |
| mbed_official | 532:fe11edbda85c | 185 | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) |
| mbed_official | 532:fe11edbda85c | 186 | { |
| mbed_official | 532:fe11edbda85c | 187 | uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; |
| mbed_official | 532:fe11edbda85c | 188 | uint32_t tmp = 0, i2sclk = 0; |
| mbed_official | 532:fe11edbda85c | 189 | |
| mbed_official | 532:fe11edbda85c | 190 | /* Check the I2S handle allocation */ |
| mbed_official | 613:bc40b8d2aec4 | 191 | if(hi2s == NULL) |
| mbed_official | 532:fe11edbda85c | 192 | { |
| mbed_official | 532:fe11edbda85c | 193 | return HAL_ERROR; |
| mbed_official | 532:fe11edbda85c | 194 | } |
| mbed_official | 532:fe11edbda85c | 195 | |
| mbed_official | 532:fe11edbda85c | 196 | /* Check the I2S parameters */ |
| mbed_official | 532:fe11edbda85c | 197 | assert_param(IS_I2S_MODE(hi2s->Init.Mode)); |
| mbed_official | 532:fe11edbda85c | 198 | assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); |
| mbed_official | 532:fe11edbda85c | 199 | assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); |
| mbed_official | 532:fe11edbda85c | 200 | assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); |
| mbed_official | 532:fe11edbda85c | 201 | assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); |
| mbed_official | 532:fe11edbda85c | 202 | assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); |
| mbed_official | 532:fe11edbda85c | 203 | assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); |
| mbed_official | 532:fe11edbda85c | 204 | |
| mbed_official | 532:fe11edbda85c | 205 | if(hi2s->State == HAL_I2S_STATE_RESET) |
| mbed_official | 532:fe11edbda85c | 206 | { |
| mbed_official | 532:fe11edbda85c | 207 | /* Allocate lock resource and initialize it */ |
| mbed_official | 532:fe11edbda85c | 208 | hi2s->Lock = HAL_UNLOCKED; |
| mbed_official | 532:fe11edbda85c | 209 | /* Init the low level hardware : GPIO, CLOCK, CORTEX */ |
| mbed_official | 532:fe11edbda85c | 210 | HAL_I2S_MspInit(hi2s); |
| mbed_official | 532:fe11edbda85c | 211 | } |
| mbed_official | 532:fe11edbda85c | 212 | |
| mbed_official | 532:fe11edbda85c | 213 | hi2s->State = HAL_I2S_STATE_BUSY; |
| mbed_official | 532:fe11edbda85c | 214 | |
| mbed_official | 532:fe11edbda85c | 215 | /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/ |
| mbed_official | 532:fe11edbda85c | 216 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ |
| mbed_official | 532:fe11edbda85c | 217 | hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ |
| mbed_official | 532:fe11edbda85c | 218 | SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ |
| mbed_official | 532:fe11edbda85c | 219 | SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); |
| mbed_official | 532:fe11edbda85c | 220 | hi2s->Instance->I2SPR = 0x0002; |
| mbed_official | 532:fe11edbda85c | 221 | |
| mbed_official | 532:fe11edbda85c | 222 | /* Get the I2SCFGR register value */ |
| mbed_official | 532:fe11edbda85c | 223 | tmpreg = hi2s->Instance->I2SCFGR; |
| mbed_official | 532:fe11edbda85c | 224 | |
| mbed_official | 532:fe11edbda85c | 225 | /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */ |
| mbed_official | 532:fe11edbda85c | 226 | /* If the requested audio frequency is not the default, compute the prescaler */ |
| mbed_official | 532:fe11edbda85c | 227 | if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) |
| mbed_official | 532:fe11edbda85c | 228 | { |
| mbed_official | 532:fe11edbda85c | 229 | /* Check the frame length (For the Prescaler computing) *******************/ |
| mbed_official | 532:fe11edbda85c | 230 | if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) |
| mbed_official | 532:fe11edbda85c | 231 | { |
| mbed_official | 532:fe11edbda85c | 232 | /* Packet length is 32 bits */ |
| mbed_official | 532:fe11edbda85c | 233 | packetlength = 2; |
| mbed_official | 532:fe11edbda85c | 234 | } |
| mbed_official | 532:fe11edbda85c | 235 | |
| mbed_official | 532:fe11edbda85c | 236 | /* Get I2S source Clock frequency ****************************************/ |
| mbed_official | 532:fe11edbda85c | 237 | i2sclk = I2S_GetInputClock(hi2s); |
| mbed_official | 532:fe11edbda85c | 238 | |
| mbed_official | 532:fe11edbda85c | 239 | /* Compute the Real divider depending on the MCLK output state, with a floating point */ |
| mbed_official | 532:fe11edbda85c | 240 | if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) |
| mbed_official | 532:fe11edbda85c | 241 | { |
| mbed_official | 532:fe11edbda85c | 242 | /* MCLK output is enabled */ |
| mbed_official | 532:fe11edbda85c | 243 | tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); |
| mbed_official | 532:fe11edbda85c | 244 | } |
| mbed_official | 532:fe11edbda85c | 245 | else |
| mbed_official | 532:fe11edbda85c | 246 | { |
| mbed_official | 532:fe11edbda85c | 247 | /* MCLK output is disabled */ |
| mbed_official | 532:fe11edbda85c | 248 | tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); |
| mbed_official | 532:fe11edbda85c | 249 | } |
| mbed_official | 532:fe11edbda85c | 250 | |
| mbed_official | 532:fe11edbda85c | 251 | /* Remove the flatting point */ |
| mbed_official | 532:fe11edbda85c | 252 | tmp = tmp / 10; |
| mbed_official | 532:fe11edbda85c | 253 | |
| mbed_official | 532:fe11edbda85c | 254 | /* Check the parity of the divider */ |
| mbed_official | 532:fe11edbda85c | 255 | i2sodd = (uint32_t)(tmp & (uint32_t)1); |
| mbed_official | 532:fe11edbda85c | 256 | |
| mbed_official | 532:fe11edbda85c | 257 | /* Compute the i2sdiv prescaler */ |
| mbed_official | 532:fe11edbda85c | 258 | i2sdiv = (uint32_t)((tmp - i2sodd) / 2); |
| mbed_official | 532:fe11edbda85c | 259 | |
| mbed_official | 532:fe11edbda85c | 260 | /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ |
| mbed_official | 532:fe11edbda85c | 261 | i2sodd = (uint32_t) (i2sodd << 8); |
| mbed_official | 532:fe11edbda85c | 262 | } |
| mbed_official | 532:fe11edbda85c | 263 | |
| mbed_official | 532:fe11edbda85c | 264 | /* Test if the divider is 1 or 0 or greater than 0xFF */ |
| mbed_official | 532:fe11edbda85c | 265 | if((i2sdiv < 2) || (i2sdiv > 0xFF)) |
| mbed_official | 532:fe11edbda85c | 266 | { |
| mbed_official | 532:fe11edbda85c | 267 | /* Set the default values */ |
| mbed_official | 532:fe11edbda85c | 268 | i2sdiv = 2; |
| mbed_official | 532:fe11edbda85c | 269 | i2sodd = 0; |
| mbed_official | 532:fe11edbda85c | 270 | } |
| mbed_official | 532:fe11edbda85c | 271 | |
| mbed_official | 532:fe11edbda85c | 272 | /* Write to SPIx I2SPR register the computed value */ |
| mbed_official | 532:fe11edbda85c | 273 | hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); |
| mbed_official | 532:fe11edbda85c | 274 | |
| mbed_official | 532:fe11edbda85c | 275 | /* Configure the I2S with the I2S_InitStruct values */ |
| mbed_official | 532:fe11edbda85c | 276 | tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL); |
| mbed_official | 532:fe11edbda85c | 277 | |
| mbed_official | 532:fe11edbda85c | 278 | #if defined(SPI_I2SCFGR_ASTRTEN) |
| mbed_official | 532:fe11edbda85c | 279 | if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) |
| mbed_official | 532:fe11edbda85c | 280 | { |
| mbed_official | 532:fe11edbda85c | 281 | /* Write to SPIx I2SCFGR */ |
| mbed_official | 532:fe11edbda85c | 282 | hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN; |
| mbed_official | 532:fe11edbda85c | 283 | } |
| mbed_official | 532:fe11edbda85c | 284 | else |
| mbed_official | 532:fe11edbda85c | 285 | { |
| mbed_official | 532:fe11edbda85c | 286 | /* Write to SPIx I2SCFGR */ |
| mbed_official | 532:fe11edbda85c | 287 | hi2s->Instance->I2SCFGR = tmpreg; |
| mbed_official | 532:fe11edbda85c | 288 | } |
| mbed_official | 532:fe11edbda85c | 289 | #else |
| mbed_official | 532:fe11edbda85c | 290 | /* Write to SPIx I2SCFGR */ |
| mbed_official | 532:fe11edbda85c | 291 | hi2s->Instance->I2SCFGR = tmpreg; |
| mbed_official | 532:fe11edbda85c | 292 | #endif |
| mbed_official | 532:fe11edbda85c | 293 | |
| mbed_official | 532:fe11edbda85c | 294 | /* Configure the I2S extended if the full duplex mode is enabled */ |
| mbed_official | 532:fe11edbda85c | 295 | assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode)); |
| mbed_official | 532:fe11edbda85c | 296 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
| mbed_official | 532:fe11edbda85c | 297 | { |
| mbed_official | 532:fe11edbda85c | 298 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ |
| mbed_official | 532:fe11edbda85c | 299 | I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ |
| mbed_official | 532:fe11edbda85c | 300 | SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ |
| mbed_official | 532:fe11edbda85c | 301 | SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); |
| mbed_official | 532:fe11edbda85c | 302 | I2SxEXT(hi2s->Instance)->I2SPR = 2; |
| mbed_official | 532:fe11edbda85c | 303 | |
| mbed_official | 532:fe11edbda85c | 304 | /* Get the I2SCFGR register value */ |
| mbed_official | 532:fe11edbda85c | 305 | tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR; |
| mbed_official | 532:fe11edbda85c | 306 | |
| mbed_official | 532:fe11edbda85c | 307 | /* Get the mode to be configured for the extended I2S */ |
| mbed_official | 532:fe11edbda85c | 308 | if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) |
| mbed_official | 532:fe11edbda85c | 309 | { |
| mbed_official | 532:fe11edbda85c | 310 | tmp = I2S_MODE_SLAVE_RX; |
| mbed_official | 532:fe11edbda85c | 311 | } |
| mbed_official | 532:fe11edbda85c | 312 | else |
| mbed_official | 532:fe11edbda85c | 313 | { |
| mbed_official | 532:fe11edbda85c | 314 | if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) |
| mbed_official | 532:fe11edbda85c | 315 | { |
| mbed_official | 532:fe11edbda85c | 316 | tmp = I2S_MODE_SLAVE_TX; |
| mbed_official | 532:fe11edbda85c | 317 | } |
| mbed_official | 532:fe11edbda85c | 318 | } |
| mbed_official | 532:fe11edbda85c | 319 | |
| mbed_official | 532:fe11edbda85c | 320 | /* Configure the I2S Slave with the I2S Master parameter values */ |
| mbed_official | 532:fe11edbda85c | 321 | tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL); |
| mbed_official | 532:fe11edbda85c | 322 | |
| mbed_official | 532:fe11edbda85c | 323 | /* Write to SPIx I2SCFGR */ |
| mbed_official | 532:fe11edbda85c | 324 | I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg; |
| mbed_official | 532:fe11edbda85c | 325 | } |
| mbed_official | 532:fe11edbda85c | 326 | |
| mbed_official | 532:fe11edbda85c | 327 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
| mbed_official | 532:fe11edbda85c | 328 | hi2s->State= HAL_I2S_STATE_READY; |
| mbed_official | 532:fe11edbda85c | 329 | |
| mbed_official | 532:fe11edbda85c | 330 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 331 | } |
| mbed_official | 87:085cde657901 | 332 | |
| mbed_official | 87:085cde657901 | 333 | /** |
| mbed_official | 87:085cde657901 | 334 | * @brief Full-Duplex Transmit/Receive data in blocking mode. |
| mbed_official | 226:b062af740e40 | 335 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 226:b062af740e40 | 336 | * the configuration information for I2S module |
| mbed_official | 87:085cde657901 | 337 | * @param pTxData: a 16-bit pointer to the Transmit data buffer. |
| mbed_official | 87:085cde657901 | 338 | * @param pRxData: a 16-bit pointer to the Receive data buffer. |
| mbed_official | 87:085cde657901 | 339 | * @param Size: number of data sample to be sent: |
| mbed_official | 87:085cde657901 | 340 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
| mbed_official | 87:085cde657901 | 341 | * configuration phase, the Size parameter means the number of 16-bit data length |
| mbed_official | 87:085cde657901 | 342 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
| mbed_official | 87:085cde657901 | 343 | * the Size parameter means the number of 16-bit data length. |
| mbed_official | 87:085cde657901 | 344 | * @param Timeout: Timeout duration |
| mbed_official | 87:085cde657901 | 345 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
| mbed_official | 87:085cde657901 | 346 | * between Master and Slave(example: audio streaming). |
| mbed_official | 87:085cde657901 | 347 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 348 | */ |
| mbed_official | 87:085cde657901 | 349 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout) |
| mbed_official | 87:085cde657901 | 350 | { |
| mbed_official | 369:2e96f1b71984 | 351 | uint32_t tickstart = 0; |
| mbed_official | 369:2e96f1b71984 | 352 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 87:085cde657901 | 353 | |
| mbed_official | 613:bc40b8d2aec4 | 354 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 87:085cde657901 | 355 | { |
| mbed_official | 87:085cde657901 | 356 | return HAL_ERROR; |
| mbed_official | 87:085cde657901 | 357 | } |
| mbed_official | 87:085cde657901 | 358 | |
| mbed_official | 87:085cde657901 | 359 | /* Check the I2S State */ |
| mbed_official | 87:085cde657901 | 360 | if(hi2s->State == HAL_I2S_STATE_READY) |
| mbed_official | 87:085cde657901 | 361 | { |
| mbed_official | 87:085cde657901 | 362 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 87:085cde657901 | 363 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 87:085cde657901 | 364 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
| mbed_official | 87:085cde657901 | 365 | is selected during the I2S configuration phase, the Size parameter means the number |
| mbed_official | 87:085cde657901 | 366 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
| mbed_official | 87:085cde657901 | 367 | frame is selected the Size parameter means the number of 16-bit data length. */ |
| mbed_official | 87:085cde657901 | 368 | if((tmp1 == I2S_DATAFORMAT_24B)|| \ |
| mbed_official | 87:085cde657901 | 369 | (tmp2 == I2S_DATAFORMAT_32B)) |
| mbed_official | 87:085cde657901 | 370 | { |
| mbed_official | 87:085cde657901 | 371 | hi2s->TxXferSize = Size*2; |
| mbed_official | 87:085cde657901 | 372 | hi2s->TxXferCount = Size*2; |
| mbed_official | 87:085cde657901 | 373 | hi2s->RxXferSize = Size*2; |
| mbed_official | 87:085cde657901 | 374 | hi2s->RxXferCount = Size*2; |
| mbed_official | 87:085cde657901 | 375 | } |
| mbed_official | 87:085cde657901 | 376 | else |
| mbed_official | 87:085cde657901 | 377 | { |
| mbed_official | 87:085cde657901 | 378 | hi2s->TxXferSize = Size; |
| mbed_official | 87:085cde657901 | 379 | hi2s->TxXferCount = Size; |
| mbed_official | 87:085cde657901 | 380 | hi2s->RxXferSize = Size; |
| mbed_official | 87:085cde657901 | 381 | hi2s->RxXferCount = Size; |
| mbed_official | 87:085cde657901 | 382 | } |
| mbed_official | 87:085cde657901 | 383 | |
| mbed_official | 87:085cde657901 | 384 | /* Process Locked */ |
| mbed_official | 87:085cde657901 | 385 | __HAL_LOCK(hi2s); |
| mbed_official | 87:085cde657901 | 386 | |
| mbed_official | 87:085cde657901 | 387 | /* Set the I2S State busy TX/RX */ |
| mbed_official | 87:085cde657901 | 388 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
| mbed_official | 87:085cde657901 | 389 | |
| mbed_official | 87:085cde657901 | 390 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 391 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 392 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 87:085cde657901 | 393 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 87:085cde657901 | 394 | { |
| mbed_official | 87:085cde657901 | 395 | /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction |
| mbed_official | 87:085cde657901 | 396 | to avoid the clock de-synchronization between Master and Slave. */ |
| mbed_official | 87:085cde657901 | 397 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 87:085cde657901 | 398 | { |
| mbed_official | 87:085cde657901 | 399 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 400 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 87:085cde657901 | 401 | |
| mbed_official | 87:085cde657901 | 402 | /* Enable I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 403 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 87:085cde657901 | 404 | } |
| mbed_official | 87:085cde657901 | 405 | |
| mbed_official | 87:085cde657901 | 406 | while(hi2s->TxXferCount > 0) |
| mbed_official | 87:085cde657901 | 407 | { |
| mbed_official | 87:085cde657901 | 408 | /* Wait until TXE flag is set */ |
| mbed_official | 87:085cde657901 | 409 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) |
| mbed_official | 87:085cde657901 | 410 | { |
| mbed_official | 87:085cde657901 | 411 | return HAL_TIMEOUT; |
| mbed_official | 87:085cde657901 | 412 | } |
| mbed_official | 87:085cde657901 | 413 | hi2s->Instance->DR = (*pTxData++); |
| mbed_official | 87:085cde657901 | 414 | |
| mbed_official | 369:2e96f1b71984 | 415 | /* Get tick */ |
| mbed_official | 369:2e96f1b71984 | 416 | tickstart = HAL_GetTick(); |
| mbed_official | 369:2e96f1b71984 | 417 | |
| mbed_official | 87:085cde657901 | 418 | /* Wait until RXNE flag is set */ |
| mbed_official | 87:085cde657901 | 419 | while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE) |
| mbed_official | 87:085cde657901 | 420 | { |
| mbed_official | 87:085cde657901 | 421 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 87:085cde657901 | 422 | { |
| mbed_official | 369:2e96f1b71984 | 423 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| mbed_official | 87:085cde657901 | 424 | { |
| mbed_official | 87:085cde657901 | 425 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 426 | __HAL_UNLOCK(hi2s); |
| mbed_official | 87:085cde657901 | 427 | |
| mbed_official | 87:085cde657901 | 428 | return HAL_TIMEOUT; |
| mbed_official | 87:085cde657901 | 429 | } |
| mbed_official | 87:085cde657901 | 430 | } |
| mbed_official | 87:085cde657901 | 431 | } |
| mbed_official | 87:085cde657901 | 432 | (*pRxData++) = I2SxEXT(hi2s->Instance)->DR; |
| mbed_official | 87:085cde657901 | 433 | |
| mbed_official | 87:085cde657901 | 434 | hi2s->TxXferCount--; |
| mbed_official | 87:085cde657901 | 435 | hi2s->RxXferCount--; |
| mbed_official | 87:085cde657901 | 436 | } |
| mbed_official | 87:085cde657901 | 437 | } |
| mbed_official | 87:085cde657901 | 438 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
| mbed_official | 87:085cde657901 | 439 | else |
| mbed_official | 87:085cde657901 | 440 | { |
| mbed_official | 87:085cde657901 | 441 | /* Check if the I2S is already enabled */ |
| mbed_official | 87:085cde657901 | 442 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 87:085cde657901 | 443 | { |
| mbed_official | 87:085cde657901 | 444 | /* Enable I2S peripheral before the I2Sext*/ |
| mbed_official | 87:085cde657901 | 445 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 87:085cde657901 | 446 | |
| mbed_official | 87:085cde657901 | 447 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 448 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 87:085cde657901 | 449 | } |
| mbed_official | 87:085cde657901 | 450 | else |
| mbed_official | 87:085cde657901 | 451 | { |
| mbed_official | 87:085cde657901 | 452 | /* Check if Master Receiver mode is selected */ |
| mbed_official | 87:085cde657901 | 453 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
| mbed_official | 87:085cde657901 | 454 | { |
| mbed_official | 87:085cde657901 | 455 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
| mbed_official | 87:085cde657901 | 456 | access to the SPI_SR register. */ |
| mbed_official | 87:085cde657901 | 457 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
| mbed_official | 87:085cde657901 | 458 | } |
| mbed_official | 87:085cde657901 | 459 | } |
| mbed_official | 87:085cde657901 | 460 | while(hi2s->TxXferCount > 0) |
| mbed_official | 87:085cde657901 | 461 | { |
| mbed_official | 369:2e96f1b71984 | 462 | /* Get tick */ |
| mbed_official | 369:2e96f1b71984 | 463 | tickstart = HAL_GetTick(); |
| mbed_official | 369:2e96f1b71984 | 464 | |
| mbed_official | 87:085cde657901 | 465 | /* Wait until TXE flag is set */ |
| mbed_official | 87:085cde657901 | 466 | while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE) |
| mbed_official | 87:085cde657901 | 467 | { |
| mbed_official | 87:085cde657901 | 468 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 87:085cde657901 | 469 | { |
| mbed_official | 369:2e96f1b71984 | 470 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| mbed_official | 87:085cde657901 | 471 | { |
| mbed_official | 87:085cde657901 | 472 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 473 | __HAL_UNLOCK(hi2s); |
| mbed_official | 87:085cde657901 | 474 | |
| mbed_official | 87:085cde657901 | 475 | return HAL_TIMEOUT; |
| mbed_official | 87:085cde657901 | 476 | } |
| mbed_official | 87:085cde657901 | 477 | } |
| mbed_official | 87:085cde657901 | 478 | } |
| mbed_official | 87:085cde657901 | 479 | I2SxEXT(hi2s->Instance)->DR = (*pTxData++); |
| mbed_official | 87:085cde657901 | 480 | |
| mbed_official | 87:085cde657901 | 481 | /* Wait until RXNE flag is set */ |
| mbed_official | 87:085cde657901 | 482 | if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) |
| mbed_official | 87:085cde657901 | 483 | { |
| mbed_official | 87:085cde657901 | 484 | return HAL_TIMEOUT; |
| mbed_official | 87:085cde657901 | 485 | } |
| mbed_official | 87:085cde657901 | 486 | (*pRxData++) = hi2s->Instance->DR; |
| mbed_official | 87:085cde657901 | 487 | |
| mbed_official | 87:085cde657901 | 488 | hi2s->TxXferCount--; |
| mbed_official | 87:085cde657901 | 489 | hi2s->RxXferCount--; |
| mbed_official | 87:085cde657901 | 490 | } |
| mbed_official | 87:085cde657901 | 491 | } |
| mbed_official | 87:085cde657901 | 492 | |
| mbed_official | 87:085cde657901 | 493 | /* Set the I2S State ready */ |
| mbed_official | 87:085cde657901 | 494 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 87:085cde657901 | 495 | |
| mbed_official | 87:085cde657901 | 496 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 497 | __HAL_UNLOCK(hi2s); |
| mbed_official | 87:085cde657901 | 498 | |
| mbed_official | 87:085cde657901 | 499 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 500 | } |
| mbed_official | 87:085cde657901 | 501 | else |
| mbed_official | 87:085cde657901 | 502 | { |
| mbed_official | 87:085cde657901 | 503 | return HAL_BUSY; |
| mbed_official | 87:085cde657901 | 504 | } |
| mbed_official | 87:085cde657901 | 505 | } |
| mbed_official | 87:085cde657901 | 506 | |
| mbed_official | 87:085cde657901 | 507 | /** |
| mbed_official | 87:085cde657901 | 508 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt |
| mbed_official | 226:b062af740e40 | 509 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 226:b062af740e40 | 510 | * the configuration information for I2S module |
| mbed_official | 87:085cde657901 | 511 | * @param pTxData: a 16-bit pointer to the Transmit data buffer. |
| mbed_official | 87:085cde657901 | 512 | * @param pRxData: a 16-bit pointer to the Receive data buffer. |
| mbed_official | 87:085cde657901 | 513 | * @param Size: number of data sample to be sent: |
| mbed_official | 87:085cde657901 | 514 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
| mbed_official | 87:085cde657901 | 515 | * configuration phase, the Size parameter means the number of 16-bit data length |
| mbed_official | 87:085cde657901 | 516 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
| mbed_official | 87:085cde657901 | 517 | * the Size parameter means the number of 16-bit data length. |
| mbed_official | 87:085cde657901 | 518 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
| mbed_official | 87:085cde657901 | 519 | * between Master and Slave(example: audio streaming). |
| mbed_official | 87:085cde657901 | 520 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 521 | */ |
| mbed_official | 87:085cde657901 | 522 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) |
| mbed_official | 87:085cde657901 | 523 | { |
| mbed_official | 87:085cde657901 | 524 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 87:085cde657901 | 525 | |
| mbed_official | 87:085cde657901 | 526 | if(hi2s->State == HAL_I2S_STATE_READY) |
| mbed_official | 87:085cde657901 | 527 | { |
| mbed_official | 613:bc40b8d2aec4 | 528 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 87:085cde657901 | 529 | { |
| mbed_official | 87:085cde657901 | 530 | return HAL_ERROR; |
| mbed_official | 87:085cde657901 | 531 | } |
| mbed_official | 87:085cde657901 | 532 | |
| mbed_official | 87:085cde657901 | 533 | hi2s->pTxBuffPtr = pTxData; |
| mbed_official | 87:085cde657901 | 534 | hi2s->pRxBuffPtr = pRxData; |
| mbed_official | 87:085cde657901 | 535 | |
| mbed_official | 87:085cde657901 | 536 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 87:085cde657901 | 537 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 87:085cde657901 | 538 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
| mbed_official | 87:085cde657901 | 539 | is selected during the I2S configuration phase, the Size parameter means the number |
| mbed_official | 87:085cde657901 | 540 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
| mbed_official | 87:085cde657901 | 541 | frame is selected the Size parameter means the number of 16-bit data length. */ |
| mbed_official | 87:085cde657901 | 542 | if((tmp1 == I2S_DATAFORMAT_24B)||\ |
| mbed_official | 87:085cde657901 | 543 | (tmp2 == I2S_DATAFORMAT_32B)) |
| mbed_official | 87:085cde657901 | 544 | { |
| mbed_official | 87:085cde657901 | 545 | hi2s->TxXferSize = Size*2; |
| mbed_official | 87:085cde657901 | 546 | hi2s->TxXferCount = Size*2; |
| mbed_official | 87:085cde657901 | 547 | hi2s->RxXferSize = Size*2; |
| mbed_official | 87:085cde657901 | 548 | hi2s->RxXferCount = Size*2; |
| mbed_official | 87:085cde657901 | 549 | } |
| mbed_official | 87:085cde657901 | 550 | else |
| mbed_official | 87:085cde657901 | 551 | { |
| mbed_official | 87:085cde657901 | 552 | hi2s->TxXferSize = Size; |
| mbed_official | 87:085cde657901 | 553 | hi2s->TxXferCount = Size; |
| mbed_official | 87:085cde657901 | 554 | hi2s->RxXferSize = Size; |
| mbed_official | 87:085cde657901 | 555 | hi2s->RxXferCount = Size; |
| mbed_official | 87:085cde657901 | 556 | } |
| mbed_official | 87:085cde657901 | 557 | |
| mbed_official | 87:085cde657901 | 558 | /* Process Locked */ |
| mbed_official | 87:085cde657901 | 559 | __HAL_LOCK(hi2s); |
| mbed_official | 87:085cde657901 | 560 | |
| mbed_official | 87:085cde657901 | 561 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
| mbed_official | 87:085cde657901 | 562 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
| mbed_official | 87:085cde657901 | 563 | |
| mbed_official | 87:085cde657901 | 564 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 565 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 566 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 87:085cde657901 | 567 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 87:085cde657901 | 568 | { |
| mbed_official | 87:085cde657901 | 569 | /* Enable I2Sext RXNE and ERR interrupts */ |
| mbed_official | 87:085cde657901 | 570 | I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR); |
| mbed_official | 87:085cde657901 | 571 | |
| mbed_official | 87:085cde657901 | 572 | /* Enable I2Sx TXE and ERR interrupts */ |
| mbed_official | 87:085cde657901 | 573 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); |
| mbed_official | 87:085cde657901 | 574 | |
| mbed_official | 87:085cde657901 | 575 | /* Check if the I2S is already enabled */ |
| mbed_official | 87:085cde657901 | 576 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 87:085cde657901 | 577 | { |
| mbed_official | 87:085cde657901 | 578 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 579 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 87:085cde657901 | 580 | |
| mbed_official | 87:085cde657901 | 581 | /* Enable I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 582 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 87:085cde657901 | 583 | } |
| mbed_official | 87:085cde657901 | 584 | } |
| mbed_official | 87:085cde657901 | 585 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
| mbed_official | 87:085cde657901 | 586 | else |
| mbed_official | 87:085cde657901 | 587 | { |
| mbed_official | 87:085cde657901 | 588 | /* Enable I2Sext TXE and ERR interrupts */ |
| mbed_official | 87:085cde657901 | 589 | I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR); |
| mbed_official | 87:085cde657901 | 590 | |
| mbed_official | 87:085cde657901 | 591 | /* Enable I2Sext RXNE and ERR interrupts */ |
| mbed_official | 87:085cde657901 | 592 | __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); |
| mbed_official | 87:085cde657901 | 593 | |
| mbed_official | 87:085cde657901 | 594 | /* Check if the I2S is already enabled */ |
| mbed_official | 87:085cde657901 | 595 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 87:085cde657901 | 596 | { |
| mbed_official | 87:085cde657901 | 597 | /* Check if the I2S_MODE_MASTER_RX is selected */ |
| mbed_official | 87:085cde657901 | 598 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
| mbed_official | 87:085cde657901 | 599 | { |
| mbed_official | 87:085cde657901 | 600 | /* Prepare the First Data before enabling the I2S */ |
| mbed_official | 87:085cde657901 | 601 | if(hi2s->TxXferCount != 0) |
| mbed_official | 87:085cde657901 | 602 | { |
| mbed_official | 87:085cde657901 | 603 | /* Transmit First data */ |
| mbed_official | 87:085cde657901 | 604 | I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); |
| mbed_official | 87:085cde657901 | 605 | hi2s->TxXferCount--; |
| mbed_official | 87:085cde657901 | 606 | |
| mbed_official | 87:085cde657901 | 607 | if(hi2s->TxXferCount == 0) |
| mbed_official | 87:085cde657901 | 608 | { |
| mbed_official | 87:085cde657901 | 609 | /* Disable I2Sext TXE interrupt */ |
| mbed_official | 87:085cde657901 | 610 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE; |
| mbed_official | 87:085cde657901 | 611 | } |
| mbed_official | 87:085cde657901 | 612 | } |
| mbed_official | 87:085cde657901 | 613 | } |
| mbed_official | 87:085cde657901 | 614 | /* Enable I2S peripheral */ |
| mbed_official | 87:085cde657901 | 615 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 87:085cde657901 | 616 | |
| mbed_official | 87:085cde657901 | 617 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 618 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 87:085cde657901 | 619 | } |
| mbed_official | 87:085cde657901 | 620 | } |
| mbed_official | 87:085cde657901 | 621 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 622 | __HAL_UNLOCK(hi2s); |
| mbed_official | 87:085cde657901 | 623 | |
| mbed_official | 87:085cde657901 | 624 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 625 | } |
| mbed_official | 87:085cde657901 | 626 | else |
| mbed_official | 87:085cde657901 | 627 | { |
| mbed_official | 87:085cde657901 | 628 | return HAL_BUSY; |
| mbed_official | 87:085cde657901 | 629 | } |
| mbed_official | 87:085cde657901 | 630 | } |
| mbed_official | 87:085cde657901 | 631 | |
| mbed_official | 87:085cde657901 | 632 | /** |
| mbed_official | 87:085cde657901 | 633 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA |
| mbed_official | 226:b062af740e40 | 634 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 226:b062af740e40 | 635 | * the configuration information for I2S module |
| mbed_official | 87:085cde657901 | 636 | * @param pTxData: a 16-bit pointer to the Transmit data buffer. |
| mbed_official | 87:085cde657901 | 637 | * @param pRxData: a 16-bit pointer to the Receive data buffer. |
| mbed_official | 87:085cde657901 | 638 | * @param Size: number of data sample to be sent: |
| mbed_official | 87:085cde657901 | 639 | * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S |
| mbed_official | 87:085cde657901 | 640 | * configuration phase, the Size parameter means the number of 16-bit data length |
| mbed_official | 87:085cde657901 | 641 | * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected |
| mbed_official | 87:085cde657901 | 642 | * the Size parameter means the number of 16-bit data length. |
| mbed_official | 87:085cde657901 | 643 | * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization |
| mbed_official | 87:085cde657901 | 644 | * between Master and Slave(example: audio streaming). |
| mbed_official | 87:085cde657901 | 645 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 646 | */ |
| mbed_official | 87:085cde657901 | 647 | HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) |
| mbed_official | 87:085cde657901 | 648 | { |
| mbed_official | 87:085cde657901 | 649 | uint32_t *tmp; |
| mbed_official | 87:085cde657901 | 650 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 87:085cde657901 | 651 | |
| mbed_official | 613:bc40b8d2aec4 | 652 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 87:085cde657901 | 653 | { |
| mbed_official | 87:085cde657901 | 654 | return HAL_ERROR; |
| mbed_official | 87:085cde657901 | 655 | } |
| mbed_official | 87:085cde657901 | 656 | |
| mbed_official | 87:085cde657901 | 657 | if(hi2s->State == HAL_I2S_STATE_READY) |
| mbed_official | 87:085cde657901 | 658 | { |
| mbed_official | 87:085cde657901 | 659 | hi2s->pTxBuffPtr = pTxData; |
| mbed_official | 87:085cde657901 | 660 | hi2s->pRxBuffPtr = pRxData; |
| mbed_official | 87:085cde657901 | 661 | |
| mbed_official | 87:085cde657901 | 662 | tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 87:085cde657901 | 663 | tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); |
| mbed_official | 87:085cde657901 | 664 | /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended |
| mbed_official | 87:085cde657901 | 665 | is selected during the I2S configuration phase, the Size parameter means the number |
| mbed_official | 87:085cde657901 | 666 | of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data |
| mbed_official | 87:085cde657901 | 667 | frame is selected the Size parameter means the number of 16-bit data length. */ |
| mbed_official | 87:085cde657901 | 668 | if((tmp1 == I2S_DATAFORMAT_24B)||\ |
| mbed_official | 87:085cde657901 | 669 | (tmp2 == I2S_DATAFORMAT_32B)) |
| mbed_official | 87:085cde657901 | 670 | { |
| mbed_official | 87:085cde657901 | 671 | hi2s->TxXferSize = Size*2; |
| mbed_official | 87:085cde657901 | 672 | hi2s->TxXferCount = Size*2; |
| mbed_official | 87:085cde657901 | 673 | hi2s->RxXferSize = Size*2; |
| mbed_official | 87:085cde657901 | 674 | hi2s->RxXferCount = Size*2; |
| mbed_official | 87:085cde657901 | 675 | } |
| mbed_official | 87:085cde657901 | 676 | else |
| mbed_official | 87:085cde657901 | 677 | { |
| mbed_official | 87:085cde657901 | 678 | hi2s->TxXferSize = Size; |
| mbed_official | 87:085cde657901 | 679 | hi2s->TxXferCount = Size; |
| mbed_official | 87:085cde657901 | 680 | hi2s->RxXferSize = Size; |
| mbed_official | 87:085cde657901 | 681 | hi2s->RxXferCount = Size; |
| mbed_official | 87:085cde657901 | 682 | } |
| mbed_official | 87:085cde657901 | 683 | |
| mbed_official | 87:085cde657901 | 684 | /* Process Locked */ |
| mbed_official | 87:085cde657901 | 685 | __HAL_LOCK(hi2s); |
| mbed_official | 87:085cde657901 | 686 | |
| mbed_official | 87:085cde657901 | 687 | hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; |
| mbed_official | 87:085cde657901 | 688 | hi2s->ErrorCode = HAL_I2S_ERROR_NONE; |
| mbed_official | 87:085cde657901 | 689 | |
| mbed_official | 532:fe11edbda85c | 690 | /* Set the I2S Rx DMA Half transfer complete callback */ |
| mbed_official | 87:085cde657901 | 691 | hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; |
| mbed_official | 87:085cde657901 | 692 | |
| mbed_official | 532:fe11edbda85c | 693 | /* Set the I2S Rx DMA transfer complete callback */ |
| mbed_official | 87:085cde657901 | 694 | hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; |
| mbed_official | 87:085cde657901 | 695 | |
| mbed_official | 87:085cde657901 | 696 | /* Set the I2S Rx DMA error callback */ |
| mbed_official | 87:085cde657901 | 697 | hi2s->hdmarx->XferErrorCallback = I2S_DMAError; |
| mbed_official | 87:085cde657901 | 698 | |
| mbed_official | 532:fe11edbda85c | 699 | /* Set the I2S Tx DMA Half transfer complete callback */ |
| mbed_official | 87:085cde657901 | 700 | hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; |
| mbed_official | 87:085cde657901 | 701 | |
| mbed_official | 532:fe11edbda85c | 702 | /* Set the I2S Tx DMA transfer complete callback */ |
| mbed_official | 87:085cde657901 | 703 | hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; |
| mbed_official | 87:085cde657901 | 704 | |
| mbed_official | 87:085cde657901 | 705 | /* Set the I2S Tx DMA error callback */ |
| mbed_official | 87:085cde657901 | 706 | hi2s->hdmatx->XferErrorCallback = I2S_DMAError; |
| mbed_official | 87:085cde657901 | 707 | |
| mbed_official | 87:085cde657901 | 708 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 709 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 710 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 87:085cde657901 | 711 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 87:085cde657901 | 712 | { |
| mbed_official | 87:085cde657901 | 713 | /* Enable the Rx DMA Stream */ |
| mbed_official | 87:085cde657901 | 714 | tmp = (uint32_t*)&pRxData; |
| mbed_official | 87:085cde657901 | 715 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize); |
| mbed_official | 87:085cde657901 | 716 | |
| mbed_official | 87:085cde657901 | 717 | /* Enable Rx DMA Request */ |
| mbed_official | 87:085cde657901 | 718 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN; |
| mbed_official | 87:085cde657901 | 719 | |
| mbed_official | 87:085cde657901 | 720 | /* Enable the Tx DMA Stream */ |
| mbed_official | 87:085cde657901 | 721 | tmp = (uint32_t*)&pTxData; |
| mbed_official | 87:085cde657901 | 722 | HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); |
| mbed_official | 87:085cde657901 | 723 | |
| mbed_official | 87:085cde657901 | 724 | /* Enable Tx DMA Request */ |
| mbed_official | 87:085cde657901 | 725 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
| mbed_official | 87:085cde657901 | 726 | |
| mbed_official | 87:085cde657901 | 727 | /* Check if the I2S is already enabled */ |
| mbed_official | 87:085cde657901 | 728 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 87:085cde657901 | 729 | { |
| mbed_official | 87:085cde657901 | 730 | /* Enable I2Sext(receiver) before enabling I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 731 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 87:085cde657901 | 732 | |
| mbed_official | 87:085cde657901 | 733 | /* Enable I2S peripheral after the I2Sext */ |
| mbed_official | 87:085cde657901 | 734 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 87:085cde657901 | 735 | } |
| mbed_official | 87:085cde657901 | 736 | } |
| mbed_official | 87:085cde657901 | 737 | else |
| mbed_official | 87:085cde657901 | 738 | { |
| mbed_official | 87:085cde657901 | 739 | /* Enable the Tx DMA Stream */ |
| mbed_official | 87:085cde657901 | 740 | tmp = (uint32_t*)&pTxData; |
| mbed_official | 87:085cde657901 | 741 | HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize); |
| mbed_official | 87:085cde657901 | 742 | |
| mbed_official | 87:085cde657901 | 743 | /* Enable Tx DMA Request */ |
| mbed_official | 87:085cde657901 | 744 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN; |
| mbed_official | 87:085cde657901 | 745 | |
| mbed_official | 87:085cde657901 | 746 | /* Enable the Rx DMA Stream */ |
| mbed_official | 87:085cde657901 | 747 | tmp = (uint32_t*)&pRxData; |
| mbed_official | 87:085cde657901 | 748 | HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); |
| mbed_official | 87:085cde657901 | 749 | |
| mbed_official | 87:085cde657901 | 750 | /* Enable Rx DMA Request */ |
| mbed_official | 87:085cde657901 | 751 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
| mbed_official | 87:085cde657901 | 752 | |
| mbed_official | 87:085cde657901 | 753 | /* Check if the I2S is already enabled */ |
| mbed_official | 87:085cde657901 | 754 | if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) |
| mbed_official | 87:085cde657901 | 755 | { |
| mbed_official | 87:085cde657901 | 756 | /* Enable I2S peripheral before the I2Sext */ |
| mbed_official | 87:085cde657901 | 757 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 87:085cde657901 | 758 | |
| mbed_official | 87:085cde657901 | 759 | /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */ |
| mbed_official | 87:085cde657901 | 760 | I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE; |
| mbed_official | 87:085cde657901 | 761 | } |
| mbed_official | 87:085cde657901 | 762 | else |
| mbed_official | 87:085cde657901 | 763 | { |
| mbed_official | 87:085cde657901 | 764 | /* Check if Master Receiver mode is selected */ |
| mbed_official | 87:085cde657901 | 765 | if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) |
| mbed_official | 87:085cde657901 | 766 | { |
| mbed_official | 87:085cde657901 | 767 | /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read |
| mbed_official | 87:085cde657901 | 768 | access to the SPI_SR register. */ |
| mbed_official | 87:085cde657901 | 769 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
| mbed_official | 87:085cde657901 | 770 | } |
| mbed_official | 87:085cde657901 | 771 | } |
| mbed_official | 87:085cde657901 | 772 | } |
| mbed_official | 87:085cde657901 | 773 | |
| mbed_official | 87:085cde657901 | 774 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 775 | __HAL_UNLOCK(hi2s); |
| mbed_official | 87:085cde657901 | 776 | |
| mbed_official | 87:085cde657901 | 777 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 778 | } |
| mbed_official | 87:085cde657901 | 779 | else |
| mbed_official | 87:085cde657901 | 780 | { |
| mbed_official | 87:085cde657901 | 781 | return HAL_BUSY; |
| mbed_official | 87:085cde657901 | 782 | } |
| mbed_official | 87:085cde657901 | 783 | } |
| mbed_official | 87:085cde657901 | 784 | |
| mbed_official | 87:085cde657901 | 785 | /** |
| mbed_official | 532:fe11edbda85c | 786 | * @brief Pauses the audio stream playing from the Media. |
| mbed_official | 532:fe11edbda85c | 787 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 788 | * the configuration information for I2S module |
| mbed_official | 532:fe11edbda85c | 789 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 790 | */ |
| mbed_official | 532:fe11edbda85c | 791 | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) |
| mbed_official | 532:fe11edbda85c | 792 | { |
| mbed_official | 532:fe11edbda85c | 793 | /* Process Locked */ |
| mbed_official | 532:fe11edbda85c | 794 | __HAL_LOCK(hi2s); |
| mbed_official | 532:fe11edbda85c | 795 | |
| mbed_official | 532:fe11edbda85c | 796 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
| mbed_official | 532:fe11edbda85c | 797 | { |
| mbed_official | 532:fe11edbda85c | 798 | /* Disable the I2S DMA Tx request */ |
| mbed_official | 532:fe11edbda85c | 799 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
| mbed_official | 532:fe11edbda85c | 800 | } |
| mbed_official | 532:fe11edbda85c | 801 | else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
| mbed_official | 532:fe11edbda85c | 802 | { |
| mbed_official | 532:fe11edbda85c | 803 | /* Disable the I2S DMA Rx request */ |
| mbed_official | 532:fe11edbda85c | 804 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
| mbed_official | 532:fe11edbda85c | 805 | } |
| mbed_official | 532:fe11edbda85c | 806 | else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
| mbed_official | 532:fe11edbda85c | 807 | { |
| mbed_official | 532:fe11edbda85c | 808 | if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX)) |
| mbed_official | 532:fe11edbda85c | 809 | { |
| mbed_official | 532:fe11edbda85c | 810 | /* Disable the I2S DMA Tx request */ |
| mbed_official | 532:fe11edbda85c | 811 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
| mbed_official | 532:fe11edbda85c | 812 | /* Disable the I2SEx Rx DMA Request */ |
| mbed_official | 532:fe11edbda85c | 813 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
| mbed_official | 532:fe11edbda85c | 814 | } |
| mbed_official | 532:fe11edbda85c | 815 | else |
| mbed_official | 532:fe11edbda85c | 816 | { |
| mbed_official | 532:fe11edbda85c | 817 | /* Disable the I2S DMA Rx request */ |
| mbed_official | 532:fe11edbda85c | 818 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
| mbed_official | 532:fe11edbda85c | 819 | /* Disable the I2SEx Tx DMA Request */ |
| mbed_official | 532:fe11edbda85c | 820 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
| mbed_official | 532:fe11edbda85c | 821 | } |
| mbed_official | 532:fe11edbda85c | 822 | } |
| mbed_official | 532:fe11edbda85c | 823 | |
| mbed_official | 532:fe11edbda85c | 824 | /* Process Unlocked */ |
| mbed_official | 532:fe11edbda85c | 825 | __HAL_UNLOCK(hi2s); |
| mbed_official | 532:fe11edbda85c | 826 | |
| mbed_official | 532:fe11edbda85c | 827 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 828 | } |
| mbed_official | 532:fe11edbda85c | 829 | |
| mbed_official | 532:fe11edbda85c | 830 | /** |
| mbed_official | 532:fe11edbda85c | 831 | * @brief Resumes the audio stream playing from the Media. |
| mbed_official | 532:fe11edbda85c | 832 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 833 | * the configuration information for I2S module |
| mbed_official | 532:fe11edbda85c | 834 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 835 | */ |
| mbed_official | 532:fe11edbda85c | 836 | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) |
| mbed_official | 532:fe11edbda85c | 837 | { |
| mbed_official | 532:fe11edbda85c | 838 | /* Process Locked */ |
| mbed_official | 532:fe11edbda85c | 839 | __HAL_LOCK(hi2s); |
| mbed_official | 532:fe11edbda85c | 840 | |
| mbed_official | 532:fe11edbda85c | 841 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
| mbed_official | 532:fe11edbda85c | 842 | { |
| mbed_official | 532:fe11edbda85c | 843 | /* Enable the I2S DMA Tx request */ |
| mbed_official | 532:fe11edbda85c | 844 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
| mbed_official | 532:fe11edbda85c | 845 | } |
| mbed_official | 532:fe11edbda85c | 846 | else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
| mbed_official | 532:fe11edbda85c | 847 | { |
| mbed_official | 532:fe11edbda85c | 848 | /* Enable the I2S DMA Rx request */ |
| mbed_official | 532:fe11edbda85c | 849 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
| mbed_official | 532:fe11edbda85c | 850 | } |
| mbed_official | 532:fe11edbda85c | 851 | else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
| mbed_official | 532:fe11edbda85c | 852 | { |
| mbed_official | 532:fe11edbda85c | 853 | if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX)) |
| mbed_official | 532:fe11edbda85c | 854 | { |
| mbed_official | 532:fe11edbda85c | 855 | /* Enable the I2S DMA Tx request */ |
| mbed_official | 532:fe11edbda85c | 856 | hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; |
| mbed_official | 532:fe11edbda85c | 857 | /* Disable the I2SEx Rx DMA Request */ |
| mbed_official | 532:fe11edbda85c | 858 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN; |
| mbed_official | 532:fe11edbda85c | 859 | } |
| mbed_official | 532:fe11edbda85c | 860 | else |
| mbed_official | 532:fe11edbda85c | 861 | { |
| mbed_official | 532:fe11edbda85c | 862 | /* Enable the I2S DMA Rx request */ |
| mbed_official | 532:fe11edbda85c | 863 | hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; |
| mbed_official | 532:fe11edbda85c | 864 | /* Enable the I2SEx Tx DMA Request */ |
| mbed_official | 532:fe11edbda85c | 865 | I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN; |
| mbed_official | 532:fe11edbda85c | 866 | } |
| mbed_official | 532:fe11edbda85c | 867 | } |
| mbed_official | 532:fe11edbda85c | 868 | |
| mbed_official | 532:fe11edbda85c | 869 | /* If the I2S peripheral is still not enabled, enable it */ |
| mbed_official | 532:fe11edbda85c | 870 | if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) |
| mbed_official | 532:fe11edbda85c | 871 | { |
| mbed_official | 532:fe11edbda85c | 872 | /* Enable I2S peripheral */ |
| mbed_official | 532:fe11edbda85c | 873 | __HAL_I2S_ENABLE(hi2s); |
| mbed_official | 532:fe11edbda85c | 874 | } |
| mbed_official | 532:fe11edbda85c | 875 | |
| mbed_official | 532:fe11edbda85c | 876 | /* Process Unlocked */ |
| mbed_official | 532:fe11edbda85c | 877 | __HAL_UNLOCK(hi2s); |
| mbed_official | 532:fe11edbda85c | 878 | |
| mbed_official | 532:fe11edbda85c | 879 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 880 | } |
| mbed_official | 532:fe11edbda85c | 881 | |
| mbed_official | 532:fe11edbda85c | 882 | /** |
| mbed_official | 532:fe11edbda85c | 883 | * @brief Resumes the audio stream playing from the Media. |
| mbed_official | 532:fe11edbda85c | 884 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 885 | * the configuration information for I2S module |
| mbed_official | 532:fe11edbda85c | 886 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 887 | */ |
| mbed_official | 532:fe11edbda85c | 888 | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) |
| mbed_official | 532:fe11edbda85c | 889 | { |
| mbed_official | 532:fe11edbda85c | 890 | /* Process Locked */ |
| mbed_official | 532:fe11edbda85c | 891 | __HAL_LOCK(hi2s); |
| mbed_official | 532:fe11edbda85c | 892 | |
| mbed_official | 532:fe11edbda85c | 893 | /* Disable the I2S Tx/Rx DMA requests */ |
| mbed_official | 532:fe11edbda85c | 894 | hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN; |
| mbed_official | 532:fe11edbda85c | 895 | hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN; |
| mbed_official | 532:fe11edbda85c | 896 | |
| mbed_official | 532:fe11edbda85c | 897 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
| mbed_official | 532:fe11edbda85c | 898 | { |
| mbed_official | 532:fe11edbda85c | 899 | /* Disable the I2S extended Tx/Rx DMA requests */ |
| mbed_official | 532:fe11edbda85c | 900 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
| mbed_official | 532:fe11edbda85c | 901 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
| mbed_official | 532:fe11edbda85c | 902 | } |
| mbed_official | 532:fe11edbda85c | 903 | |
| mbed_official | 532:fe11edbda85c | 904 | /* Abort the I2S DMA Stream tx */ |
| mbed_official | 613:bc40b8d2aec4 | 905 | if(hi2s->hdmatx != NULL) |
| mbed_official | 532:fe11edbda85c | 906 | { |
| mbed_official | 532:fe11edbda85c | 907 | HAL_DMA_Abort(hi2s->hdmatx); |
| mbed_official | 532:fe11edbda85c | 908 | } |
| mbed_official | 532:fe11edbda85c | 909 | /* Abort the I2S DMA Stream rx */ |
| mbed_official | 613:bc40b8d2aec4 | 910 | if(hi2s->hdmarx != NULL) |
| mbed_official | 532:fe11edbda85c | 911 | { |
| mbed_official | 532:fe11edbda85c | 912 | HAL_DMA_Abort(hi2s->hdmarx); |
| mbed_official | 532:fe11edbda85c | 913 | } |
| mbed_official | 532:fe11edbda85c | 914 | |
| mbed_official | 532:fe11edbda85c | 915 | /* Disable I2S peripheral */ |
| mbed_official | 532:fe11edbda85c | 916 | __HAL_I2S_DISABLE(hi2s); |
| mbed_official | 532:fe11edbda85c | 917 | |
| mbed_official | 532:fe11edbda85c | 918 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
| mbed_official | 532:fe11edbda85c | 919 | { |
| mbed_official | 532:fe11edbda85c | 920 | /* Disable the I2Sext peripheral */ |
| mbed_official | 532:fe11edbda85c | 921 | I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE; |
| mbed_official | 532:fe11edbda85c | 922 | } |
| mbed_official | 532:fe11edbda85c | 923 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 532:fe11edbda85c | 924 | |
| mbed_official | 532:fe11edbda85c | 925 | /* Process Unlocked */ |
| mbed_official | 532:fe11edbda85c | 926 | __HAL_UNLOCK(hi2s); |
| mbed_official | 532:fe11edbda85c | 927 | |
| mbed_official | 532:fe11edbda85c | 928 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 929 | } |
| mbed_official | 532:fe11edbda85c | 930 | |
| mbed_official | 532:fe11edbda85c | 931 | /** |
| mbed_official | 532:fe11edbda85c | 932 | * @brief This function handles I2S interrupt request. |
| mbed_official | 532:fe11edbda85c | 933 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 934 | * the configuration information for I2S module |
| mbed_official | 532:fe11edbda85c | 935 | * @retval None |
| mbed_official | 532:fe11edbda85c | 936 | */ |
| mbed_official | 532:fe11edbda85c | 937 | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) |
| mbed_official | 532:fe11edbda85c | 938 | { |
| mbed_official | 532:fe11edbda85c | 939 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 532:fe11edbda85c | 940 | __IO uint32_t tmpreg1 = 0; |
| mbed_official | 532:fe11edbda85c | 941 | if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE) |
| mbed_official | 532:fe11edbda85c | 942 | { |
| mbed_official | 532:fe11edbda85c | 943 | if(hi2s->State == HAL_I2S_STATE_BUSY_RX) |
| mbed_official | 532:fe11edbda85c | 944 | { |
| mbed_official | 532:fe11edbda85c | 945 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE); |
| mbed_official | 532:fe11edbda85c | 946 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE); |
| mbed_official | 532:fe11edbda85c | 947 | /* I2S in mode Receiver ------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 948 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 949 | { |
| mbed_official | 532:fe11edbda85c | 950 | I2S_Receive_IT(hi2s); |
| mbed_official | 532:fe11edbda85c | 951 | } |
| mbed_official | 532:fe11edbda85c | 952 | |
| mbed_official | 532:fe11edbda85c | 953 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); |
| mbed_official | 532:fe11edbda85c | 954 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
| mbed_official | 532:fe11edbda85c | 955 | /* I2S Overrun error interrupt occurred ---------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 956 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 957 | { |
| mbed_official | 532:fe11edbda85c | 958 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
| mbed_official | 532:fe11edbda85c | 959 | hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; |
| mbed_official | 532:fe11edbda85c | 960 | } |
| mbed_official | 532:fe11edbda85c | 961 | } |
| mbed_official | 532:fe11edbda85c | 962 | |
| mbed_official | 532:fe11edbda85c | 963 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX) |
| mbed_official | 532:fe11edbda85c | 964 | { |
| mbed_official | 532:fe11edbda85c | 965 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE); |
| mbed_official | 532:fe11edbda85c | 966 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE); |
| mbed_official | 532:fe11edbda85c | 967 | /* I2S in mode Tramitter -----------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 968 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 969 | { |
| mbed_official | 532:fe11edbda85c | 970 | I2S_Transmit_IT(hi2s); |
| mbed_official | 532:fe11edbda85c | 971 | } |
| mbed_official | 532:fe11edbda85c | 972 | |
| mbed_official | 532:fe11edbda85c | 973 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); |
| mbed_official | 532:fe11edbda85c | 974 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
| mbed_official | 532:fe11edbda85c | 975 | /* I2S Underrun error interrupt occurred --------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 976 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 977 | { |
| mbed_official | 532:fe11edbda85c | 978 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
| mbed_official | 532:fe11edbda85c | 979 | hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; |
| mbed_official | 532:fe11edbda85c | 980 | } |
| mbed_official | 532:fe11edbda85c | 981 | } |
| mbed_official | 532:fe11edbda85c | 982 | } |
| mbed_official | 532:fe11edbda85c | 983 | else |
| mbed_official | 532:fe11edbda85c | 984 | { |
| mbed_official | 532:fe11edbda85c | 985 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 986 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 987 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 532:fe11edbda85c | 988 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 532:fe11edbda85c | 989 | { |
| mbed_official | 532:fe11edbda85c | 990 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE; |
| mbed_official | 532:fe11edbda85c | 991 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE; |
| mbed_official | 532:fe11edbda85c | 992 | /* I2Sext in mode Receiver ---------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 993 | if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE)) |
| mbed_official | 532:fe11edbda85c | 994 | { |
| mbed_official | 532:fe11edbda85c | 995 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 996 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 997 | /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, |
| mbed_official | 532:fe11edbda85c | 998 | the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */ |
| mbed_official | 532:fe11edbda85c | 999 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 532:fe11edbda85c | 1000 | { |
| mbed_official | 532:fe11edbda85c | 1001 | I2SEx_TransmitReceive_IT(hi2s); |
| mbed_official | 532:fe11edbda85c | 1002 | } |
| mbed_official | 532:fe11edbda85c | 1003 | } |
| mbed_official | 532:fe11edbda85c | 1004 | |
| mbed_official | 532:fe11edbda85c | 1005 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR; |
| mbed_official | 532:fe11edbda85c | 1006 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; |
| mbed_official | 532:fe11edbda85c | 1007 | /* I2Sext Overrun error interrupt occurred ------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 1008 | if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR)) |
| mbed_official | 532:fe11edbda85c | 1009 | { |
| mbed_official | 532:fe11edbda85c | 1010 | /* Clear I2Sext OVR Flag */ |
| mbed_official | 532:fe11edbda85c | 1011 | tmpreg1 = I2SxEXT(hi2s->Instance)->DR; |
| mbed_official | 532:fe11edbda85c | 1012 | tmpreg1 = I2SxEXT(hi2s->Instance)->SR; |
| mbed_official | 532:fe11edbda85c | 1013 | hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR; |
| mbed_official | 532:fe11edbda85c | 1014 | UNUSED(tmpreg1); |
| mbed_official | 532:fe11edbda85c | 1015 | } |
| mbed_official | 532:fe11edbda85c | 1016 | |
| mbed_official | 532:fe11edbda85c | 1017 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE); |
| mbed_official | 532:fe11edbda85c | 1018 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE); |
| mbed_official | 532:fe11edbda85c | 1019 | /* I2S in mode Tramitter -----------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 1020 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 1021 | { |
| mbed_official | 532:fe11edbda85c | 1022 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 1023 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 1024 | /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX, |
| mbed_official | 532:fe11edbda85c | 1025 | the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */ |
| mbed_official | 532:fe11edbda85c | 1026 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 532:fe11edbda85c | 1027 | { |
| mbed_official | 532:fe11edbda85c | 1028 | I2SEx_TransmitReceive_IT(hi2s); |
| mbed_official | 532:fe11edbda85c | 1029 | } |
| mbed_official | 532:fe11edbda85c | 1030 | } |
| mbed_official | 532:fe11edbda85c | 1031 | |
| mbed_official | 532:fe11edbda85c | 1032 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); |
| mbed_official | 532:fe11edbda85c | 1033 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
| mbed_official | 532:fe11edbda85c | 1034 | /* I2S Underrun error interrupt occurred --------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 1035 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 1036 | { |
| mbed_official | 532:fe11edbda85c | 1037 | __HAL_I2S_CLEAR_UDRFLAG(hi2s); |
| mbed_official | 532:fe11edbda85c | 1038 | hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; |
| mbed_official | 532:fe11edbda85c | 1039 | } |
| mbed_official | 532:fe11edbda85c | 1040 | } |
| mbed_official | 532:fe11edbda85c | 1041 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
| mbed_official | 532:fe11edbda85c | 1042 | else |
| mbed_official | 532:fe11edbda85c | 1043 | { |
| mbed_official | 532:fe11edbda85c | 1044 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE); |
| mbed_official | 532:fe11edbda85c | 1045 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE); |
| mbed_official | 532:fe11edbda85c | 1046 | /* I2S in mode Receiver ------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 1047 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 1048 | { |
| mbed_official | 532:fe11edbda85c | 1049 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 1050 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 1051 | /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, |
| mbed_official | 532:fe11edbda85c | 1052 | the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */ |
| mbed_official | 532:fe11edbda85c | 1053 | if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX)) |
| mbed_official | 532:fe11edbda85c | 1054 | { |
| mbed_official | 532:fe11edbda85c | 1055 | I2SEx_TransmitReceive_IT(hi2s); |
| mbed_official | 532:fe11edbda85c | 1056 | } |
| mbed_official | 532:fe11edbda85c | 1057 | } |
| mbed_official | 532:fe11edbda85c | 1058 | |
| mbed_official | 532:fe11edbda85c | 1059 | tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); |
| mbed_official | 532:fe11edbda85c | 1060 | tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); |
| mbed_official | 532:fe11edbda85c | 1061 | /* I2S Overrun error interrupt occurred ---------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 1062 | if((tmp1 != RESET) && (tmp2 != RESET)) |
| mbed_official | 532:fe11edbda85c | 1063 | { |
| mbed_official | 532:fe11edbda85c | 1064 | __HAL_I2S_CLEAR_OVRFLAG(hi2s); |
| mbed_official | 532:fe11edbda85c | 1065 | hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; |
| mbed_official | 532:fe11edbda85c | 1066 | } |
| mbed_official | 532:fe11edbda85c | 1067 | |
| mbed_official | 532:fe11edbda85c | 1068 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE; |
| mbed_official | 532:fe11edbda85c | 1069 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE; |
| mbed_official | 532:fe11edbda85c | 1070 | /* I2Sext in mode Tramitter --------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 1071 | if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE)) |
| mbed_official | 532:fe11edbda85c | 1072 | { |
| mbed_official | 532:fe11edbda85c | 1073 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 1074 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 532:fe11edbda85c | 1075 | /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX, |
| mbed_official | 532:fe11edbda85c | 1076 | the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */ |
| mbed_official | 532:fe11edbda85c | 1077 | if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX)) |
| mbed_official | 532:fe11edbda85c | 1078 | { |
| mbed_official | 532:fe11edbda85c | 1079 | I2SEx_TransmitReceive_IT(hi2s); |
| mbed_official | 532:fe11edbda85c | 1080 | } |
| mbed_official | 532:fe11edbda85c | 1081 | } |
| mbed_official | 532:fe11edbda85c | 1082 | |
| mbed_official | 532:fe11edbda85c | 1083 | tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR; |
| mbed_official | 532:fe11edbda85c | 1084 | tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR; |
| mbed_official | 532:fe11edbda85c | 1085 | /* I2Sext Underrun error interrupt occurred -----------------------------*/ |
| mbed_official | 532:fe11edbda85c | 1086 | if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR)) |
| mbed_official | 532:fe11edbda85c | 1087 | { |
| mbed_official | 532:fe11edbda85c | 1088 | /* Clear I2Sext UDR Flag */ |
| mbed_official | 532:fe11edbda85c | 1089 | tmpreg1 = I2SxEXT(hi2s->Instance)->SR; |
| mbed_official | 532:fe11edbda85c | 1090 | hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR; |
| mbed_official | 532:fe11edbda85c | 1091 | UNUSED(tmpreg1); |
| mbed_official | 532:fe11edbda85c | 1092 | } |
| mbed_official | 532:fe11edbda85c | 1093 | } |
| mbed_official | 532:fe11edbda85c | 1094 | } |
| mbed_official | 532:fe11edbda85c | 1095 | |
| mbed_official | 532:fe11edbda85c | 1096 | /* Call the Error call Back in case of Errors */ |
| mbed_official | 532:fe11edbda85c | 1097 | if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE) |
| mbed_official | 532:fe11edbda85c | 1098 | { |
| mbed_official | 532:fe11edbda85c | 1099 | /* Set the I2S state ready to be able to start again the process */ |
| mbed_official | 532:fe11edbda85c | 1100 | hi2s->State= HAL_I2S_STATE_READY; |
| mbed_official | 532:fe11edbda85c | 1101 | HAL_I2S_ErrorCallback(hi2s); |
| mbed_official | 532:fe11edbda85c | 1102 | } |
| mbed_official | 532:fe11edbda85c | 1103 | } |
| mbed_official | 532:fe11edbda85c | 1104 | |
| mbed_official | 532:fe11edbda85c | 1105 | /** |
| mbed_official | 87:085cde657901 | 1106 | * @} |
| mbed_official | 87:085cde657901 | 1107 | */ |
| mbed_official | 87:085cde657901 | 1108 | |
| mbed_official | 532:fe11edbda85c | 1109 | |
| mbed_official | 87:085cde657901 | 1110 | /** |
| mbed_official | 87:085cde657901 | 1111 | * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt |
| mbed_official | 226:b062af740e40 | 1112 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 226:b062af740e40 | 1113 | * the configuration information for I2S module |
| mbed_official | 87:085cde657901 | 1114 | * @retval HAL status |
| mbed_official | 87:085cde657901 | 1115 | */ |
| mbed_official | 87:085cde657901 | 1116 | HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s) |
| mbed_official | 87:085cde657901 | 1117 | { |
| mbed_official | 87:085cde657901 | 1118 | uint32_t tmp1 = 0, tmp2 = 0; |
| mbed_official | 87:085cde657901 | 1119 | |
| mbed_official | 87:085cde657901 | 1120 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
| mbed_official | 87:085cde657901 | 1121 | { |
| mbed_official | 87:085cde657901 | 1122 | /* Process Locked */ |
| mbed_official | 87:085cde657901 | 1123 | __HAL_LOCK(hi2s); |
| mbed_official | 87:085cde657901 | 1124 | |
| mbed_official | 87:085cde657901 | 1125 | tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 1126 | tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG; |
| mbed_official | 87:085cde657901 | 1127 | /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */ |
| mbed_official | 87:085cde657901 | 1128 | if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX)) |
| mbed_official | 87:085cde657901 | 1129 | { |
| mbed_official | 87:085cde657901 | 1130 | if(hi2s->TxXferCount != 0) |
| mbed_official | 87:085cde657901 | 1131 | { |
| mbed_official | 87:085cde657901 | 1132 | if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET) |
| mbed_official | 87:085cde657901 | 1133 | { |
| mbed_official | 87:085cde657901 | 1134 | /* Transmit data */ |
| mbed_official | 87:085cde657901 | 1135 | hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); |
| mbed_official | 87:085cde657901 | 1136 | hi2s->TxXferCount--; |
| mbed_official | 87:085cde657901 | 1137 | |
| mbed_official | 87:085cde657901 | 1138 | if(hi2s->TxXferCount == 0) |
| mbed_official | 87:085cde657901 | 1139 | { |
| mbed_official | 87:085cde657901 | 1140 | /* Disable TXE interrupt */ |
| mbed_official | 87:085cde657901 | 1141 | __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE); |
| mbed_official | 87:085cde657901 | 1142 | } |
| mbed_official | 87:085cde657901 | 1143 | } |
| mbed_official | 87:085cde657901 | 1144 | } |
| mbed_official | 87:085cde657901 | 1145 | |
| mbed_official | 87:085cde657901 | 1146 | if(hi2s->RxXferCount != 0) |
| mbed_official | 87:085cde657901 | 1147 | { |
| mbed_official | 87:085cde657901 | 1148 | if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE) |
| mbed_official | 87:085cde657901 | 1149 | { |
| mbed_official | 87:085cde657901 | 1150 | /* Receive data */ |
| mbed_official | 87:085cde657901 | 1151 | (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR; |
| mbed_official | 87:085cde657901 | 1152 | hi2s->RxXferCount--; |
| mbed_official | 87:085cde657901 | 1153 | |
| mbed_official | 87:085cde657901 | 1154 | if(hi2s->RxXferCount == 0) |
| mbed_official | 87:085cde657901 | 1155 | { |
| mbed_official | 87:085cde657901 | 1156 | /* Disable I2Sext RXNE interrupt */ |
| mbed_official | 87:085cde657901 | 1157 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE; |
| mbed_official | 87:085cde657901 | 1158 | } |
| mbed_official | 87:085cde657901 | 1159 | } |
| mbed_official | 87:085cde657901 | 1160 | } |
| mbed_official | 87:085cde657901 | 1161 | } |
| mbed_official | 87:085cde657901 | 1162 | /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */ |
| mbed_official | 87:085cde657901 | 1163 | else |
| mbed_official | 87:085cde657901 | 1164 | { |
| mbed_official | 87:085cde657901 | 1165 | if(hi2s->TxXferCount != 0) |
| mbed_official | 87:085cde657901 | 1166 | { |
| mbed_official | 87:085cde657901 | 1167 | if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE) |
| mbed_official | 87:085cde657901 | 1168 | { |
| mbed_official | 87:085cde657901 | 1169 | /* Transmit data */ |
| mbed_official | 87:085cde657901 | 1170 | I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++); |
| mbed_official | 87:085cde657901 | 1171 | hi2s->TxXferCount--; |
| mbed_official | 87:085cde657901 | 1172 | |
| mbed_official | 87:085cde657901 | 1173 | if(hi2s->TxXferCount == 0) |
| mbed_official | 87:085cde657901 | 1174 | { |
| mbed_official | 87:085cde657901 | 1175 | /* Disable I2Sext TXE interrupt */ |
| mbed_official | 87:085cde657901 | 1176 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE; |
| mbed_official | 87:085cde657901 | 1177 | |
| mbed_official | 87:085cde657901 | 1178 | HAL_I2S_TxCpltCallback(hi2s); |
| mbed_official | 87:085cde657901 | 1179 | } |
| mbed_official | 87:085cde657901 | 1180 | } |
| mbed_official | 87:085cde657901 | 1181 | } |
| mbed_official | 87:085cde657901 | 1182 | if(hi2s->RxXferCount != 0) |
| mbed_official | 87:085cde657901 | 1183 | { |
| mbed_official | 87:085cde657901 | 1184 | if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET) |
| mbed_official | 87:085cde657901 | 1185 | { |
| mbed_official | 87:085cde657901 | 1186 | /* Receive data */ |
| mbed_official | 87:085cde657901 | 1187 | (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; |
| mbed_official | 87:085cde657901 | 1188 | hi2s->RxXferCount--; |
| mbed_official | 87:085cde657901 | 1189 | |
| mbed_official | 87:085cde657901 | 1190 | if(hi2s->RxXferCount == 0) |
| mbed_official | 87:085cde657901 | 1191 | { |
| mbed_official | 87:085cde657901 | 1192 | /* Disable RXNE interrupt */ |
| mbed_official | 87:085cde657901 | 1193 | __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE); |
| mbed_official | 87:085cde657901 | 1194 | |
| mbed_official | 87:085cde657901 | 1195 | HAL_I2S_RxCpltCallback(hi2s); |
| mbed_official | 87:085cde657901 | 1196 | } |
| mbed_official | 87:085cde657901 | 1197 | } |
| mbed_official | 87:085cde657901 | 1198 | } |
| mbed_official | 87:085cde657901 | 1199 | } |
| mbed_official | 87:085cde657901 | 1200 | |
| mbed_official | 87:085cde657901 | 1201 | tmp1 = hi2s->RxXferCount; |
| mbed_official | 87:085cde657901 | 1202 | tmp2 = hi2s->TxXferCount; |
| mbed_official | 87:085cde657901 | 1203 | if((tmp1 == 0) && (tmp2 == 0)) |
| mbed_official | 87:085cde657901 | 1204 | { |
| mbed_official | 87:085cde657901 | 1205 | /* Disable I2Sx ERR interrupt */ |
| mbed_official | 87:085cde657901 | 1206 | __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR); |
| mbed_official | 87:085cde657901 | 1207 | /* Disable I2Sext ERR interrupt */ |
| mbed_official | 87:085cde657901 | 1208 | I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR; |
| mbed_official | 87:085cde657901 | 1209 | |
| mbed_official | 87:085cde657901 | 1210 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 87:085cde657901 | 1211 | } |
| mbed_official | 87:085cde657901 | 1212 | |
| mbed_official | 87:085cde657901 | 1213 | /* Process Unlocked */ |
| mbed_official | 87:085cde657901 | 1214 | __HAL_UNLOCK(hi2s); |
| mbed_official | 87:085cde657901 | 1215 | |
| mbed_official | 87:085cde657901 | 1216 | return HAL_OK; |
| mbed_official | 87:085cde657901 | 1217 | } |
| mbed_official | 87:085cde657901 | 1218 | else |
| mbed_official | 87:085cde657901 | 1219 | { |
| mbed_official | 87:085cde657901 | 1220 | return HAL_BUSY; |
| mbed_official | 87:085cde657901 | 1221 | } |
| mbed_official | 87:085cde657901 | 1222 | } |
| mbed_official | 532:fe11edbda85c | 1223 | #endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */ |
| mbed_official | 532:fe11edbda85c | 1224 | /** |
| mbed_official | 532:fe11edbda85c | 1225 | * @brief DMA I2S transmit process complete callback |
| mbed_official | 532:fe11edbda85c | 1226 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 1227 | * the configuration information for the specified DMA module. |
| mbed_official | 532:fe11edbda85c | 1228 | * @retval None |
| mbed_official | 532:fe11edbda85c | 1229 | */ |
| mbed_official | 532:fe11edbda85c | 1230 | void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 532:fe11edbda85c | 1231 | { |
| mbed_official | 532:fe11edbda85c | 1232 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
| mbed_official | 532:fe11edbda85c | 1233 | |
| mbed_official | 532:fe11edbda85c | 1234 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
| mbed_official | 532:fe11edbda85c | 1235 | { |
| mbed_official | 532:fe11edbda85c | 1236 | hi2s->TxXferCount = 0; |
| mbed_official | 87:085cde657901 | 1237 | |
| mbed_official | 532:fe11edbda85c | 1238 | /* Disable Tx DMA Request */ |
| mbed_official | 532:fe11edbda85c | 1239 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
| mbed_official | 532:fe11edbda85c | 1240 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| mbed_official | 532:fe11edbda85c | 1241 | defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
| mbed_official | 532:fe11edbda85c | 1242 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| mbed_official | 532:fe11edbda85c | 1243 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
| mbed_official | 532:fe11edbda85c | 1244 | { |
| mbed_official | 532:fe11edbda85c | 1245 | /* Disable Rx DMA Request for the slave*/ |
| mbed_official | 532:fe11edbda85c | 1246 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
| mbed_official | 532:fe11edbda85c | 1247 | } |
| mbed_official | 532:fe11edbda85c | 1248 | #endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */ |
| mbed_official | 532:fe11edbda85c | 1249 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
| mbed_official | 532:fe11edbda85c | 1250 | { |
| mbed_official | 532:fe11edbda85c | 1251 | if(hi2s->RxXferCount == 0) |
| mbed_official | 532:fe11edbda85c | 1252 | { |
| mbed_official | 532:fe11edbda85c | 1253 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 532:fe11edbda85c | 1254 | } |
| mbed_official | 532:fe11edbda85c | 1255 | } |
| mbed_official | 532:fe11edbda85c | 1256 | else |
| mbed_official | 532:fe11edbda85c | 1257 | { |
| mbed_official | 532:fe11edbda85c | 1258 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 532:fe11edbda85c | 1259 | } |
| mbed_official | 532:fe11edbda85c | 1260 | } |
| mbed_official | 532:fe11edbda85c | 1261 | HAL_I2S_TxCpltCallback(hi2s); |
| mbed_official | 532:fe11edbda85c | 1262 | } |
| mbed_official | 532:fe11edbda85c | 1263 | |
| mbed_official | 532:fe11edbda85c | 1264 | /** |
| mbed_official | 532:fe11edbda85c | 1265 | * @brief DMA I2S receive process complete callback |
| mbed_official | 532:fe11edbda85c | 1266 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 1267 | * the configuration information for the specified DMA module. |
| mbed_official | 532:fe11edbda85c | 1268 | * @retval None |
| mbed_official | 532:fe11edbda85c | 1269 | */ |
| mbed_official | 532:fe11edbda85c | 1270 | void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 532:fe11edbda85c | 1271 | { |
| mbed_official | 532:fe11edbda85c | 1272 | I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
| mbed_official | 532:fe11edbda85c | 1273 | |
| mbed_official | 532:fe11edbda85c | 1274 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
| mbed_official | 532:fe11edbda85c | 1275 | { |
| mbed_official | 532:fe11edbda85c | 1276 | /* Disable Rx DMA Request */ |
| mbed_official | 532:fe11edbda85c | 1277 | hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); |
| mbed_official | 532:fe11edbda85c | 1278 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| mbed_official | 532:fe11edbda85c | 1279 | defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
| mbed_official | 532:fe11edbda85c | 1280 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) |
| mbed_official | 532:fe11edbda85c | 1281 | if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) |
| mbed_official | 532:fe11edbda85c | 1282 | { |
| mbed_official | 532:fe11edbda85c | 1283 | /* Disable Tx DMA Request for the slave*/ |
| mbed_official | 532:fe11edbda85c | 1284 | I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); |
| mbed_official | 532:fe11edbda85c | 1285 | } |
| mbed_official | 532:fe11edbda85c | 1286 | #endif /* STM32F40xxx/ STM32F41xxx/ STM32F42xxx/ STM32F43xxx/ STM32F401xx/ STM32F411xx */ |
| mbed_official | 532:fe11edbda85c | 1287 | hi2s->RxXferCount = 0; |
| mbed_official | 532:fe11edbda85c | 1288 | if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) |
| mbed_official | 532:fe11edbda85c | 1289 | { |
| mbed_official | 532:fe11edbda85c | 1290 | if(hi2s->TxXferCount == 0) |
| mbed_official | 532:fe11edbda85c | 1291 | { |
| mbed_official | 532:fe11edbda85c | 1292 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 532:fe11edbda85c | 1293 | } |
| mbed_official | 532:fe11edbda85c | 1294 | } |
| mbed_official | 532:fe11edbda85c | 1295 | else |
| mbed_official | 532:fe11edbda85c | 1296 | { |
| mbed_official | 532:fe11edbda85c | 1297 | hi2s->State = HAL_I2S_STATE_READY; |
| mbed_official | 532:fe11edbda85c | 1298 | } |
| mbed_official | 532:fe11edbda85c | 1299 | } |
| mbed_official | 532:fe11edbda85c | 1300 | HAL_I2S_RxCpltCallback(hi2s); |
| mbed_official | 532:fe11edbda85c | 1301 | } |
| mbed_official | 532:fe11edbda85c | 1302 | |
| mbed_official | 532:fe11edbda85c | 1303 | /** |
| mbed_official | 532:fe11edbda85c | 1304 | * @brief Get I2S clock Input based on Source clock selection in RCC |
| mbed_official | 532:fe11edbda85c | 1305 | * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains |
| mbed_official | 532:fe11edbda85c | 1306 | * the configuration information for I2S module |
| mbed_official | 532:fe11edbda85c | 1307 | * @retval I2S Clock Input |
| mbed_official | 532:fe11edbda85c | 1308 | */ |
| mbed_official | 532:fe11edbda85c | 1309 | uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s) |
| mbed_official | 532:fe11edbda85c | 1310 | { |
| mbed_official | 532:fe11edbda85c | 1311 | /* This variable used to store the VCO Input (value in Hz) */ |
| mbed_official | 532:fe11edbda85c | 1312 | uint32_t vcoinput = 0; |
| mbed_official | 532:fe11edbda85c | 1313 | /* This variable used to store the VCO Output (value in Hz) */ |
| mbed_official | 532:fe11edbda85c | 1314 | uint32_t vcooutput = 0; |
| mbed_official | 532:fe11edbda85c | 1315 | /* This variable used to store the I2S_CK_x (value in Hz) */ |
| mbed_official | 532:fe11edbda85c | 1316 | uint32_t i2ssourceclock = 0; |
| mbed_official | 532:fe11edbda85c | 1317 | |
| mbed_official | 532:fe11edbda85c | 1318 | /* Configure SAI Clock based on SAI source clock selection */ |
| mbed_official | 532:fe11edbda85c | 1319 | #if defined(STM32F446xx) |
| mbed_official | 532:fe11edbda85c | 1320 | switch(hi2s->Init.ClockSource) |
| mbed_official | 532:fe11edbda85c | 1321 | { |
| mbed_official | 532:fe11edbda85c | 1322 | case I2S_CLOCK_EXTERNAL : |
| mbed_official | 532:fe11edbda85c | 1323 | { |
| mbed_official | 532:fe11edbda85c | 1324 | /* Set the I2S clock to the external clock value */ |
| mbed_official | 532:fe11edbda85c | 1325 | i2ssourceclock = EXTERNAL_CLOCK_VALUE; |
| mbed_official | 532:fe11edbda85c | 1326 | break; |
| mbed_official | 532:fe11edbda85c | 1327 | } |
| mbed_official | 532:fe11edbda85c | 1328 | case I2S_CLOCK_PLL : |
| mbed_official | 532:fe11edbda85c | 1329 | { |
| mbed_official | 532:fe11edbda85c | 1330 | /* Configure the PLLI2S division factor */ |
| mbed_official | 532:fe11edbda85c | 1331 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ |
| mbed_official | 532:fe11edbda85c | 1332 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) |
| mbed_official | 532:fe11edbda85c | 1333 | { |
| mbed_official | 532:fe11edbda85c | 1334 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1335 | vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); |
| mbed_official | 532:fe11edbda85c | 1336 | } |
| mbed_official | 532:fe11edbda85c | 1337 | else |
| mbed_official | 532:fe11edbda85c | 1338 | { |
| mbed_official | 532:fe11edbda85c | 1339 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1340 | vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); |
| mbed_official | 532:fe11edbda85c | 1341 | } |
| mbed_official | 532:fe11edbda85c | 1342 | |
| mbed_official | 532:fe11edbda85c | 1343 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
| mbed_official | 532:fe11edbda85c | 1344 | vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6))); |
| mbed_official | 532:fe11edbda85c | 1345 | /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ |
| mbed_official | 532:fe11edbda85c | 1346 | i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28))); |
| mbed_official | 532:fe11edbda85c | 1347 | break; |
| mbed_official | 532:fe11edbda85c | 1348 | } |
| mbed_official | 532:fe11edbda85c | 1349 | case I2S_CLOCK_PLLR : |
| mbed_official | 532:fe11edbda85c | 1350 | { |
| mbed_official | 532:fe11edbda85c | 1351 | /* Configure the PLLI2S division factor */ |
| mbed_official | 532:fe11edbda85c | 1352 | /* PLL_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 532:fe11edbda85c | 1353 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) |
| mbed_official | 532:fe11edbda85c | 1354 | { |
| mbed_official | 532:fe11edbda85c | 1355 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1356 | vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| mbed_official | 532:fe11edbda85c | 1357 | } |
| mbed_official | 532:fe11edbda85c | 1358 | else |
| mbed_official | 532:fe11edbda85c | 1359 | { |
| mbed_official | 532:fe11edbda85c | 1360 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1361 | vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| mbed_official | 532:fe11edbda85c | 1362 | } |
| mbed_official | 532:fe11edbda85c | 1363 | |
| mbed_official | 532:fe11edbda85c | 1364 | /* PLL_VCO Output = PLL_VCO Input * PLLN */ |
| mbed_official | 532:fe11edbda85c | 1365 | vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6) & (RCC_PLLCFGR_PLLN >> 6))); |
| mbed_official | 532:fe11edbda85c | 1366 | /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ |
| mbed_official | 532:fe11edbda85c | 1367 | i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28) & (RCC_PLLCFGR_PLLR >> 28))); |
| mbed_official | 532:fe11edbda85c | 1368 | break; |
| mbed_official | 532:fe11edbda85c | 1369 | } |
| mbed_official | 532:fe11edbda85c | 1370 | case I2S_CLOCK_PLLSRC : |
| mbed_official | 532:fe11edbda85c | 1371 | { |
| mbed_official | 532:fe11edbda85c | 1372 | /* Configure the PLLI2S division factor */ |
| mbed_official | 532:fe11edbda85c | 1373 | /* PLL_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 532:fe11edbda85c | 1374 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) |
| mbed_official | 532:fe11edbda85c | 1375 | { |
| mbed_official | 532:fe11edbda85c | 1376 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1377 | i2ssourceclock = (uint32_t)(HSE_VALUE); |
| mbed_official | 532:fe11edbda85c | 1378 | } |
| mbed_official | 532:fe11edbda85c | 1379 | else |
| mbed_official | 532:fe11edbda85c | 1380 | { |
| mbed_official | 532:fe11edbda85c | 1381 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1382 | i2ssourceclock = (uint32_t)(HSI_VALUE); |
| mbed_official | 532:fe11edbda85c | 1383 | } |
| mbed_official | 532:fe11edbda85c | 1384 | break; |
| mbed_official | 532:fe11edbda85c | 1385 | } |
| mbed_official | 532:fe11edbda85c | 1386 | default : |
| mbed_official | 532:fe11edbda85c | 1387 | { |
| mbed_official | 532:fe11edbda85c | 1388 | break; |
| mbed_official | 532:fe11edbda85c | 1389 | } |
| mbed_official | 532:fe11edbda85c | 1390 | } |
| mbed_official | 532:fe11edbda85c | 1391 | #endif /* STM32F446xx */ |
| mbed_official | 532:fe11edbda85c | 1392 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
| mbed_official | 532:fe11edbda85c | 1393 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| mbed_official | 532:fe11edbda85c | 1394 | defined(STM32F401xC) || defined(STM32F401xE) |
| mbed_official | 532:fe11edbda85c | 1395 | |
| mbed_official | 532:fe11edbda85c | 1396 | /* If an external I2S clock has to be used, the specific define should be set |
| mbed_official | 532:fe11edbda85c | 1397 | in the project configuration or in the stm32f4xx_conf.h file */ |
| mbed_official | 532:fe11edbda85c | 1398 | if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL) |
| mbed_official | 532:fe11edbda85c | 1399 | { |
| mbed_official | 532:fe11edbda85c | 1400 | /* Enable the External Clock selection */ |
| mbed_official | 532:fe11edbda85c | 1401 | __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT); |
| mbed_official | 532:fe11edbda85c | 1402 | |
| mbed_official | 532:fe11edbda85c | 1403 | /* Set the I2S clock to the external clock value */ |
| mbed_official | 532:fe11edbda85c | 1404 | i2ssourceclock = EXTERNAL_CLOCK_VALUE; |
| mbed_official | 532:fe11edbda85c | 1405 | } |
| mbed_official | 532:fe11edbda85c | 1406 | else |
| mbed_official | 532:fe11edbda85c | 1407 | { |
| mbed_official | 532:fe11edbda85c | 1408 | /* Configure the PLLI2S division factor */ |
| mbed_official | 532:fe11edbda85c | 1409 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ |
| mbed_official | 532:fe11edbda85c | 1410 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) |
| mbed_official | 532:fe11edbda85c | 1411 | { |
| mbed_official | 532:fe11edbda85c | 1412 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1413 | vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| mbed_official | 532:fe11edbda85c | 1414 | } |
| mbed_official | 532:fe11edbda85c | 1415 | else |
| mbed_official | 532:fe11edbda85c | 1416 | { |
| mbed_official | 532:fe11edbda85c | 1417 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1418 | vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); |
| mbed_official | 532:fe11edbda85c | 1419 | } |
| mbed_official | 532:fe11edbda85c | 1420 | |
| mbed_official | 532:fe11edbda85c | 1421 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
| mbed_official | 532:fe11edbda85c | 1422 | vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6))); |
| mbed_official | 532:fe11edbda85c | 1423 | /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ |
| mbed_official | 532:fe11edbda85c | 1424 | i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28))); |
| mbed_official | 532:fe11edbda85c | 1425 | } |
| mbed_official | 532:fe11edbda85c | 1426 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */ |
| mbed_official | 532:fe11edbda85c | 1427 | |
| mbed_official | 532:fe11edbda85c | 1428 | #if defined(STM32F411xE) |
| mbed_official | 532:fe11edbda85c | 1429 | |
| mbed_official | 532:fe11edbda85c | 1430 | /* If an external I2S clock has to be used, the specific define should be set |
| mbed_official | 532:fe11edbda85c | 1431 | in the project configuration or in the stm32f4xx_conf.h file */ |
| mbed_official | 532:fe11edbda85c | 1432 | if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL) |
| mbed_official | 532:fe11edbda85c | 1433 | { |
| mbed_official | 532:fe11edbda85c | 1434 | /* Enable the External Clock selection */ |
| mbed_official | 532:fe11edbda85c | 1435 | __HAL_RCC_I2S_CONFIG(RCC_I2SCLKSOURCE_EXT); |
| mbed_official | 532:fe11edbda85c | 1436 | |
| mbed_official | 532:fe11edbda85c | 1437 | /* Set the I2S clock to the external clock value */ |
| mbed_official | 532:fe11edbda85c | 1438 | i2ssourceclock = EXTERNAL_CLOCK_VALUE; |
| mbed_official | 532:fe11edbda85c | 1439 | } |
| mbed_official | 532:fe11edbda85c | 1440 | else |
| mbed_official | 532:fe11edbda85c | 1441 | { |
| mbed_official | 532:fe11edbda85c | 1442 | /* Configure the PLLI2S division factor */ |
| mbed_official | 532:fe11edbda85c | 1443 | /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ |
| mbed_official | 532:fe11edbda85c | 1444 | if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) |
| mbed_official | 532:fe11edbda85c | 1445 | { |
| mbed_official | 532:fe11edbda85c | 1446 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1447 | vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); |
| mbed_official | 532:fe11edbda85c | 1448 | } |
| mbed_official | 532:fe11edbda85c | 1449 | else |
| mbed_official | 532:fe11edbda85c | 1450 | { |
| mbed_official | 532:fe11edbda85c | 1451 | /* Get the I2S source clock value */ |
| mbed_official | 532:fe11edbda85c | 1452 | vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); |
| mbed_official | 532:fe11edbda85c | 1453 | } |
| mbed_official | 532:fe11edbda85c | 1454 | |
| mbed_official | 532:fe11edbda85c | 1455 | /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ |
| mbed_official | 532:fe11edbda85c | 1456 | vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6))); |
| mbed_official | 532:fe11edbda85c | 1457 | /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ |
| mbed_official | 532:fe11edbda85c | 1458 | i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28))); |
| mbed_official | 532:fe11edbda85c | 1459 | } |
| mbed_official | 532:fe11edbda85c | 1460 | #endif /* STM32F411xE */ |
| mbed_official | 532:fe11edbda85c | 1461 | |
| mbed_official | 532:fe11edbda85c | 1462 | /* the return result is the value of SAI clock */ |
| mbed_official | 532:fe11edbda85c | 1463 | return i2ssourceclock; |
| mbed_official | 532:fe11edbda85c | 1464 | |
| mbed_official | 532:fe11edbda85c | 1465 | } |
| mbed_official | 87:085cde657901 | 1466 | /** |
| mbed_official | 87:085cde657901 | 1467 | * @} |
| mbed_official | 87:085cde657901 | 1468 | */ |
| mbed_official | 87:085cde657901 | 1469 | |
| mbed_official | 87:085cde657901 | 1470 | #endif /* HAL_I2S_MODULE_ENABLED */ |
| mbed_official | 87:085cde657901 | 1471 | /** |
| mbed_official | 87:085cde657901 | 1472 | * @} |
| mbed_official | 87:085cde657901 | 1473 | */ |
| mbed_official | 87:085cde657901 | 1474 | |
| mbed_official | 87:085cde657901 | 1475 | /** |
| mbed_official | 87:085cde657901 | 1476 | * @} |
| mbed_official | 87:085cde657901 | 1477 | */ |
| mbed_official | 87:085cde657901 | 1478 | |
| mbed_official | 87:085cde657901 | 1479 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |