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targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:: mbed_official
Date:: Fri Jul 17 09:15:10 2015 +0100
Revision:: 592:a274ee790e56
Parent:: 579:53297373a894

Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6

Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/

More API implementation for SAMR21

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User	Revision	Line number	New contents of line
mbed_official	579:53297373a894	1	#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED
mbed_official	579:53297373a894	2	#define SYSTEM_CLOCK_FEATURE_H_INCLUDED
mbed_official	579:53297373a894	3
mbed_official	579:53297373a894	4	#ifdef __cplusplus
mbed_official	579:53297373a894	5	extern "C" {
mbed_official	579:53297373a894	6	#endif
mbed_official	579:53297373a894	7
mbed_official	579:53297373a894	8	/**
mbed_official	579:53297373a894	9	* \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management Driver (SYSTEM CLOCK)
mbed_official	579:53297373a894	10	*
mbed_official	579:53297373a894	11	* This driver for Atmel庐 \| SMART SAM devices provides an interface for the configuration
mbed_official	579:53297373a894	12	* and management of the device's clocking related functions. This includes
mbed_official	579:53297373a894	13	* the various clock sources, bus clocks, and generic clocks within the device,
mbed_official	579:53297373a894	14	* with functions to manage the enabling, disabling, source selection, and
mbed_official	579:53297373a894	15	* prescaling of clocks to various internal peripherals.
mbed_official	579:53297373a894	16	*
mbed_official	579:53297373a894	17	* The following peripherals are used by this module:
mbed_official	579:53297373a894	18	*
mbed_official	579:53297373a894	19	* - GCLK (Generic Clock Management)
mbed_official	579:53297373a894	20	* - PM (Power Management)
mbed_official	579:53297373a894	21	* - SYSCTRL (Clock Source Control)
mbed_official	579:53297373a894	22	*
mbed_official	579:53297373a894	23	* The following devices can use this module:
mbed_official	579:53297373a894	24	* - Atmel \| SMART SAM D20/D21
mbed_official	579:53297373a894	25	* - Atmel \| SMART SAM R21
mbed_official	579:53297373a894	26	* - Atmel \| SMART SAM D10/D11
mbed_official	579:53297373a894	27	*
mbed_official	579:53297373a894	28	* The outline of this documentation is as follows:
mbed_official	579:53297373a894	29	* - \ref asfdoc_sam0_system_clock_prerequisites
mbed_official	579:53297373a894	30	* - \ref asfdoc_sam0_system_clock_module_overview
mbed_official	579:53297373a894	31	* - \ref asfdoc_sam0_system_clock_special_considerations
mbed_official	579:53297373a894	32	* - \ref asfdoc_sam0_system_clock_extra_info
mbed_official	579:53297373a894	33	* - \ref asfdoc_sam0_system_clock_examples
mbed_official	579:53297373a894	34	* - \ref asfdoc_sam0_system_clock_api_overview
mbed_official	579:53297373a894	35	*
mbed_official	579:53297373a894	36	*
mbed_official	579:53297373a894	37	* \section asfdoc_sam0_system_clock_prerequisites Prerequisites
mbed_official	579:53297373a894	38	*
mbed_official	579:53297373a894	39	* There are no prerequisites for this module.
mbed_official	579:53297373a894	40	*
mbed_official	579:53297373a894	41	*
mbed_official	579:53297373a894	42	* \section asfdoc_sam0_system_clock_module_overview Module Overview
mbed_official	579:53297373a894	43	* The SAM devices contain a sophisticated clocking system, which is designed
mbed_official	579:53297373a894	44	* to give the maximum flexibility to the user application. This system allows
mbed_official	579:53297373a894	45	* a system designer to tune the performance and power consumption of the device
mbed_official	579:53297373a894	46	* in a dynamic manner, to achieve the best trade-off between the two for a
mbed_official	579:53297373a894	47	* particular application.
mbed_official	579:53297373a894	48	*
mbed_official	579:53297373a894	49	* This driver provides a set of functions for the configuration and management
mbed_official	579:53297373a894	50	* of the various clock related functionality within the device.
mbed_official	579:53297373a894	51	*
mbed_official	579:53297373a894	52	* \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
mbed_official	579:53297373a894	53	* <table>
mbed_official	579:53297373a894	54	* <tr>
mbed_official	579:53297373a894	55	* <th>Driver Feature Macro</th>
mbed_official	579:53297373a894	56	* <th>Supported devices</th>
mbed_official	579:53297373a894	57	* </tr>
mbed_official	579:53297373a894	58	* <tr>
mbed_official	579:53297373a894	59	* <td>FEATURE_SYSTEM_CLOCK_DPLL</td>
mbed_official	579:53297373a894	60	* <td>SAMD21, SAMR21, SAMD10, SAMD11</td>
mbed_official	579:53297373a894	61	* </tr>
mbed_official	579:53297373a894	62	* </table>
mbed_official	579:53297373a894	63	* \note The specific features are only available in the driver when the
mbed_official	579:53297373a894	64	* selected device supports those features.
mbed_official	579:53297373a894	65	*
mbed_official	579:53297373a894	66	* \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources
mbed_official	579:53297373a894	67	* The SAM devices have a number of master clock source modules, each of
mbed_official	579:53297373a894	68	* which being capable of producing a stabilized output frequency, which can then
mbed_official	579:53297373a894	69	* be fed into the various peripherals and modules within the device.
mbed_official	579:53297373a894	70	*
mbed_official	579:53297373a894	71	* Possible clock source modules include internal R/C oscillators, internal
mbed_official	579:53297373a894	72	* DFLL modules, as well as external crystal oscillators and/or clock inputs.
mbed_official	579:53297373a894	73	*
mbed_official	579:53297373a894	74	* \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks
mbed_official	579:53297373a894	75	* The CPU and AHB/APBx buses are clocked by the same physical clock source
mbed_official	579:53297373a894	76	* (referred in this module as the Main Clock), however the APBx buses may
mbed_official	579:53297373a894	77	* have additional prescaler division ratios set to give each peripheral bus a
mbed_official	579:53297373a894	78	* different clock speed.
mbed_official	579:53297373a894	79	*
mbed_official	579:53297373a894	80	* The general main clock tree for the CPU and associated buses is shown in
mbed_official	579:53297373a894	81	* \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below".
mbed_official	579:53297373a894	82	*
mbed_official	579:53297373a894	83	* \anchor asfdoc_sam0_system_clock_module_clock_tree
mbed_official	579:53297373a894	84	* \dot
mbed_official	579:53297373a894	85	* digraph overview {
mbed_official	579:53297373a894	86	* rankdir=LR;
mbed_official	579:53297373a894	87	* clk_src [label="Clock Sources", shape=none, height=0];
mbed_official	579:53297373a894	88	* node [label="CPU Bus" shape=ellipse] cpu_bus;
mbed_official	579:53297373a894	89	* node [label="AHB Bus" shape=ellipse] ahb_bus;
mbed_official	579:53297373a894	90	* node [label="APBA Bus" shape=ellipse] apb_a_bus;
mbed_official	579:53297373a894	91	* node [label="APBB Bus" shape=ellipse] apb_b_bus;
mbed_official	579:53297373a894	92	* node [label="APBC Bus" shape=ellipse] apb_c_bus;
mbed_official	579:53297373a894	93	* node [label="Main Bus\nPrescaler" shape=square] main_prescaler;
mbed_official	579:53297373a894	94	* node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler;
mbed_official	579:53297373a894	95	* node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler;
mbed_official	579:53297373a894	96	* node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler;
mbed_official	579:53297373a894	97	* node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux;
mbed_official	579:53297373a894	98	*
mbed_official	579:53297373a894	99	* clk_src -> main_clock_mux;
mbed_official	579:53297373a894	100	* main_clock_mux -> main_prescaler;
mbed_official	579:53297373a894	101	* main_prescaler -> cpu_bus;
mbed_official	579:53297373a894	102	* main_prescaler -> ahb_bus;
mbed_official	579:53297373a894	103	* main_prescaler -> apb_a_prescaler;
mbed_official	579:53297373a894	104	* main_prescaler -> apb_b_prescaler;
mbed_official	579:53297373a894	105	* main_prescaler -> apb_c_prescaler;
mbed_official	579:53297373a894	106	* apb_a_prescaler -> apb_a_bus;
mbed_official	579:53297373a894	107	* apb_b_prescaler -> apb_b_bus;
mbed_official	579:53297373a894	108	* apb_c_prescaler -> apb_c_bus;
mbed_official	579:53297373a894	109	* }
mbed_official	579:53297373a894	110	* \enddot
mbed_official	579:53297373a894	111	*
mbed_official	579:53297373a894	112	* \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking
mbed_official	579:53297373a894	113	* To save power, the input clock to one or more peripherals on the AHB and APBx
mbed_official	579:53297373a894	114	* buses can be masked away - when masked, no clock is passed into the module.
mbed_official	579:53297373a894	115	* Disabling of clocks of unused modules will prevent all access to the masked
mbed_official	579:53297373a894	116	* module, but will reduce the overall device power consumption.
mbed_official	579:53297373a894	117	*
mbed_official	579:53297373a894	118	* \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks
mbed_official	579:53297373a894	119	* Within the SAM devices there are a number of Generic Clocks; these are used to
mbed_official	579:53297373a894	120	* provide clocks to the various peripheral clock domains in the device in a
mbed_official	579:53297373a894	121	* standardized manner. One or more master source clocks can be selected as the
mbed_official	579:53297373a894	122	* input clock to a Generic Clock Generator, which can prescale down the input
mbed_official	579:53297373a894	123	* frequency to a slower rate for use in a peripheral.
mbed_official	579:53297373a894	124	*
mbed_official	579:53297373a894	125	* Additionally, a number of individually selectable Generic Clock Channels are
mbed_official	579:53297373a894	126	* provided, which multiplex and gate the various generator outputs for one or
mbed_official	579:53297373a894	127	* more peripherals within the device. This setup allows for a single common
mbed_official	579:53297373a894	128	* generator to feed one or more channels, which can then be enabled or disabled
mbed_official	579:53297373a894	129	* individually as required.
mbed_official	579:53297373a894	130	*
mbed_official	579:53297373a894	131	* \anchor asfdoc_sam0_system_clock_module_chain_overview
mbed_official	579:53297373a894	132	* \dot
mbed_official	579:53297373a894	133	* digraph overview {
mbed_official	579:53297373a894	134	* rankdir=LR;
mbed_official	579:53297373a894	135	* node [label="Clock\nSource a" shape=square] system_clock_source;
mbed_official	579:53297373a894	136	* node [label="Generator 1" shape=square] clock_gen;
mbed_official	579:53297373a894	137	* node [label="Channel x" shape=square] clock_chan0;
mbed_official	579:53297373a894	138	* node [label="Channel y" shape=square] clock_chan1;
mbed_official	579:53297373a894	139	* node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
mbed_official	579:53297373a894	140	* node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
mbed_official	579:53297373a894	141	*
mbed_official	579:53297373a894	142	* system_clock_source -> clock_gen;
mbed_official	579:53297373a894	143	* clock_gen -> clock_chan0;
mbed_official	579:53297373a894	144	* clock_chan0 -> peripheral0;
mbed_official	579:53297373a894	145	* clock_gen -> clock_chan1;
mbed_official	579:53297373a894	146	* clock_chan1 -> peripheral1;
mbed_official	579:53297373a894	147	* }
mbed_official	579:53297373a894	148	* \enddot
mbed_official	579:53297373a894	149	*
mbed_official	579:53297373a894	150	* \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example
mbed_official	579:53297373a894	151	* An example setup of a complete clock chain within the device is shown in
mbed_official	579:53297373a894	152	* \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below".
mbed_official	579:53297373a894	153	*
mbed_official	579:53297373a894	154	* \anchor asfdoc_sam0_system_clock_module_chain_example_fig
mbed_official	579:53297373a894	155	* \dot
mbed_official	579:53297373a894	156	* digraph overview {
mbed_official	579:53297373a894	157	* rankdir=LR;
mbed_official	579:53297373a894	158	* node [label="External\nOscillator" shape=square] system_clock_source0;
mbed_official	579:53297373a894	159	* node [label="Generator 0" shape=square] clock_gen0;
mbed_official	579:53297373a894	160	* node [label="Channel x" shape=square] clock_chan0;
mbed_official	579:53297373a894	161	* node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0;
mbed_official	579:53297373a894	162	*
mbed_official	579:53297373a894	163	* system_clock_source0 -> clock_gen0;
mbed_official	579:53297373a894	164	* clock_gen0 -> clock_chan0;
mbed_official	579:53297373a894	165	* clock_chan0 -> peripheral0;
mbed_official	579:53297373a894	166	* node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1;
mbed_official	579:53297373a894	167	* node [label="Generator 1" shape=square] clock_gen1;
mbed_official	579:53297373a894	168	* node [label="Channel y" shape=square] clock_chan1;
mbed_official	579:53297373a894	169	* node [label="Channel z" shape=square] clock_chan2;
mbed_official	579:53297373a894	170	* node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1;
mbed_official	579:53297373a894	171	* node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2;
mbed_official	579:53297373a894	172	*
mbed_official	579:53297373a894	173	* system_clock_source1 -> clock_gen1;
mbed_official	579:53297373a894	174	* clock_gen1 -> clock_chan1;
mbed_official	579:53297373a894	175	* clock_gen1 -> clock_chan2;
mbed_official	579:53297373a894	176	* clock_chan1 -> peripheral1;
mbed_official	579:53297373a894	177	* clock_chan2 -> peripheral2;
mbed_official	579:53297373a894	178	* }
mbed_official	579:53297373a894	179	* \enddot
mbed_official	579:53297373a894	180	*
mbed_official	579:53297373a894	181	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators
mbed_official	579:53297373a894	182	* Each Generic Clock generator within the device can source its input clock
mbed_official	579:53297373a894	183	* from one of the provided Source Clocks, and prescale the output for one or
mbed_official	579:53297373a894	184	* more Generic Clock Channels in a one-to-many relationship. The generators
mbed_official	579:53297373a894	185	* thus allow for several clocks to be generated of different frequencies,
mbed_official	579:53297373a894	186	* power usages, and accuracies, which can be turned on and off individually to
mbed_official	579:53297373a894	187	* disable the clocks to multiple peripherals as a group.
mbed_official	579:53297373a894	188	*
mbed_official	579:53297373a894	189	* \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels
mbed_official	579:53297373a894	190	* To connect a Generic Clock Generator to a peripheral within the
mbed_official	579:53297373a894	191	* device, a Generic Clock Channel is used. Each peripheral or
mbed_official	579:53297373a894	192	* peripheral group has an associated Generic Clock Channel, which serves as the
mbed_official	579:53297373a894	193	* clock input for the peripheral(s). To supply a clock to the peripheral
mbed_official	579:53297373a894	194	* module(s), the associated channel must be connected to a running Generic
mbed_official	579:53297373a894	195	* Clock Generator and the channel enabled.
mbed_official	579:53297373a894	196	*
mbed_official	579:53297373a894	197	* \section asfdoc_sam0_system_clock_special_considerations Special Considerations
mbed_official	579:53297373a894	198	*
mbed_official	579:53297373a894	199	* There are no special considerations for this module.
mbed_official	579:53297373a894	200	*
mbed_official	579:53297373a894	201	*
mbed_official	579:53297373a894	202	* \section asfdoc_sam0_system_clock_extra_info Extra Information
mbed_official	579:53297373a894	203	*
mbed_official	579:53297373a894	204	* For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes:
mbed_official	579:53297373a894	205	* - \ref asfdoc_sam0_system_clock_extra_acronyms
mbed_official	579:53297373a894	206	* - \ref asfdoc_sam0_system_clock_extra_dependencies
mbed_official	579:53297373a894	207	* - \ref asfdoc_sam0_system_clock_extra_errata
mbed_official	579:53297373a894	208	* - \ref asfdoc_sam0_system_clock_extra_history
mbed_official	579:53297373a894	209	*
mbed_official	579:53297373a894	210	*
mbed_official	579:53297373a894	211	* \section asfdoc_sam0_system_clock_examples Examples
mbed_official	579:53297373a894	212	*
mbed_official	579:53297373a894	213	* For a list of examples related to this driver, see
mbed_official	579:53297373a894	214	* \ref asfdoc_sam0_system_clock_exqsg.
mbed_official	579:53297373a894	215	*
mbed_official	579:53297373a894	216	*
mbed_official	579:53297373a894	217	* \section asfdoc_sam0_system_clock_api_overview API Overview
mbed_official	579:53297373a894	218	* @{
mbed_official	579:53297373a894	219	*/
mbed_official	579:53297373a894	220
mbed_official	579:53297373a894	221	#include <compiler.h>
mbed_official	579:53297373a894	222
mbed_official	579:53297373a894	223	#include <status_codes.h>
mbed_official	579:53297373a894	224	/**
mbed_official	579:53297373a894	225	* \name Driver Feature Definition
mbed_official	579:53297373a894	226	* Define system clock features set according to different device family.
mbed_official	579:53297373a894	227	* @{
mbed_official	579:53297373a894	228	*/
mbed_official	579:53297373a894	229	#if (SAMD21) \|\| (SAMR21) \|\| (SAMD11) \|\| (SAMD10) \|\| defined(__DOXYGEN__)
mbed_official	579:53297373a894	230	/** Digital Phase Locked Loop (DPLL) feature support. */
mbed_official	579:53297373a894	231	# define FEATURE_SYSTEM_CLOCK_DPLL
mbed_official	579:53297373a894	232	#endif
mbed_official	579:53297373a894	233	/@}/
mbed_official	579:53297373a894	234
mbed_official	579:53297373a894	235	/**
mbed_official	579:53297373a894	236	* \brief Available start-up times for the XOSC32K.
mbed_official	579:53297373a894	237	*
mbed_official	579:53297373a894	238	* Available external 32KHz oscillator start-up times, as a number of external
mbed_official	579:53297373a894	239	* clock cycles.
mbed_official	579:53297373a894	240	*/
mbed_official	579:53297373a894	241	enum system_xosc32k_startup {
mbed_official	579:53297373a894	242	/** Wait zero clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	243	SYSTEM_XOSC32K_STARTUP_0,
mbed_official	579:53297373a894	244	/** Wait 32 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	245	SYSTEM_XOSC32K_STARTUP_32,
mbed_official	579:53297373a894	246	/** Wait 2048 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	247	SYSTEM_XOSC32K_STARTUP_2048,
mbed_official	579:53297373a894	248	/** Wait 4096 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	249	SYSTEM_XOSC32K_STARTUP_4096,
mbed_official	579:53297373a894	250	/** Wait 16384 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	251	SYSTEM_XOSC32K_STARTUP_16384,
mbed_official	579:53297373a894	252	/** Wait 32768 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	253	SYSTEM_XOSC32K_STARTUP_32768,
mbed_official	579:53297373a894	254	/** Wait 65536 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	255	SYSTEM_XOSC32K_STARTUP_65536,
mbed_official	579:53297373a894	256	/** Wait 131072 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	257	SYSTEM_XOSC32K_STARTUP_131072,
mbed_official	579:53297373a894	258	};
mbed_official	579:53297373a894	259
mbed_official	579:53297373a894	260	/**
mbed_official	579:53297373a894	261	* \brief Available start-up times for the XOSC.
mbed_official	579:53297373a894	262	*
mbed_official	579:53297373a894	263	* Available external oscillator start-up times, as a number of external clock
mbed_official	579:53297373a894	264	* cycles.
mbed_official	579:53297373a894	265	*/
mbed_official	579:53297373a894	266	enum system_xosc_startup {
mbed_official	579:53297373a894	267	/** Wait one clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	268	SYSTEM_XOSC_STARTUP_1,
mbed_official	579:53297373a894	269	/** Wait two clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	270	SYSTEM_XOSC_STARTUP_2,
mbed_official	579:53297373a894	271	/** Wait four clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	272	SYSTEM_XOSC_STARTUP_4,
mbed_official	579:53297373a894	273	/** Wait eight clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	274	SYSTEM_XOSC_STARTUP_8,
mbed_official	579:53297373a894	275	/** Wait 16 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	276	SYSTEM_XOSC_STARTUP_16,
mbed_official	579:53297373a894	277	/** Wait 32 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	278	SYSTEM_XOSC_STARTUP_32,
mbed_official	579:53297373a894	279	/** Wait 64 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	280	SYSTEM_XOSC_STARTUP_64,
mbed_official	579:53297373a894	281	/** Wait 128 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	282	SYSTEM_XOSC_STARTUP_128,
mbed_official	579:53297373a894	283	/** Wait 256 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	284	SYSTEM_XOSC_STARTUP_256,
mbed_official	579:53297373a894	285	/** Wait 512 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	286	SYSTEM_XOSC_STARTUP_512,
mbed_official	579:53297373a894	287	/** Wait 1024 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	288	SYSTEM_XOSC_STARTUP_1024,
mbed_official	579:53297373a894	289	/** Wait 2048 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	290	SYSTEM_XOSC_STARTUP_2048,
mbed_official	579:53297373a894	291	/** Wait 4096 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	292	SYSTEM_XOSC_STARTUP_4096,
mbed_official	579:53297373a894	293	/** Wait 8192 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	294	SYSTEM_XOSC_STARTUP_8192,
mbed_official	579:53297373a894	295	/** Wait 16384 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	296	SYSTEM_XOSC_STARTUP_16384,
mbed_official	579:53297373a894	297	/** Wait 32768 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	298	SYSTEM_XOSC_STARTUP_32768,
mbed_official	579:53297373a894	299	};
mbed_official	579:53297373a894	300
mbed_official	579:53297373a894	301	/**
mbed_official	579:53297373a894	302	* \brief Available start-up times for the OSC32K.
mbed_official	579:53297373a894	303	*
mbed_official	579:53297373a894	304	* Available internal 32KHz oscillator start-up times, as a number of internal
mbed_official	579:53297373a894	305	* OSC32K clock cycles.
mbed_official	579:53297373a894	306	*/
mbed_official	579:53297373a894	307	enum system_osc32k_startup {
mbed_official	579:53297373a894	308	/** Wait three clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	309	SYSTEM_OSC32K_STARTUP_3,
mbed_official	579:53297373a894	310	/** Wait four clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	311	SYSTEM_OSC32K_STARTUP_4,
mbed_official	579:53297373a894	312	/** Wait six clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	313	SYSTEM_OSC32K_STARTUP_6,
mbed_official	579:53297373a894	314	/** Wait ten clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	315	SYSTEM_OSC32K_STARTUP_10,
mbed_official	579:53297373a894	316	/** Wait 18 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	317	SYSTEM_OSC32K_STARTUP_18,
mbed_official	579:53297373a894	318	/** Wait 34 clock cycles until the clock source is considered stable */
mbed_official	579:53297373a894	319	SYSTEM_OSC32K_STARTUP_34,
mbed_official	579:53297373a894	320	/** Wait 66 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	321	SYSTEM_OSC32K_STARTUP_66,
mbed_official	579:53297373a894	322	/** Wait 130 clock cycles until the clock source is considered stable. */
mbed_official	579:53297373a894	323	SYSTEM_OSC32K_STARTUP_130,
mbed_official	579:53297373a894	324	};
mbed_official	579:53297373a894	325
mbed_official	579:53297373a894	326	/**
mbed_official	579:53297373a894	327	* \brief Division prescalers for the internal 8MHz system clock.
mbed_official	579:53297373a894	328	*
mbed_official	579:53297373a894	329	* Available prescalers for the internal 8MHz (nominal) system clock.
mbed_official	579:53297373a894	330	*/
mbed_official	579:53297373a894	331	enum system_osc8m_div {
mbed_official	579:53297373a894	332	/** Do not divide the 8MHz RC oscillator output. */
mbed_official	579:53297373a894	333	SYSTEM_OSC8M_DIV_1,
mbed_official	579:53297373a894	334	/** Divide the 8MHz RC oscillator output by two. */
mbed_official	579:53297373a894	335	SYSTEM_OSC8M_DIV_2,
mbed_official	579:53297373a894	336	/** Divide the 8MHz RC oscillator output by four. */
mbed_official	579:53297373a894	337	SYSTEM_OSC8M_DIV_4,
mbed_official	579:53297373a894	338	/** Divide the 8MHz RC oscillator output by eight. */
mbed_official	579:53297373a894	339	SYSTEM_OSC8M_DIV_8,
mbed_official	579:53297373a894	340	};
mbed_official	579:53297373a894	341
mbed_official	579:53297373a894	342	/**
mbed_official	579:53297373a894	343	* \brief Frequency range for the internal 8MHz RC oscillator.
mbed_official	579:53297373a894	344	*
mbed_official	579:53297373a894	345	* Internal 8MHz RC oscillator frequency range setting
mbed_official	579:53297373a894	346	*/
mbed_official	579:53297373a894	347	enum system_osc8m_frequency_range {
mbed_official	579:53297373a894	348	/** Frequency range 4MHz to 6MHz. */
mbed_official	579:53297373a894	349	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
mbed_official	579:53297373a894	350	/** Frequency range 6MHz to 8MHz. */
mbed_official	579:53297373a894	351	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
mbed_official	579:53297373a894	352	/** Frequency range 8MHz to 11MHz. */
mbed_official	579:53297373a894	353	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
mbed_official	579:53297373a894	354	/** Frequency range 11MHz to 15MHz. */
mbed_official	579:53297373a894	355	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
mbed_official	579:53297373a894	356	};
mbed_official	579:53297373a894	357
mbed_official	579:53297373a894	358	/**
mbed_official	579:53297373a894	359	* \brief Main CPU and APB/AHB bus clock source prescaler values.
mbed_official	579:53297373a894	360	*
mbed_official	579:53297373a894	361	* Available division ratios for the CPU and APB/AHB bus clocks.
mbed_official	579:53297373a894	362	*/
mbed_official	579:53297373a894	363	enum system_main_clock_div {
mbed_official	579:53297373a894	364	/** Divide Main clock by one. */
mbed_official	579:53297373a894	365	SYSTEM_MAIN_CLOCK_DIV_1,
mbed_official	579:53297373a894	366	/** Divide Main clock by two. */
mbed_official	579:53297373a894	367	SYSTEM_MAIN_CLOCK_DIV_2,
mbed_official	579:53297373a894	368	/** Divide Main clock by four. */
mbed_official	579:53297373a894	369	SYSTEM_MAIN_CLOCK_DIV_4,
mbed_official	579:53297373a894	370	/** Divide Main clock by eight. */
mbed_official	579:53297373a894	371	SYSTEM_MAIN_CLOCK_DIV_8,
mbed_official	579:53297373a894	372	/** Divide Main clock by 16. */
mbed_official	579:53297373a894	373	SYSTEM_MAIN_CLOCK_DIV_16,
mbed_official	579:53297373a894	374	/** Divide Main clock by 32. */
mbed_official	579:53297373a894	375	SYSTEM_MAIN_CLOCK_DIV_32,
mbed_official	579:53297373a894	376	/** Divide Main clock by 64. */
mbed_official	579:53297373a894	377	SYSTEM_MAIN_CLOCK_DIV_64,
mbed_official	579:53297373a894	378	/** Divide Main clock by 128. */
mbed_official	579:53297373a894	379	SYSTEM_MAIN_CLOCK_DIV_128,
mbed_official	579:53297373a894	380	};
mbed_official	579:53297373a894	381
mbed_official	579:53297373a894	382	/**
mbed_official	579:53297373a894	383	* \brief External clock source types.
mbed_official	579:53297373a894	384	*
mbed_official	579:53297373a894	385	* Available external clock source types.
mbed_official	579:53297373a894	386	*/
mbed_official	579:53297373a894	387	enum system_clock_external {
mbed_official	579:53297373a894	388	/** The external clock source is a crystal oscillator. */
mbed_official	579:53297373a894	389	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
mbed_official	579:53297373a894	390	/** The connected clock source is an external logic level clock signal. */
mbed_official	579:53297373a894	391	SYSTEM_CLOCK_EXTERNAL_CLOCK,
mbed_official	579:53297373a894	392	};
mbed_official	579:53297373a894	393
mbed_official	579:53297373a894	394	/**
mbed_official	579:53297373a894	395	* \brief Operating modes of the DFLL clock source.
mbed_official	579:53297373a894	396	*
mbed_official	579:53297373a894	397	* Available operating modes of the DFLL clock source module.
mbed_official	579:53297373a894	398	*/
mbed_official	579:53297373a894	399	enum system_clock_dfll_loop_mode {
mbed_official	579:53297373a894	400	/** The DFLL is operating in open loop mode with no feedback. */
mbed_official	579:53297373a894	401	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
mbed_official	579:53297373a894	402	/** The DFLL is operating in closed loop mode with frequency feedback from
mbed_official	579:53297373a894	403	* a low frequency reference clock.
mbed_official	579:53297373a894	404	*/
mbed_official	579:53297373a894	405	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
mbed_official	579:53297373a894	406
mbed_official	579:53297373a894	407	#ifdef SYSCTRL_DFLLCTRL_USBCRM
mbed_official	579:53297373a894	408	/** The DFLL is operating in USB recovery mode with frequency feedback
mbed_official	579:53297373a894	409	* from USB SOF.
mbed_official	579:53297373a894	410	*/
mbed_official	579:53297373a894	411	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
mbed_official	579:53297373a894	412	#endif
mbed_official	579:53297373a894	413	};
mbed_official	579:53297373a894	414
mbed_official	579:53297373a894	415	/**
mbed_official	579:53297373a894	416	* \brief Locking behavior for the DFLL during device wake-up.
mbed_official	579:53297373a894	417	*
mbed_official	579:53297373a894	418	* DFLL lock behavior modes on device wake-up from sleep.
mbed_official	579:53297373a894	419	*/
mbed_official	579:53297373a894	420	enum system_clock_dfll_wakeup_lock {
mbed_official	579:53297373a894	421	/** Keep DFLL lock when the device wakes from sleep. */
mbed_official	579:53297373a894	422	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
mbed_official	579:53297373a894	423	/** Lose DFLL lock when the devices wakes from sleep. */
mbed_official	579:53297373a894	424	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
mbed_official	579:53297373a894	425	};
mbed_official	579:53297373a894	426
mbed_official	579:53297373a894	427	/**
mbed_official	579:53297373a894	428	* \brief Fine tracking behavior for the DFLL once a lock has been acquired.
mbed_official	579:53297373a894	429	*
mbed_official	579:53297373a894	430	* DFLL fine tracking behavior modes after a lock has been acquired.
mbed_official	579:53297373a894	431	*/
mbed_official	579:53297373a894	432	enum system_clock_dfll_stable_tracking {
mbed_official	579:53297373a894	433	/** Keep tracking after the DFLL has gotten a fine lock. */
mbed_official	579:53297373a894	434	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
mbed_official	579:53297373a894	435	/** Stop tracking after the DFLL has gotten a fine lock. */
mbed_official	579:53297373a894	436	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
mbed_official	579:53297373a894	437	};
mbed_official	579:53297373a894	438
mbed_official	579:53297373a894	439	/**
mbed_official	579:53297373a894	440	* \brief Chill-cycle behavior of the DFLL module.
mbed_official	579:53297373a894	441	*
mbed_official	579:53297373a894	442	* DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period
mbed_official	579:53297373a894	443	* of time when the DFLL output frequency is not measured by the unit, to allow
mbed_official	579:53297373a894	444	* the output to stabilize after a change in the input clock source.
mbed_official	579:53297373a894	445	*/
mbed_official	579:53297373a894	446	enum system_clock_dfll_chill_cycle {
mbed_official	579:53297373a894	447	/** Enable a chill cycle, where the DFLL output frequency is not measured. */
mbed_official	579:53297373a894	448	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
mbed_official	579:53297373a894	449	/** Disable a chill cycle, where the DFLL output frequency is not measured. */
mbed_official	579:53297373a894	450	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
mbed_official	579:53297373a894	451	};
mbed_official	579:53297373a894	452
mbed_official	579:53297373a894	453	/**
mbed_official	579:53297373a894	454	* \brief QuickLock settings for the DFLL module.
mbed_official	579:53297373a894	455	*
mbed_official	579:53297373a894	456	* DFLL QuickLock settings for the DFLL module, to allow for a faster lock of
mbed_official	579:53297373a894	457	* the DFLL output frequency at the expense of accuracy.
mbed_official	579:53297373a894	458	*/
mbed_official	579:53297373a894	459	enum system_clock_dfll_quick_lock {
mbed_official	579:53297373a894	460	/** Enable the QuickLock feature for looser lock requirements on the DFLL. */
mbed_official	579:53297373a894	461	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
mbed_official	579:53297373a894	462	/** Disable the QuickLock feature for strict lock requirements on the DFLL. */
mbed_official	579:53297373a894	463	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
mbed_official	579:53297373a894	464	};
mbed_official	579:53297373a894	465
mbed_official	579:53297373a894	466	/**
mbed_official	579:53297373a894	467	* \brief Available clock sources in the system.
mbed_official	579:53297373a894	468	*
mbed_official	579:53297373a894	469	* Clock sources available to the GCLK generators.
mbed_official	579:53297373a894	470	*/
mbed_official	579:53297373a894	471	enum system_clock_source {
mbed_official	579:53297373a894	472	/** Internal 8MHz RC oscillator. */
mbed_official	579:53297373a894	473	SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M,
mbed_official	579:53297373a894	474	/** Internal 32KHz RC oscillator. */
mbed_official	579:53297373a894	475	SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K,
mbed_official	579:53297373a894	476	/** External oscillator. */
mbed_official	579:53297373a894	477	SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC ,
mbed_official	579:53297373a894	478	/** External 32KHz oscillator. */
mbed_official	579:53297373a894	479	SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K,
mbed_official	579:53297373a894	480	/** Digital Frequency Locked Loop (DFLL). */
mbed_official	579:53297373a894	481	SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M,
mbed_official	579:53297373a894	482	/** Internal Ultra Low Power 32KHz oscillator. */
mbed_official	579:53297373a894	483	SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K,
mbed_official	579:53297373a894	484	/** Generator input pad */
mbed_official	579:53297373a894	485	SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN,
mbed_official	579:53297373a894	486	/** Generic clock generator one output */
mbed_official	579:53297373a894	487	SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1,
mbed_official	579:53297373a894	488	#ifdef FEATURE_SYSTEM_CLOCK_DPLL
mbed_official	579:53297373a894	489	/** Digital Phase Locked Loop (DPLL).
mbed_official	579:53297373a894	490	* Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
mbed_official	579:53297373a894	491	*/
mbed_official	579:53297373a894	492	SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
mbed_official	579:53297373a894	493	#endif
mbed_official	579:53297373a894	494	};
mbed_official	579:53297373a894	495
mbed_official	579:53297373a894	496	/**
mbed_official	579:53297373a894	497	* \brief List of APB peripheral buses.
mbed_official	579:53297373a894	498	*
mbed_official	579:53297373a894	499	* Available bus clock domains on the APB bus.
mbed_official	579:53297373a894	500	*/
mbed_official	579:53297373a894	501	enum system_clock_apb_bus {
mbed_official	579:53297373a894	502	/** Peripheral bus A on the APB bus. */
mbed_official	579:53297373a894	503	SYSTEM_CLOCK_APB_APBA,
mbed_official	579:53297373a894	504	/** Peripheral bus B on the APB bus. */
mbed_official	579:53297373a894	505	SYSTEM_CLOCK_APB_APBB,
mbed_official	579:53297373a894	506	/** Peripheral bus C on the APB bus. */
mbed_official	579:53297373a894	507	SYSTEM_CLOCK_APB_APBC,
mbed_official	579:53297373a894	508	};
mbed_official	579:53297373a894	509
mbed_official	579:53297373a894	510	/**
mbed_official	579:53297373a894	511	* \brief Configuration structure for XOSC.
mbed_official	579:53297373a894	512	*
mbed_official	579:53297373a894	513	* External oscillator clock configuration structure.
mbed_official	579:53297373a894	514	*/
mbed_official	579:53297373a894	515	struct system_clock_source_xosc_config {
mbed_official	579:53297373a894	516	/** External clock type. */
mbed_official	579:53297373a894	517	enum system_clock_external external_clock;
mbed_official	579:53297373a894	518	/** Crystal oscillator start-up time. */
mbed_official	579:53297373a894	519	enum system_xosc_startup startup_time;
mbed_official	579:53297373a894	520	/** Enable automatic amplitude gain control. */
mbed_official	579:53297373a894	521	bool auto_gain_control;
mbed_official	579:53297373a894	522	/** External clock/crystal frequency. */
mbed_official	579:53297373a894	523	uint32_t frequency;
mbed_official	579:53297373a894	524	/** Keep the XOSC enabled in standby sleep mode. */
mbed_official	579:53297373a894	525	bool run_in_standby;
mbed_official	579:53297373a894	526	/** Run On Demand. If this is set the XOSC won't run
mbed_official	579:53297373a894	527	* until requested by a peripheral. */
mbed_official	579:53297373a894	528	bool on_demand;
mbed_official	579:53297373a894	529	};
mbed_official	579:53297373a894	530
mbed_official	579:53297373a894	531	/**
mbed_official	579:53297373a894	532	* \brief Configuration structure for XOSC32K.
mbed_official	579:53297373a894	533	*
mbed_official	579:53297373a894	534	* External 32KHz oscillator clock configuration structure.
mbed_official	579:53297373a894	535	*/
mbed_official	579:53297373a894	536	struct system_clock_source_xosc32k_config {
mbed_official	579:53297373a894	537	/** External clock type. */
mbed_official	579:53297373a894	538	enum system_clock_external external_clock;
mbed_official	579:53297373a894	539	/** Crystal oscillator start-up time. */
mbed_official	579:53297373a894	540	enum system_xosc32k_startup startup_time;
mbed_official	579:53297373a894	541	/** Enable automatic amplitude control. */
mbed_official	579:53297373a894	542	bool auto_gain_control;
mbed_official	579:53297373a894	543	/** Enable 1KHz output. */
mbed_official	579:53297373a894	544	bool enable_1khz_output;
mbed_official	579:53297373a894	545	/** Enable 32KHz output. */
mbed_official	579:53297373a894	546	bool enable_32khz_output;
mbed_official	579:53297373a894	547	/** External clock/crystal frequency. */
mbed_official	579:53297373a894	548	uint32_t frequency;
mbed_official	579:53297373a894	549	/** Keep the XOSC32K enabled in standby sleep mode. */
mbed_official	579:53297373a894	550	bool run_in_standby;
mbed_official	579:53297373a894	551	/** Run On Demand. If this is set the XOSC32K won't run
mbed_official	579:53297373a894	552	* until requested by a peripheral. */
mbed_official	579:53297373a894	553	bool on_demand;
mbed_official	579:53297373a894	554	/** Lock configuration after it has been written,
mbed_official	579:53297373a894	555	* a device reset will release the lock. */
mbed_official	579:53297373a894	556	bool write_once;
mbed_official	579:53297373a894	557	};
mbed_official	579:53297373a894	558
mbed_official	579:53297373a894	559	/**
mbed_official	579:53297373a894	560	* \brief Configuration structure for OSC8M.
mbed_official	579:53297373a894	561	*
mbed_official	579:53297373a894	562	* Internal 8MHz (nominal) oscillator configuration structure.
mbed_official	579:53297373a894	563	*/
mbed_official	579:53297373a894	564	struct system_clock_source_osc8m_config {
mbed_official	579:53297373a894	565	/* Internal 8MHz RC oscillator prescaler. */
mbed_official	579:53297373a894	566	enum system_osc8m_div prescaler;
mbed_official	579:53297373a894	567	/** Keep the OSC8M enabled in standby sleep mode. */
mbed_official	579:53297373a894	568	bool run_in_standby;
mbed_official	579:53297373a894	569	/** Run On Demand. If this is set the OSC8M won't run
mbed_official	579:53297373a894	570	* until requested by a peripheral. */
mbed_official	579:53297373a894	571	bool on_demand;
mbed_official	579:53297373a894	572	};
mbed_official	579:53297373a894	573
mbed_official	579:53297373a894	574	/**
mbed_official	579:53297373a894	575	* \brief Configuration structure for OSC32K.
mbed_official	579:53297373a894	576	*
mbed_official	579:53297373a894	577	* Internal 32KHz (nominal) oscillator configuration structure.
mbed_official	579:53297373a894	578	*/
mbed_official	579:53297373a894	579	struct system_clock_source_osc32k_config {
mbed_official	579:53297373a894	580	/** Startup time. */
mbed_official	579:53297373a894	581	enum system_osc32k_startup startup_time;
mbed_official	579:53297373a894	582	/** Enable 1KHz output. */
mbed_official	579:53297373a894	583	bool enable_1khz_output;
mbed_official	579:53297373a894	584	/** Enable 32KHz output. */
mbed_official	579:53297373a894	585	bool enable_32khz_output;
mbed_official	579:53297373a894	586	/** Keep the OSC32K enabled in standby sleep mode. */
mbed_official	579:53297373a894	587	bool run_in_standby;
mbed_official	579:53297373a894	588	/** Run On Demand. If this is set the OSC32K won't run
mbed_official	579:53297373a894	589	* until requested by a peripheral. */
mbed_official	579:53297373a894	590	bool on_demand;
mbed_official	579:53297373a894	591	/** Lock configuration after it has been written,
mbed_official	579:53297373a894	592	* a device reset will release the lock. */
mbed_official	579:53297373a894	593	bool write_once;
mbed_official	579:53297373a894	594	};
mbed_official	579:53297373a894	595
mbed_official	579:53297373a894	596	/**
mbed_official	579:53297373a894	597	* \brief Configuration structure for DFLL.
mbed_official	579:53297373a894	598	*
mbed_official	579:53297373a894	599	* DFLL oscillator configuration structure.
mbed_official	579:53297373a894	600	*/
mbed_official	579:53297373a894	601	struct system_clock_source_dfll_config {
mbed_official	579:53297373a894	602	/** Loop mode. */
mbed_official	579:53297373a894	603	enum system_clock_dfll_loop_mode loop_mode;
mbed_official	579:53297373a894	604	/** Run On Demand. If this is set the DFLL won't run
mbed_official	579:53297373a894	605	* until requested by a peripheral. */
mbed_official	579:53297373a894	606	bool on_demand;
mbed_official	579:53297373a894	607	/** Enable Quick Lock. */
mbed_official	579:53297373a894	608	enum system_clock_dfll_quick_lock quick_lock;
mbed_official	579:53297373a894	609	/** Enable Chill Cycle. */
mbed_official	579:53297373a894	610	enum system_clock_dfll_chill_cycle chill_cycle;
mbed_official	579:53297373a894	611	/** DFLL lock state on wakeup. */
mbed_official	579:53297373a894	612	enum system_clock_dfll_wakeup_lock wakeup_lock;
mbed_official	579:53297373a894	613	/** DFLL tracking after fine lock. */
mbed_official	579:53297373a894	614	enum system_clock_dfll_stable_tracking stable_tracking;
mbed_official	579:53297373a894	615	/** Coarse calibration value (Open loop mode). */
mbed_official	579:53297373a894	616	uint8_t coarse_value;
mbed_official	579:53297373a894	617	/** Fine calibration value (Open loop mode). */
mbed_official	579:53297373a894	618	uint16_t fine_value;
mbed_official	579:53297373a894	619	/** Coarse adjustment maximum step size (Closed loop mode). */
mbed_official	579:53297373a894	620	uint8_t coarse_max_step;
mbed_official	579:53297373a894	621	/** Fine adjustment maximum step size (Closed loop mode). */
mbed_official	579:53297373a894	622	uint16_t fine_max_step;
mbed_official	579:53297373a894	623	/** DFLL multiply factor (Closed loop mode. */
mbed_official	579:53297373a894	624	uint16_t multiply_factor;
mbed_official	579:53297373a894	625	};
mbed_official	579:53297373a894	626
mbed_official	579:53297373a894	627	/**
mbed_official	579:53297373a894	628	* \name External Oscillator Management
mbed_official	579:53297373a894	629	* @{
mbed_official	579:53297373a894	630	*/
mbed_official	579:53297373a894	631
mbed_official	579:53297373a894	632	/**
mbed_official	579:53297373a894	633	* \brief Retrieve the default configuration for XOSC.
mbed_official	579:53297373a894	634	*
mbed_official	579:53297373a894	635	* Fills a configuration structure with the default configuration for an
mbed_official	579:53297373a894	636	* external oscillator module:
mbed_official	579:53297373a894	637	* - External Crystal
mbed_official	579:53297373a894	638	* - Start-up time of 16384 external clock cycles
mbed_official	579:53297373a894	639	* - Automatic crystal gain control mode enabled
mbed_official	579:53297373a894	640	* - Frequency of 12MHz
mbed_official	579:53297373a894	641	* - Don't run in STANDBY sleep mode
mbed_official	579:53297373a894	642	* - Run only when requested by peripheral (on demand)
mbed_official	579:53297373a894	643	*
mbed_official	579:53297373a894	644	* \param[out] config Configuration structure to fill with default values
mbed_official	579:53297373a894	645	*/
mbed_official	579:53297373a894	646	static inline void system_clock_source_xosc_get_config_defaults(
mbed_official	579:53297373a894	647	struct system_clock_source_xosc_config *const config)
mbed_official	579:53297373a894	648	{
mbed_official	579:53297373a894	649	Assert(config);
mbed_official	579:53297373a894	650
mbed_official	579:53297373a894	651	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
mbed_official	579:53297373a894	652	config->startup_time = SYSTEM_XOSC_STARTUP_16384;
mbed_official	579:53297373a894	653	config->auto_gain_control = true;
mbed_official	579:53297373a894	654	config->frequency = 12000000UL;
mbed_official	579:53297373a894	655	config->run_in_standby = false;
mbed_official	579:53297373a894	656	config->on_demand = true;
mbed_official	579:53297373a894	657	}
mbed_official	579:53297373a894	658
mbed_official	579:53297373a894	659	void system_clock_source_xosc_set_config(
mbed_official	579:53297373a894	660	struct system_clock_source_xosc_config *const config);
mbed_official	579:53297373a894	661
mbed_official	579:53297373a894	662	/**
mbed_official	579:53297373a894	663	* @}
mbed_official	579:53297373a894	664	*/
mbed_official	579:53297373a894	665
mbed_official	579:53297373a894	666
mbed_official	579:53297373a894	667	/**
mbed_official	579:53297373a894	668	* \name External 32KHz Oscillator Management
mbed_official	579:53297373a894	669	* @{
mbed_official	579:53297373a894	670	*/
mbed_official	579:53297373a894	671
mbed_official	579:53297373a894	672	/**
mbed_official	579:53297373a894	673	* \brief Retrieve the default configuration for XOSC32K.
mbed_official	579:53297373a894	674	*
mbed_official	579:53297373a894	675	* Fills a configuration structure with the default configuration for an
mbed_official	579:53297373a894	676	* external 32KHz oscillator module:
mbed_official	579:53297373a894	677	* - External Crystal
mbed_official	579:53297373a894	678	* - Start-up time of 16384 external clock cycles
mbed_official	579:53297373a894	679	* - Automatic crystal gain control mode disabled
mbed_official	579:53297373a894	680	* - Frequency of 32.768KHz
mbed_official	579:53297373a894	681	* - 1KHz clock output disabled
mbed_official	579:53297373a894	682	* - 32KHz clock output enabled
mbed_official	579:53297373a894	683	* - Don't run in STANDBY sleep mode
mbed_official	579:53297373a894	684	* - Run only when requested by peripheral (on demand)
mbed_official	579:53297373a894	685	* - Don't lock registers after configuration has been written
mbed_official	579:53297373a894	686	*
mbed_official	579:53297373a894	687	* \param[out] config Configuration structure to fill with default values
mbed_official	579:53297373a894	688	*/
mbed_official	579:53297373a894	689	static inline void system_clock_source_xosc32k_get_config_defaults(
mbed_official	579:53297373a894	690	struct system_clock_source_xosc32k_config *const config)
mbed_official	579:53297373a894	691	{
mbed_official	579:53297373a894	692	Assert(config);
mbed_official	579:53297373a894	693
mbed_official	579:53297373a894	694	config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
mbed_official	579:53297373a894	695	config->startup_time = SYSTEM_XOSC32K_STARTUP_16384;
mbed_official	579:53297373a894	696	config->auto_gain_control = false;
mbed_official	579:53297373a894	697	config->frequency = 32768UL;
mbed_official	579:53297373a894	698	config->enable_1khz_output = false;
mbed_official	579:53297373a894	699	config->enable_32khz_output = true;
mbed_official	579:53297373a894	700	config->run_in_standby = false;
mbed_official	579:53297373a894	701	config->on_demand = true;
mbed_official	579:53297373a894	702	config->write_once = false;
mbed_official	579:53297373a894	703	}
mbed_official	579:53297373a894	704
mbed_official	579:53297373a894	705	void system_clock_source_xosc32k_set_config(
mbed_official	579:53297373a894	706	struct system_clock_source_xosc32k_config *const config);
mbed_official	579:53297373a894	707	/**
mbed_official	579:53297373a894	708	* @}
mbed_official	579:53297373a894	709	*/
mbed_official	579:53297373a894	710
mbed_official	579:53297373a894	711
mbed_official	579:53297373a894	712	/**
mbed_official	579:53297373a894	713	* \name Internal 32KHz Oscillator Management
mbed_official	579:53297373a894	714	* @{
mbed_official	579:53297373a894	715	*/
mbed_official	579:53297373a894	716
mbed_official	579:53297373a894	717	/**
mbed_official	579:53297373a894	718	* \brief Retrieve the default configuration for OSC32K.
mbed_official	579:53297373a894	719	*
mbed_official	579:53297373a894	720	* Fills a configuration structure with the default configuration for an
mbed_official	579:53297373a894	721	* internal 32KHz oscillator module:
mbed_official	579:53297373a894	722	* - 1KHz clock output enabled
mbed_official	579:53297373a894	723	* - 32KHz clock output enabled
mbed_official	579:53297373a894	724	* - Don't run in STANDBY sleep mode
mbed_official	579:53297373a894	725	* - Run only when requested by peripheral (on demand)
mbed_official	579:53297373a894	726	* - Set startup time to 130 cycles
mbed_official	579:53297373a894	727	* - Don't lock registers after configuration has been written
mbed_official	579:53297373a894	728	*
mbed_official	579:53297373a894	729	* \param[out] config Configuration structure to fill with default values
mbed_official	579:53297373a894	730	*/
mbed_official	579:53297373a894	731	static inline void system_clock_source_osc32k_get_config_defaults(
mbed_official	579:53297373a894	732	struct system_clock_source_osc32k_config *const config)
mbed_official	579:53297373a894	733	{
mbed_official	579:53297373a894	734	Assert(config);
mbed_official	579:53297373a894	735
mbed_official	579:53297373a894	736	config->enable_1khz_output = true;
mbed_official	579:53297373a894	737	config->enable_32khz_output = true;
mbed_official	579:53297373a894	738	config->run_in_standby = false;
mbed_official	579:53297373a894	739	config->on_demand = true;
mbed_official	579:53297373a894	740	config->startup_time = SYSTEM_OSC32K_STARTUP_130;
mbed_official	579:53297373a894	741	config->write_once = false;
mbed_official	579:53297373a894	742	}
mbed_official	579:53297373a894	743
mbed_official	579:53297373a894	744	void system_clock_source_osc32k_set_config(
mbed_official	579:53297373a894	745	struct system_clock_source_osc32k_config *const config);
mbed_official	579:53297373a894	746
mbed_official	579:53297373a894	747	/**
mbed_official	579:53297373a894	748	* @}
mbed_official	579:53297373a894	749	*/
mbed_official	579:53297373a894	750
mbed_official	579:53297373a894	751
mbed_official	579:53297373a894	752	/**
mbed_official	579:53297373a894	753	* \name Internal 8MHz Oscillator Management
mbed_official	579:53297373a894	754	* @{
mbed_official	579:53297373a894	755	*/
mbed_official	579:53297373a894	756
mbed_official	579:53297373a894	757	/**
mbed_official	579:53297373a894	758	* \brief Retrieve the default configuration for OSC8M.
mbed_official	579:53297373a894	759	*
mbed_official	579:53297373a894	760	* Fills a configuration structure with the default configuration for an
mbed_official	579:53297373a894	761	* internal 8MHz (nominal) oscillator module:
mbed_official	579:53297373a894	762	* - Clock output frequency divided by a factor of eight
mbed_official	579:53297373a894	763	* - Don't run in STANDBY sleep mode
mbed_official	579:53297373a894	764	* - Run only when requested by peripheral (on demand)
mbed_official	579:53297373a894	765	*
mbed_official	579:53297373a894	766	* \param[out] config Configuration structure to fill with default values
mbed_official	579:53297373a894	767	*/
mbed_official	579:53297373a894	768	static inline void system_clock_source_osc8m_get_config_defaults(
mbed_official	579:53297373a894	769	struct system_clock_source_osc8m_config *const config)
mbed_official	579:53297373a894	770	{
mbed_official	579:53297373a894	771	Assert(config);
mbed_official	579:53297373a894	772
mbed_official	579:53297373a894	773	config->prescaler = SYSTEM_OSC8M_DIV_8;
mbed_official	579:53297373a894	774	config->run_in_standby = false;
mbed_official	579:53297373a894	775	config->on_demand = true;
mbed_official	579:53297373a894	776	}
mbed_official	579:53297373a894	777
mbed_official	579:53297373a894	778	void system_clock_source_osc8m_set_config(
mbed_official	579:53297373a894	779	struct system_clock_source_osc8m_config *const config);
mbed_official	579:53297373a894	780
mbed_official	579:53297373a894	781	/**
mbed_official	579:53297373a894	782	* @}
mbed_official	579:53297373a894	783	*/
mbed_official	579:53297373a894	784
mbed_official	579:53297373a894	785
mbed_official	579:53297373a894	786	/**
mbed_official	579:53297373a894	787	* \name Internal DFLL Management
mbed_official	579:53297373a894	788	* @{
mbed_official	579:53297373a894	789	*/
mbed_official	579:53297373a894	790
mbed_official	579:53297373a894	791	/**
mbed_official	579:53297373a894	792	* \brief Retrieve the default configuration for DFLL.
mbed_official	579:53297373a894	793	*
mbed_official	579:53297373a894	794	* Fills a configuration structure with the default configuration for a
mbed_official	579:53297373a894	795	* DFLL oscillator module:
mbed_official	579:53297373a894	796	* - Open loop mode
mbed_official	579:53297373a894	797	* - QuickLock mode enabled
mbed_official	579:53297373a894	798	* - Chill cycle enabled
mbed_official	579:53297373a894	799	* - Output frequency lock maintained during device wake-up
mbed_official	579:53297373a894	800	* - Continuous tracking of the output frequency
mbed_official	579:53297373a894	801	* - Default tracking values at the mid-points for both coarse and fine
mbed_official	579:53297373a894	802	* tracking parameters
mbed_official	579:53297373a894	803	* - Don't run in STANDBY sleep mode
mbed_official	579:53297373a894	804	* - Run only when requested by peripheral (on demand)
mbed_official	579:53297373a894	805	*
mbed_official	579:53297373a894	806	* \param[out] config Configuration structure to fill with default values
mbed_official	579:53297373a894	807	*/
mbed_official	579:53297373a894	808	static inline void system_clock_source_dfll_get_config_defaults(
mbed_official	579:53297373a894	809	struct system_clock_source_dfll_config *const config)
mbed_official	579:53297373a894	810	{
mbed_official	579:53297373a894	811	Assert(config);
mbed_official	579:53297373a894	812
mbed_official	579:53297373a894	813	config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
mbed_official	579:53297373a894	814	config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
mbed_official	579:53297373a894	815	config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
mbed_official	579:53297373a894	816	config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
mbed_official	579:53297373a894	817	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
mbed_official	579:53297373a894	818	config->on_demand = true;
mbed_official	579:53297373a894	819
mbed_official	579:53297373a894	820	/* Open loop mode calibration value */
mbed_official	579:53297373a894	821	config->coarse_value = 0x1f / 4; /* Midpoint */
mbed_official	579:53297373a894	822	config->fine_value = 0xff / 4; /* Midpoint */
mbed_official	579:53297373a894	823
mbed_official	579:53297373a894	824	/* Closed loop mode */
mbed_official	579:53297373a894	825	config->coarse_max_step = 1;
mbed_official	579:53297373a894	826	config->fine_max_step = 1;
mbed_official	579:53297373a894	827	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
mbed_official	579:53297373a894	828	}
mbed_official	579:53297373a894	829
mbed_official	579:53297373a894	830	void system_clock_source_dfll_set_config(
mbed_official	579:53297373a894	831	struct system_clock_source_dfll_config *const config);
mbed_official	579:53297373a894	832
mbed_official	579:53297373a894	833	/**
mbed_official	579:53297373a894	834	* @}
mbed_official	579:53297373a894	835	*/
mbed_official	579:53297373a894	836
mbed_official	579:53297373a894	837	/**
mbed_official	579:53297373a894	838	* \name Clock Source Management
mbed_official	579:53297373a894	839	* @{
mbed_official	579:53297373a894	840	*/
mbed_official	579:53297373a894	841	enum status_code system_clock_source_write_calibration(
mbed_official	579:53297373a894	842	const enum system_clock_source system_clock_source,
mbed_official	579:53297373a894	843	const uint16_t calibration_value,
mbed_official	579:53297373a894	844	const uint8_t freq_range);
mbed_official	579:53297373a894	845
mbed_official	579:53297373a894	846	enum status_code system_clock_source_enable(
mbed_official	579:53297373a894	847	const enum system_clock_source system_clock_source);
mbed_official	579:53297373a894	848
mbed_official	579:53297373a894	849	enum status_code system_clock_source_disable(
mbed_official	579:53297373a894	850	const enum system_clock_source clk_source);
mbed_official	579:53297373a894	851
mbed_official	579:53297373a894	852	bool system_clock_source_is_ready(
mbed_official	579:53297373a894	853	const enum system_clock_source clk_source);
mbed_official	579:53297373a894	854
mbed_official	579:53297373a894	855	uint32_t system_clock_source_get_hz(
mbed_official	579:53297373a894	856	const enum system_clock_source clk_source);
mbed_official	579:53297373a894	857
mbed_official	579:53297373a894	858	/**
mbed_official	579:53297373a894	859	* @}
mbed_official	579:53297373a894	860	*/
mbed_official	579:53297373a894	861
mbed_official	579:53297373a894	862	/**
mbed_official	579:53297373a894	863	* \name Main Clock Management
mbed_official	579:53297373a894	864	* @{
mbed_official	579:53297373a894	865	*/
mbed_official	579:53297373a894	866
mbed_official	579:53297373a894	867	/**
mbed_official	579:53297373a894	868	* \brief Set main CPU clock divider.
mbed_official	579:53297373a894	869	*
mbed_official	579:53297373a894	870	* Sets the clock divider used on the main clock to provide the CPU clock.
mbed_official	579:53297373a894	871	*
mbed_official	579:53297373a894	872	* \param[in] divider CPU clock divider to set
mbed_official	579:53297373a894	873	*/
mbed_official	579:53297373a894	874	static inline void system_cpu_clock_set_divider(
mbed_official	579:53297373a894	875	const enum system_main_clock_div divider)
mbed_official	579:53297373a894	876	{
mbed_official	579:53297373a894	877	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
mbed_official	579:53297373a894	878	PM->CPUSEL.reg = (uint32_t)divider;
mbed_official	579:53297373a894	879	}
mbed_official	579:53297373a894	880
mbed_official	579:53297373a894	881	/**
mbed_official	579:53297373a894	882	* \brief Retrieves the current frequency of the CPU core.
mbed_official	579:53297373a894	883	*
mbed_official	579:53297373a894	884	* Retrieves the operating frequency of the CPU core, obtained from the main
mbed_official	579:53297373a894	885	* generic clock and the set CPU bus divider.
mbed_official	579:53297373a894	886	*
mbed_official	579:53297373a894	887	* \return Current CPU frequency in Hz.
mbed_official	579:53297373a894	888	*/
mbed_official	579:53297373a894	889	static inline uint32_t system_cpu_clock_get_hz(void)
mbed_official	579:53297373a894	890	{
mbed_official	579:53297373a894	891	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
mbed_official	579:53297373a894	892	}
mbed_official	579:53297373a894	893
mbed_official	579:53297373a894	894	/**
mbed_official	579:53297373a894	895	* \brief Set APBx clock divider.
mbed_official	579:53297373a894	896	*
mbed_official	579:53297373a894	897	* Set the clock divider used on the main clock to provide the clock for the
mbed_official	579:53297373a894	898	* given APBx bus.
mbed_official	579:53297373a894	899	*
mbed_official	579:53297373a894	900	* \param[in] divider APBx bus divider to set
mbed_official	579:53297373a894	901	* \param[in] bus APBx bus to set divider
mbed_official	579:53297373a894	902	*
mbed_official	579:53297373a894	903	* \returns Status of the clock division change operation.
mbed_official	579:53297373a894	904	*
mbed_official	579:53297373a894	905	* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
mbed_official	579:53297373a894	906	* \retval STATUS_OK The APBx clock was set successfully
mbed_official	579:53297373a894	907	*/
mbed_official	579:53297373a894	908	static inline enum status_code system_apb_clock_set_divider(
mbed_official	579:53297373a894	909	const enum system_clock_apb_bus bus,
mbed_official	579:53297373a894	910	const enum system_main_clock_div divider)
mbed_official	579:53297373a894	911	{
mbed_official	579:53297373a894	912	switch (bus) {
mbed_official	579:53297373a894	913	case SYSTEM_CLOCK_APB_APBA:
mbed_official	579:53297373a894	914	PM->APBASEL.reg = (uint32_t)divider;
mbed_official	579:53297373a894	915	break;
mbed_official	579:53297373a894	916	case SYSTEM_CLOCK_APB_APBB:
mbed_official	579:53297373a894	917	PM->APBBSEL.reg = (uint32_t)divider;
mbed_official	579:53297373a894	918	break;
mbed_official	579:53297373a894	919	case SYSTEM_CLOCK_APB_APBC:
mbed_official	579:53297373a894	920	PM->APBCSEL.reg = (uint32_t)divider;
mbed_official	579:53297373a894	921	break;
mbed_official	579:53297373a894	922	default:
mbed_official	579:53297373a894	923	Assert(false);
mbed_official	579:53297373a894	924	return STATUS_ERR_INVALID_ARG;
mbed_official	579:53297373a894	925	}
mbed_official	579:53297373a894	926
mbed_official	579:53297373a894	927	return STATUS_OK;
mbed_official	579:53297373a894	928	}
mbed_official	579:53297373a894	929
mbed_official	579:53297373a894	930	/**
mbed_official	579:53297373a894	931	* \brief Retrieves the current frequency of a ABPx.
mbed_official	579:53297373a894	932	*
mbed_official	579:53297373a894	933	* Retrieves the operating frequency of an APBx bus, obtained from the main
mbed_official	579:53297373a894	934	* generic clock and the set APBx bus divider.
mbed_official	579:53297373a894	935	*
mbed_official	579:53297373a894	936	* \return Current APBx bus frequency in Hz.
mbed_official	579:53297373a894	937	*/
mbed_official	579:53297373a894	938	static inline uint32_t system_apb_clock_get_hz(
mbed_official	579:53297373a894	939	const enum system_clock_apb_bus bus)
mbed_official	579:53297373a894	940	{
mbed_official	579:53297373a894	941	uint16_t bus_divider = 0;
mbed_official	579:53297373a894	942
mbed_official	579:53297373a894	943	switch (bus) {
mbed_official	579:53297373a894	944	case SYSTEM_CLOCK_APB_APBA:
mbed_official	579:53297373a894	945	bus_divider = PM->APBASEL.reg;
mbed_official	579:53297373a894	946	break;
mbed_official	579:53297373a894	947	case SYSTEM_CLOCK_APB_APBB:
mbed_official	579:53297373a894	948	bus_divider = PM->APBBSEL.reg;
mbed_official	579:53297373a894	949	break;
mbed_official	579:53297373a894	950	case SYSTEM_CLOCK_APB_APBC:
mbed_official	579:53297373a894	951	bus_divider = PM->APBCSEL.reg;
mbed_official	579:53297373a894	952	break;
mbed_official	579:53297373a894	953	default:
mbed_official	579:53297373a894	954	Assert(false);
mbed_official	579:53297373a894	955	return 0;
mbed_official	579:53297373a894	956	}
mbed_official	579:53297373a894	957
mbed_official	579:53297373a894	958	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
mbed_official	579:53297373a894	959	}
mbed_official	579:53297373a894	960
mbed_official	579:53297373a894	961
mbed_official	579:53297373a894	962	/**
mbed_official	579:53297373a894	963	* @}
mbed_official	579:53297373a894	964	*/
mbed_official	579:53297373a894	965
mbed_official	579:53297373a894	966	/**
mbed_official	579:53297373a894	967	* \name Bus Clock Masking
mbed_official	579:53297373a894	968	* @{
mbed_official	579:53297373a894	969	*/
mbed_official	579:53297373a894	970
mbed_official	579:53297373a894	971	/**
mbed_official	579:53297373a894	972	* \brief Set bits in the clock mask for the AHB bus.
mbed_official	579:53297373a894	973	*
mbed_official	579:53297373a894	974	* This function will set bits in the clock mask for the AHB bus.
mbed_official	579:53297373a894	975	* Any bits set to 1 will enable that clock, 0 bits in the mask
mbed_official	579:53297373a894	976	* will be ignored.
mbed_official	579:53297373a894	977	*
mbed_official	579:53297373a894	978	* \param[in] ahb_mask AHB clock mask to enable
mbed_official	579:53297373a894	979	*/
mbed_official	579:53297373a894	980	static inline void system_ahb_clock_set_mask(
mbed_official	579:53297373a894	981	const uint32_t ahb_mask)
mbed_official	579:53297373a894	982	{
mbed_official	579:53297373a894	983	PM->AHBMASK.reg \|= ahb_mask;
mbed_official	579:53297373a894	984	}
mbed_official	579:53297373a894	985
mbed_official	579:53297373a894	986	/**
mbed_official	579:53297373a894	987	* \brief Clear bits in the clock mask for the AHB bus.
mbed_official	579:53297373a894	988	*
mbed_official	579:53297373a894	989	* This function will clear bits in the clock mask for the AHB bus.
mbed_official	579:53297373a894	990	* Any bits set to 1 will disable that clock, 0 bits in the mask
mbed_official	579:53297373a894	991	* will be ignored.
mbed_official	579:53297373a894	992	*
mbed_official	579:53297373a894	993	* \param[in] ahb_mask AHB clock mask to disable
mbed_official	579:53297373a894	994	*/
mbed_official	579:53297373a894	995	static inline void system_ahb_clock_clear_mask(
mbed_official	579:53297373a894	996	const uint32_t ahb_mask)
mbed_official	579:53297373a894	997	{
mbed_official	579:53297373a894	998	PM->AHBMASK.reg &= ~ahb_mask;
mbed_official	579:53297373a894	999	}
mbed_official	579:53297373a894	1000
mbed_official	579:53297373a894	1001	/**
mbed_official	579:53297373a894	1002	* \brief Set bits in the clock mask for an APBx bus.
mbed_official	579:53297373a894	1003	*
mbed_official	579:53297373a894	1004	* This function will set bits in the clock mask for an APBx bus.
mbed_official	579:53297373a894	1005	* Any bits set to 1 will enable the corresponding module clock, zero bits in
mbed_official	579:53297373a894	1006	* the mask will be ignored.
mbed_official	579:53297373a894	1007	*
mbed_official	579:53297373a894	1008	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
mbed_official	579:53297373a894	1009	* the device header files
mbed_official	579:53297373a894	1010	* \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_*
mbed_official	579:53297373a894	1011	* constants from the device header files
mbed_official	579:53297373a894	1012	*
mbed_official	579:53297373a894	1013	* \returns Status indicating the result of the clock mask change operation.
mbed_official	579:53297373a894	1014	*
mbed_official	579:53297373a894	1015	* \retval STATUS_ERR_INVALID_ARG Invalid bus given
mbed_official	579:53297373a894	1016	* \retval STATUS_OK The clock mask was set successfully
mbed_official	579:53297373a894	1017	*/
mbed_official	579:53297373a894	1018	static inline enum status_code system_apb_clock_set_mask(
mbed_official	579:53297373a894	1019	const enum system_clock_apb_bus bus,
mbed_official	579:53297373a894	1020	const uint32_t mask)
mbed_official	579:53297373a894	1021	{
mbed_official	579:53297373a894	1022	switch (bus) {
mbed_official	579:53297373a894	1023	case SYSTEM_CLOCK_APB_APBA:
mbed_official	579:53297373a894	1024	PM->APBAMASK.reg \|= mask;
mbed_official	579:53297373a894	1025	break;
mbed_official	579:53297373a894	1026
mbed_official	579:53297373a894	1027	case SYSTEM_CLOCK_APB_APBB:
mbed_official	579:53297373a894	1028	PM->APBBMASK.reg \|= mask;
mbed_official	579:53297373a894	1029	break;
mbed_official	579:53297373a894	1030
mbed_official	579:53297373a894	1031	case SYSTEM_CLOCK_APB_APBC:
mbed_official	579:53297373a894	1032	PM->APBCMASK.reg \|= mask;
mbed_official	579:53297373a894	1033	break;
mbed_official	579:53297373a894	1034
mbed_official	579:53297373a894	1035	default:
mbed_official	579:53297373a894	1036	Assert(false);
mbed_official	579:53297373a894	1037	return STATUS_ERR_INVALID_ARG;
mbed_official	579:53297373a894	1038
mbed_official	579:53297373a894	1039	}
mbed_official	579:53297373a894	1040
mbed_official	579:53297373a894	1041	return STATUS_OK;
mbed_official	579:53297373a894	1042	}
mbed_official	579:53297373a894	1043
mbed_official	579:53297373a894	1044	/**
mbed_official	579:53297373a894	1045	* \brief Clear bits in the clock mask for an APBx bus.
mbed_official	579:53297373a894	1046	*
mbed_official	579:53297373a894	1047	* This function will clear bits in the clock mask for an APBx bus.
mbed_official	579:53297373a894	1048	* Any bits set to 1 will disable the corresponding module clock, zero bits in
mbed_official	579:53297373a894	1049	* the mask will be ignored.
mbed_official	579:53297373a894	1050	*
mbed_official	579:53297373a894	1051	* \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from
mbed_official	579:53297373a894	1052	* the device header files
mbed_official	579:53297373a894	1053	* \param[in] bus Bus to clear clock mask bits
mbed_official	579:53297373a894	1054	*
mbed_official	579:53297373a894	1055	* \returns Status indicating the result of the clock mask change operation.
mbed_official	579:53297373a894	1056	*
mbed_official	579:53297373a894	1057	* \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given
mbed_official	579:53297373a894	1058	* \retval STATUS_OK The clock mask was changed successfully
mbed_official	579:53297373a894	1059	*/
mbed_official	579:53297373a894	1060	static inline enum status_code system_apb_clock_clear_mask(
mbed_official	579:53297373a894	1061	const enum system_clock_apb_bus bus,
mbed_official	579:53297373a894	1062	const uint32_t mask)
mbed_official	579:53297373a894	1063	{
mbed_official	579:53297373a894	1064	switch (bus) {
mbed_official	579:53297373a894	1065	case SYSTEM_CLOCK_APB_APBA:
mbed_official	579:53297373a894	1066	PM->APBAMASK.reg &= ~mask;
mbed_official	579:53297373a894	1067	break;
mbed_official	579:53297373a894	1068
mbed_official	579:53297373a894	1069	case SYSTEM_CLOCK_APB_APBB:
mbed_official	579:53297373a894	1070	PM->APBBMASK.reg &= ~mask;
mbed_official	579:53297373a894	1071	break;
mbed_official	579:53297373a894	1072
mbed_official	579:53297373a894	1073	case SYSTEM_CLOCK_APB_APBC:
mbed_official	579:53297373a894	1074	PM->APBCMASK.reg &= ~mask;
mbed_official	579:53297373a894	1075	break;
mbed_official	579:53297373a894	1076
mbed_official	579:53297373a894	1077	default:
mbed_official	579:53297373a894	1078	Assert(false);
mbed_official	579:53297373a894	1079	return STATUS_ERR_INVALID_ARG;
mbed_official	579:53297373a894	1080	}
mbed_official	579:53297373a894	1081
mbed_official	579:53297373a894	1082	return STATUS_OK;
mbed_official	579:53297373a894	1083	}
mbed_official	579:53297373a894	1084
mbed_official	579:53297373a894	1085	/**
mbed_official	579:53297373a894	1086	* @}
mbed_official	579:53297373a894	1087	*/
mbed_official	579:53297373a894	1088
mbed_official	579:53297373a894	1089	#ifdef FEATURE_SYSTEM_CLOCK_DPLL
mbed_official	579:53297373a894	1090	/**
mbed_official	579:53297373a894	1091	* \brief Reference clock source of the DPLL module.
mbed_official	579:53297373a894	1092	*/
mbed_official	579:53297373a894	1093	enum system_clock_source_dpll_reference_clock {
mbed_official	579:53297373a894	1094	/** Select CLK_DPLL_REF0 as clock reference. */
mbed_official	579:53297373a894	1095	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0,
mbed_official	579:53297373a894	1096	/** Select CLK_DPLL_REF1 as clock reference. */
mbed_official	579:53297373a894	1097	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1,
mbed_official	579:53297373a894	1098	/** Select GCLK_DPLL as clock reference. */
mbed_official	579:53297373a894	1099	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
mbed_official	579:53297373a894	1100	};
mbed_official	579:53297373a894	1101
mbed_official	579:53297373a894	1102	/**
mbed_official	579:53297373a894	1103	* \brief Lock time-out value of the DPLL module.
mbed_official	579:53297373a894	1104	*/
mbed_official	579:53297373a894	1105	enum system_clock_source_dpll_lock_time {
mbed_official	579:53297373a894	1106	/** Set no time-out as default. */
mbed_official	579:53297373a894	1107	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
mbed_official	579:53297373a894	1108	/** Set time-out if no lock within 8ms. */
mbed_official	579:53297373a894	1109	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
mbed_official	579:53297373a894	1110	/** Set time-out if no lock within 9ms. */
mbed_official	579:53297373a894	1111	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
mbed_official	579:53297373a894	1112	/** Set time-out if no lock within 10ms. */
mbed_official	579:53297373a894	1113	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
mbed_official	579:53297373a894	1114	/** Set time-out if no lock within 11ms. */
mbed_official	579:53297373a894	1115	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
mbed_official	579:53297373a894	1116	};
mbed_official	579:53297373a894	1117
mbed_official	579:53297373a894	1118	/**
mbed_official	579:53297373a894	1119	* \brief Filter type of the DPLL module.
mbed_official	579:53297373a894	1120	*/
mbed_official	579:53297373a894	1121	enum system_clock_source_dpll_filter {
mbed_official	579:53297373a894	1122	/** Default filter mode. */
mbed_official	579:53297373a894	1123	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
mbed_official	579:53297373a894	1124	/** Low bandwidth filter. */
mbed_official	579:53297373a894	1125	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
mbed_official	579:53297373a894	1126	/** High bandwidth filter. */
mbed_official	579:53297373a894	1127	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
mbed_official	579:53297373a894	1128	/** High damping filter. */
mbed_official	579:53297373a894	1129	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
mbed_official	579:53297373a894	1130	};
mbed_official	579:53297373a894	1131
mbed_official	579:53297373a894	1132	/**
mbed_official	579:53297373a894	1133	* \brief Configuration structure for DPLL.
mbed_official	579:53297373a894	1134	*
mbed_official	579:53297373a894	1135	* DPLL oscillator configuration structure.
mbed_official	579:53297373a894	1136	*/
mbed_official	579:53297373a894	1137	struct system_clock_source_dpll_config {
mbed_official	579:53297373a894	1138	/** Run On Demand. If this is set the DPLL won't run
mbed_official	579:53297373a894	1139	* until requested by a peripheral. */
mbed_official	579:53297373a894	1140	bool on_demand;
mbed_official	579:53297373a894	1141	/** Keep the DPLL enabled in standby sleep mode. */
mbed_official	579:53297373a894	1142	bool run_in_standby;
mbed_official	579:53297373a894	1143	/** Bypass lock signal. */
mbed_official	579:53297373a894	1144	bool lock_bypass;
mbed_official	579:53297373a894	1145	/** Wake up fast. If this is set DPLL output clock is enabled after
mbed_official	579:53297373a894	1146	* the startup time. */
mbed_official	579:53297373a894	1147	bool wake_up_fast;
mbed_official	579:53297373a894	1148	/** Enable low power mode. */
mbed_official	579:53297373a894	1149	bool low_power_enable;
mbed_official	579:53297373a894	1150
mbed_official	579:53297373a894	1151	/** Output frequency of the clock. */
mbed_official	579:53297373a894	1152	uint32_t output_frequency;
mbed_official	579:53297373a894	1153	/** Reference frequency of the clock. */
mbed_official	579:53297373a894	1154	uint32_t reference_frequency;
mbed_official	579:53297373a894	1155	/** Devider of reference clock. */
mbed_official	579:53297373a894	1156	uint16_t reference_divider;
mbed_official	579:53297373a894	1157
mbed_official	579:53297373a894	1158	/** Filter type of the DPLL module. */
mbed_official	579:53297373a894	1159	enum system_clock_source_dpll_filter filter;
mbed_official	579:53297373a894	1160	/** Lock time-out value of the DPLL module. */
mbed_official	579:53297373a894	1161	enum system_clock_source_dpll_lock_time lock_time;
mbed_official	579:53297373a894	1162	/** Reference clock source of the DPLL module. */
mbed_official	579:53297373a894	1163	enum system_clock_source_dpll_reference_clock reference_clock;
mbed_official	579:53297373a894	1164	};
mbed_official	579:53297373a894	1165
mbed_official	579:53297373a894	1166	/**
mbed_official	579:53297373a894	1167	* \name Internal DPLL Management
mbed_official	579:53297373a894	1168	* @{
mbed_official	579:53297373a894	1169	*/
mbed_official	579:53297373a894	1170
mbed_official	579:53297373a894	1171	/**
mbed_official	579:53297373a894	1172	* \brief Retrieve the default configuration for DPLL.
mbed_official	579:53297373a894	1173	*
mbed_official	579:53297373a894	1174	* Fills a configuration structure with the default configuration for a
mbed_official	579:53297373a894	1175	* DPLL oscillator module:
mbed_official	579:53297373a894	1176	* - Run only when requested by peripheral (on demand)
mbed_official	579:53297373a894	1177	* - Don't run in STANDBY sleep mode
mbed_official	579:53297373a894	1178	* - Lock bypass disabled
mbed_official	579:53297373a894	1179	* - Fast wake up disabled
mbed_official	579:53297373a894	1180	* - Low power mode disabled
mbed_official	579:53297373a894	1181	* - Output frequency is 48MHz
mbed_official	579:53297373a894	1182	* - Reference clock frequency is 32768Hz
mbed_official	579:53297373a894	1183	* - Not divide reference clock
mbed_official	579:53297373a894	1184	* - Select REF0 as reference clock
mbed_official	579:53297373a894	1185	* - Set lock time to default mode
mbed_official	579:53297373a894	1186	* - Use default filter
mbed_official	579:53297373a894	1187	*
mbed_official	579:53297373a894	1188	* \param[out] config Configuration structure to fill with default values
mbed_official	579:53297373a894	1189	*/
mbed_official	579:53297373a894	1190	static inline void system_clock_source_dpll_get_config_defaults(
mbed_official	579:53297373a894	1191	struct system_clock_source_dpll_config *const config)
mbed_official	579:53297373a894	1192	{
mbed_official	579:53297373a894	1193	config->on_demand = true;
mbed_official	579:53297373a894	1194	config->run_in_standby = false;
mbed_official	579:53297373a894	1195	config->lock_bypass = false;
mbed_official	579:53297373a894	1196	config->wake_up_fast = false;
mbed_official	579:53297373a894	1197	config->low_power_enable = false;
mbed_official	579:53297373a894	1198
mbed_official	579:53297373a894	1199	config->output_frequency = 48000000;
mbed_official	579:53297373a894	1200	config->reference_frequency = 32768;
mbed_official	579:53297373a894	1201	config->reference_divider = 1;
mbed_official	579:53297373a894	1202	config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0;
mbed_official	579:53297373a894	1203
mbed_official	579:53297373a894	1204	config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
mbed_official	579:53297373a894	1205	config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
mbed_official	579:53297373a894	1206	};
mbed_official	579:53297373a894	1207
mbed_official	579:53297373a894	1208	void system_clock_source_dpll_set_config(
mbed_official	579:53297373a894	1209	struct system_clock_source_dpll_config *const config);
mbed_official	579:53297373a894	1210
mbed_official	579:53297373a894	1211	/* @} */
mbed_official	579:53297373a894	1212	#endif
mbed_official	579:53297373a894	1213
mbed_official	579:53297373a894	1214	/**
mbed_official	579:53297373a894	1215	* \name System Clock Initialization
mbed_official	579:53297373a894	1216	* @{
mbed_official	579:53297373a894	1217	*/
mbed_official	579:53297373a894	1218
mbed_official	579:53297373a894	1219	void system_clock_init(void);
mbed_official	579:53297373a894	1220
mbed_official	579:53297373a894	1221	/**
mbed_official	579:53297373a894	1222	* @}
mbed_official	579:53297373a894	1223	*/
mbed_official	579:53297373a894	1224
mbed_official	579:53297373a894	1225	/**
mbed_official	579:53297373a894	1226	* \name System Flash Wait States
mbed_official	579:53297373a894	1227	* @{
mbed_official	579:53297373a894	1228	*/
mbed_official	579:53297373a894	1229
mbed_official	579:53297373a894	1230	/**
mbed_official	579:53297373a894	1231	* \brief Set flash controller wait states.
mbed_official	579:53297373a894	1232	*
mbed_official	579:53297373a894	1233	* Will set the number of wait states that are used by the onboard
mbed_official	579:53297373a894	1234	* flash memory. The number of wait states depend on both device
mbed_official	579:53297373a894	1235	* supply voltage and CPU speed. The required number of wait states
mbed_official	579:53297373a894	1236	* can be found in the electrical characteristics of the device.
mbed_official	579:53297373a894	1237	*
mbed_official	579:53297373a894	1238	* \param[in] wait_states Number of wait states to use for internal flash
mbed_official	579:53297373a894	1239	*/
mbed_official	579:53297373a894	1240	static inline void system_flash_set_waitstates(uint8_t wait_states)
mbed_official	579:53297373a894	1241	{
mbed_official	579:53297373a894	1242	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
mbed_official	579:53297373a894	1243	((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
mbed_official	579:53297373a894	1244
mbed_official	579:53297373a894	1245	NVMCTRL->CTRLB.bit.RWS = wait_states;
mbed_official	579:53297373a894	1246	}
mbed_official	579:53297373a894	1247	/**
mbed_official	579:53297373a894	1248	* @}
mbed_official	579:53297373a894	1249	*/
mbed_official	579:53297373a894	1250
mbed_official	579:53297373a894	1251	/**
mbed_official	579:53297373a894	1252	* @}
mbed_official	579:53297373a894	1253	*/
mbed_official	579:53297373a894	1254
mbed_official	579:53297373a894	1255	/**
mbed_official	579:53297373a894	1256	* \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver
mbed_official	579:53297373a894	1257	*
mbed_official	579:53297373a894	1258	* \section asfdoc_sam0_system_clock_extra_acronyms Acronyms
mbed_official	579:53297373a894	1259	* Below is a table listing the acronyms used in this module, along with their
mbed_official	579:53297373a894	1260	* intended meanings.
mbed_official	579:53297373a894	1261	*
mbed_official	579:53297373a894	1262	* <table>
mbed_official	579:53297373a894	1263	* <tr>
mbed_official	579:53297373a894	1264	* <th>Acronym</th>
mbed_official	579:53297373a894	1265	* <th>Description</th>
mbed_official	579:53297373a894	1266	* </tr>
mbed_official	579:53297373a894	1267	* <tr>
mbed_official	579:53297373a894	1268	* <td>DFLL</td>
mbed_official	579:53297373a894	1269	* <td>Digital Frequency Locked Loop</td>
mbed_official	579:53297373a894	1270	* </tr>
mbed_official	579:53297373a894	1271	* <tr>
mbed_official	579:53297373a894	1272	* <td>MUX</td>
mbed_official	579:53297373a894	1273	* <td>Multiplexer</td>
mbed_official	579:53297373a894	1274	* </tr>
mbed_official	579:53297373a894	1275	* <tr>
mbed_official	579:53297373a894	1276	* <td>OSC32K</td>
mbed_official	579:53297373a894	1277	* <td>Internal 32KHz Oscillator</td>
mbed_official	579:53297373a894	1278	* </tr>
mbed_official	579:53297373a894	1279	* <tr>
mbed_official	579:53297373a894	1280	* <td>OSC8M</td>
mbed_official	579:53297373a894	1281	* <td>Internal 8MHz Oscillator</td>
mbed_official	579:53297373a894	1282	* </tr>
mbed_official	579:53297373a894	1283	* <tr>
mbed_official	579:53297373a894	1284	* <td>PLL</td>
mbed_official	579:53297373a894	1285	* <td>Phase Locked Loop</td>
mbed_official	579:53297373a894	1286	* </tr>
mbed_official	579:53297373a894	1287	* <tr>
mbed_official	579:53297373a894	1288	* <td>OSC</td>
mbed_official	579:53297373a894	1289	* <td>Oscillator</td>
mbed_official	579:53297373a894	1290	* </tr>
mbed_official	579:53297373a894	1291	* <tr>
mbed_official	579:53297373a894	1292	* <td>XOSC</td>
mbed_official	579:53297373a894	1293	* <td>External Oscillator</td>
mbed_official	579:53297373a894	1294	* </tr>
mbed_official	579:53297373a894	1295	* <tr>
mbed_official	579:53297373a894	1296	* <td>XOSC32K</td>
mbed_official	579:53297373a894	1297	* <td>External 32KHz Oscillator</td>
mbed_official	579:53297373a894	1298	* </tr>
mbed_official	579:53297373a894	1299	* <tr>
mbed_official	579:53297373a894	1300	* <td>AHB</td>
mbed_official	579:53297373a894	1301	* <td>Advanced High-performance Bus</td>
mbed_official	579:53297373a894	1302	* </tr>
mbed_official	579:53297373a894	1303	* <tr>
mbed_official	579:53297373a894	1304	* <td>APB</td>
mbed_official	579:53297373a894	1305	* <td>Advanced Peripheral Bus</td>
mbed_official	579:53297373a894	1306	* </tr>
mbed_official	579:53297373a894	1307	* <tr>
mbed_official	579:53297373a894	1308	* <td>DPLL</td>
mbed_official	579:53297373a894	1309	* <td>Digital Phase Locked Loop</td>
mbed_official	579:53297373a894	1310	* </tr>
mbed_official	579:53297373a894	1311	* </table>
mbed_official	579:53297373a894	1312	*
mbed_official	579:53297373a894	1313	*
mbed_official	579:53297373a894	1314	* \section asfdoc_sam0_system_clock_extra_dependencies Dependencies
mbed_official	579:53297373a894	1315	* This driver has the following dependencies:
mbed_official	579:53297373a894	1316	*
mbed_official	579:53297373a894	1317	* - None
mbed_official	579:53297373a894	1318	*
mbed_official	579:53297373a894	1319	*
mbed_official	579:53297373a894	1320	* \section asfdoc_sam0_system_clock_extra_errata Errata
mbed_official	579:53297373a894	1321	*
mbed_official	579:53297373a894	1322	* - This driver implements workaround for errata 10558
mbed_official	579:53297373a894	1323	*
mbed_official	579:53297373a894	1324	* "Several reset values of SYSCTRL.INTFLAG are wrong (BOD and DFLL)"
mbed_official	579:53297373a894	1325	* When system_init is called it will reset these interrupts flags before they are used.
mbed_official	579:53297373a894	1326
mbed_official	579:53297373a894	1327	* - This driver implements experimental workaround for errata 9905
mbed_official	579:53297373a894	1328	*
mbed_official	579:53297373a894	1329	* "The DFLL clock must be requested before being configured otherwise a
mbed_official	579:53297373a894	1330	* write access to a DFLL register can freeze the device."
mbed_official	579:53297373a894	1331	* This driver will enable and configure the DFLL before the ONDEMAND bit is set.
mbed_official	579:53297373a894	1332	*
mbed_official	579:53297373a894	1333	*
mbed_official	579:53297373a894	1334	* \section asfdoc_sam0_system_clock_extra_history Module History
mbed_official	579:53297373a894	1335	* An overview of the module history is presented in the table below, with
mbed_official	579:53297373a894	1336	* details on the enhancements and fixes made to the module since its first
mbed_official	579:53297373a894	1337	* release. The current version of this corresponds to the newest version in
mbed_official	579:53297373a894	1338	* the table.
mbed_official	579:53297373a894	1339	*
mbed_official	579:53297373a894	1340	* <table>
mbed_official	579:53297373a894	1341	* <tr>
mbed_official	579:53297373a894	1342	* <th>Changelog</th>
mbed_official	579:53297373a894	1343	* </tr>
mbed_official	579:53297373a894	1344	* <tr>
mbed_official	579:53297373a894	1345	* <td>
mbed_official	579:53297373a894	1346	* \li Corrected OSC32K startup time definitions
mbed_official	579:53297373a894	1347	* \li Support locking of OSC32K and XOSC32K config register (default: false)
mbed_official	579:53297373a894	1348	* \li Added DPLL support, functions added:
mbed_official	579:53297373a894	1349	* \c system_clock_source_dpll_get_config_defaults() and
mbed_official	579:53297373a894	1350	* \c system_clock_source_dpll_set_config()
mbed_official	579:53297373a894	1351	* \li Moved gclk channel locking feature out of the config struct
mbed_official	579:53297373a894	1352	* functions added:
mbed_official	579:53297373a894	1353	* \c system_gclk_chan_lock(),
mbed_official	579:53297373a894	1354	* \c system_gclk_chan_is_locked()
mbed_official	579:53297373a894	1355	* \c system_gclk_chan_is_enabled() and
mbed_official	579:53297373a894	1356	* \c system_gclk_gen_is_enabled()
mbed_official	579:53297373a894	1357	* </td>
mbed_official	579:53297373a894	1358	* </tr>
mbed_official	579:53297373a894	1359	* <tr>
mbed_official	579:53297373a894	1360	* <td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
mbed_official	579:53297373a894	1361	* and configured to a failed/not running clock generator</td>
mbed_official	579:53297373a894	1362	* </tr>
mbed_official	579:53297373a894	1363	* <tr>
mbed_official	579:53297373a894	1364	* <td>
mbed_official	579:53297373a894	1365	* \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
mbed_official	579:53297373a894	1366	* \li Fixed system_flash_set_waitstates() failing with an assertion
mbed_official	579:53297373a894	1367	* if an odd number of wait states provided
mbed_official	579:53297373a894	1368	* </td>
mbed_official	579:53297373a894	1369	* </tr>
mbed_official	579:53297373a894	1370	* <tr>
mbed_official	579:53297373a894	1371	* <td>
mbed_official	579:53297373a894	1372	* \li Updated dfll configuration function to implement workaround for
mbed_official	579:53297373a894	1373	* errata 9905 in the DFLL module
mbed_official	579:53297373a894	1374	* \li Updated \c system_clock_init() to reset interrupt flags before
mbed_official	579:53297373a894	1375	* they are used, errata 10558
mbed_official	579:53297373a894	1376	* \li Fixed \c system_clock_source_get_hz() to return correcy DFLL
mbed_official	579:53297373a894	1377	* frequency number
mbed_official	579:53297373a894	1378	* </td>
mbed_official	579:53297373a894	1379	* </tr>
mbed_official	579:53297373a894	1380	* <tr>
mbed_official	579:53297373a894	1381	* <td>\li Fixed \c system_clock_source_is_ready not returning the correct
mbed_official	579:53297373a894	1382	* state for \c SYSTEM_CLOCK_SOURCE_OSC8M
mbed_official	579:53297373a894	1383	* \li Renamed the various \c system_clock_source_*_get_default_config()
mbed_official	579:53297373a894	1384	* functions to \c system_clock_source_*_get_config_defaults() to
mbed_official	579:53297373a894	1385	* match the remainder of ASF
mbed_official	579:53297373a894	1386	* \li Added OSC8M calibration constant loading from the device signature
mbed_official	579:53297373a894	1387	* row when the oscillator is initialized
mbed_official	579:53297373a894	1388	* \li Updated default configuration of the XOSC32 to disable Automatic
mbed_official	579:53297373a894	1389	* Gain Control due to silicon errata
mbed_official	579:53297373a894	1390	* </td>
mbed_official	579:53297373a894	1391	* </tr>
mbed_official	579:53297373a894	1392	* <tr>
mbed_official	579:53297373a894	1393	* <td>Initial Release</td>
mbed_official	579:53297373a894	1394	* </tr>
mbed_official	579:53297373a894	1395	* </table>
mbed_official	579:53297373a894	1396	*/
mbed_official	579:53297373a894	1397
mbed_official	579:53297373a894	1398	/**
mbed_official	579:53297373a894	1399	* \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver
mbed_official	579:53297373a894	1400	*
mbed_official	579:53297373a894	1401	* This is a list of the available Quick Start guides (QSGs) and example
mbed_official	579:53297373a894	1402	* applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple
mbed_official	579:53297373a894	1403	* examples with step-by-step instructions to configure and use this driver in
mbed_official	579:53297373a894	1404	* a selection of use cases. Note that QSGs can be compiled as a standalone
mbed_official	579:53297373a894	1405	* application or be added to the user application.
mbed_official	579:53297373a894	1406	*
mbed_official	579:53297373a894	1407	* - \subpage asfdoc_sam0_system_clock_basic_use_case
mbed_official	579:53297373a894	1408	* - \subpage asfdoc_sam0_system_gclk_basic_use_case
mbed_official	579:53297373a894	1409	*
mbed_official	579:53297373a894	1410	* \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
mbed_official	579:53297373a894	1411	*
mbed_official	579:53297373a894	1412	* <table>
mbed_official	579:53297373a894	1413	* <tr>
mbed_official	579:53297373a894	1414	* <th>Doc. Rev.</td>
mbed_official	579:53297373a894	1415	* <th>Date</td>
mbed_official	579:53297373a894	1416	* <th>Comments</td>
mbed_official	579:53297373a894	1417	* </tr>
mbed_official	579:53297373a894	1418	* <tr>
mbed_official	579:53297373a894	1419	* <td>D</td>
mbed_official	579:53297373a894	1420	* <td>12/2014</td>
mbed_official	579:53297373a894	1421	* <td>Added support for SAMR21 and SAMD10/D11.</td>
mbed_official	579:53297373a894	1422	* </tr>
mbed_official	579:53297373a894	1423	* <tr>
mbed_official	579:53297373a894	1424	* <td>C</td>
mbed_official	579:53297373a894	1425	* <td>01/2014</td>
mbed_official	579:53297373a894	1426	* <td>Added support for SAMD21.</td>
mbed_official	579:53297373a894	1427	* </tr>
mbed_official	579:53297373a894	1428	* <tr>
mbed_official	579:53297373a894	1429	* <td>B</td>
mbed_official	579:53297373a894	1430	* <td>06/2013</td>
mbed_official	579:53297373a894	1431	* <td>Corrected documentation typos. Fixed missing steps in the Basic
mbed_official	579:53297373a894	1432	* Use Case Quick Start Guide.</td>
mbed_official	579:53297373a894	1433	* </tr>
mbed_official	579:53297373a894	1434	* <tr>
mbed_official	579:53297373a894	1435	* <td>A</td>
mbed_official	579:53297373a894	1436	* <td>06/2013</td>
mbed_official	579:53297373a894	1437	* <td>Initial release</td>
mbed_official	579:53297373a894	1438	* </tr>
mbed_official	579:53297373a894	1439	* </table>
mbed_official	579:53297373a894	1440	*/
mbed_official	579:53297373a894	1441
mbed_official	579:53297373a894	1442	#ifdef __cplusplus
mbed_official	579:53297373a894	1443	}
mbed_official	579:53297373a894	1444	#endif
mbed_official	579:53297373a894	1445
mbed_official	579:53297373a894	1446	#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */

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Type:	Library
Created:	27 Oct 2015
Imports:	0
Forks:	0
Commits:	637
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targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock_feature.h@592:a274ee790e56, 2015-07-17 (annotated)

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