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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_tcc1.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_TCC1_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_TCC1_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for TCC1 peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */
mbed_official 579:53297373a894 7 #define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */
mbed_official 579:53297373a894 8 #define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */
mbed_official 579:53297373a894 9 #define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
mbed_official 579:53297373a894 10 #define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
mbed_official 579:53297373a894 11 #define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
mbed_official 579:53297373a894 12 #define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */
mbed_official 579:53297373a894 13 #define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */
mbed_official 579:53297373a894 14 #define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */
mbed_official 579:53297373a894 15 #define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
mbed_official 579:53297373a894 16 #define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
mbed_official 579:53297373a894 17 #define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 18 #define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */
mbed_official 579:53297373a894 19 #define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */
mbed_official 579:53297373a894 20 #define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */
mbed_official 579:53297373a894 21 #define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */
mbed_official 579:53297373a894 22 #define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */
mbed_official 579:53297373a894 23 #define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
mbed_official 579:53297373a894 24 #define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
mbed_official 579:53297373a894 25 #define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
mbed_official 579:53297373a894 26 #define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
mbed_official 579:53297373a894 27 #define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */
mbed_official 579:53297373a894 28 #define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
mbed_official 579:53297373a894 29 #define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
mbed_official 579:53297373a894 30 #else
mbed_official 579:53297373a894 31 #define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */
mbed_official 579:53297373a894 32 #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
mbed_official 579:53297373a894 33 #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
mbed_official 579:53297373a894 34 #define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
mbed_official 579:53297373a894 35 #define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
mbed_official 579:53297373a894 36 #define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
mbed_official 579:53297373a894 37 #define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */
mbed_official 579:53297373a894 38 #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
mbed_official 579:53297373a894 39 #define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */
mbed_official 579:53297373a894 40 #define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
mbed_official 579:53297373a894 41 #define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
mbed_official 579:53297373a894 42 #define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 43 #define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */
mbed_official 579:53297373a894 44 #define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */
mbed_official 579:53297373a894 45 #define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
mbed_official 579:53297373a894 46 #define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
mbed_official 579:53297373a894 47 #define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */
mbed_official 579:53297373a894 48 #define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
mbed_official 579:53297373a894 49 #define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
mbed_official 579:53297373a894 50 #define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
mbed_official 579:53297373a894 51 #define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
mbed_official 579:53297373a894 52 #define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
mbed_official 579:53297373a894 53 #define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
mbed_official 579:53297373a894 54 #define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
mbed_official 579:53297373a894 55 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 56
mbed_official 579:53297373a894 57 /* ========== Instance parameters for TCC1 peripheral ========== */
mbed_official 579:53297373a894 58 #define TCC1_CC_NUM 2 // Number of Compare/Capture units
mbed_official 579:53297373a894 59 #define TCC1_DITHERING 1 // Dithering feature implemented
mbed_official 579:53297373a894 60 #define TCC1_DMAC_ID_MC_0 19
mbed_official 579:53297373a894 61 #define TCC1_DMAC_ID_MC_1 20
mbed_official 579:53297373a894 62 #define TCC1_DMAC_ID_MC_LSB 19
mbed_official 579:53297373a894 63 #define TCC1_DMAC_ID_MC_MSB 20
mbed_official 579:53297373a894 64 #define TCC1_DMAC_ID_MC_SIZE 2
mbed_official 579:53297373a894 65 #define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger
mbed_official 579:53297373a894 66 #define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
mbed_official 579:53297373a894 67 #define TCC1_EXT 24 // Coding of implemented extended features
mbed_official 579:53297373a894 68 #define TCC1_GCLK_ID 26 // Index of Generic Clock
mbed_official 579:53297373a894 69 #define TCC1_OTMX 0 // Output Matrix feature implemented
mbed_official 579:53297373a894 70 #define TCC1_OW_NUM 4 // Number of Output Waveforms
mbed_official 579:53297373a894 71 #define TCC1_PG 1 // Pattern Generation feature implemented
mbed_official 579:53297373a894 72 #define TCC1_SIZE 24
mbed_official 579:53297373a894 73 #define TCC1_SWAP 0 // DTI outputs swap feature implemented
mbed_official 579:53297373a894 74 #define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
mbed_official 579:53297373a894 75
mbed_official 579:53297373a894 76 #endif /* _SAMD21_TCC1_INSTANCE_ */