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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_port.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_PORT_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_PORT_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for PORT peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */
mbed_official 579:53297373a894 7 #define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
mbed_official 579:53297373a894 8 #define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
mbed_official 579:53297373a894 9 #define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
mbed_official 579:53297373a894 10 #define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
mbed_official 579:53297373a894 11 #define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
mbed_official 579:53297373a894 12 #define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
mbed_official 579:53297373a894 13 #define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
mbed_official 579:53297373a894 14 #define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
mbed_official 579:53297373a894 15 #define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */
mbed_official 579:53297373a894 16 #define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
mbed_official 579:53297373a894 17 #define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
mbed_official 579:53297373a894 18 #define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
mbed_official 579:53297373a894 19 #define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
mbed_official 579:53297373a894 20 #define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
mbed_official 579:53297373a894 21 #define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
mbed_official 579:53297373a894 22 #define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
mbed_official 579:53297373a894 23 #define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
mbed_official 579:53297373a894 24 #define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
mbed_official 579:53297373a894 25 #define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
mbed_official 579:53297373a894 26 #define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
mbed_official 579:53297373a894 27 #define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
mbed_official 579:53297373a894 28 #define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
mbed_official 579:53297373a894 29 #define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
mbed_official 579:53297373a894 30 #define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
mbed_official 579:53297373a894 31 #define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
mbed_official 579:53297373a894 32 #else
mbed_official 579:53297373a894 33 #define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
mbed_official 579:53297373a894 34 #define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
mbed_official 579:53297373a894 35 #define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
mbed_official 579:53297373a894 36 #define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
mbed_official 579:53297373a894 37 #define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
mbed_official 579:53297373a894 38 #define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
mbed_official 579:53297373a894 39 #define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
mbed_official 579:53297373a894 40 #define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
mbed_official 579:53297373a894 41 #define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
mbed_official 579:53297373a894 42 #define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */
mbed_official 579:53297373a894 43 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
mbed_official 579:53297373a894 44 #define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
mbed_official 579:53297373a894 45 #define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
mbed_official 579:53297373a894 46 #define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
mbed_official 579:53297373a894 47 #define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
mbed_official 579:53297373a894 48 #define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
mbed_official 579:53297373a894 49 #define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
mbed_official 579:53297373a894 50 #define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
mbed_official 579:53297373a894 51 #define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
mbed_official 579:53297373a894 52 #define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
mbed_official 579:53297373a894 53 #define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
mbed_official 579:53297373a894 54 #define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
mbed_official 579:53297373a894 55 #define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
mbed_official 579:53297373a894 56 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
mbed_official 579:53297373a894 57 #define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
mbed_official 579:53297373a894 58 #define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
mbed_official 579:53297373a894 59 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 60
mbed_official 579:53297373a894 61 /* ========== Instance parameters for PORT peripheral ========== */
mbed_official 579:53297373a894 62 #define PORT_BITS 84 // Number of PORT pins
mbed_official 579:53297373a894 63 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
mbed_official 579:53297373a894 64 #define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
mbed_official 579:53297373a894 65 #define PORT_DRVSTR 1 // DRVSTR supported
mbed_official 579:53297373a894 66 #define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
mbed_official 579:53297373a894 67 #define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
mbed_official 579:53297373a894 68 #define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
mbed_official 579:53297373a894 69 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
mbed_official 579:53297373a894 70 #define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
mbed_official 579:53297373a894 71 #define PORT_ODRAIN 0 // ODRAIN supported
mbed_official 579:53297373a894 72 #define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
mbed_official 579:53297373a894 73 #define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
mbed_official 579:53297373a894 74 #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
mbed_official 579:53297373a894 75 #define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
mbed_official 579:53297373a894 76 #define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
mbed_official 579:53297373a894 77 #define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
mbed_official 579:53297373a894 78 #define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
mbed_official 579:53297373a894 79 #define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
mbed_official 579:53297373a894 80 #define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
mbed_official 579:53297373a894 81 #define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
mbed_official 579:53297373a894 82 #define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
mbed_official 579:53297373a894 83 #define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
mbed_official 579:53297373a894 84 #define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
mbed_official 579:53297373a894 85 #define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
mbed_official 579:53297373a894 86 #define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
mbed_official 579:53297373a894 87 #define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
mbed_official 579:53297373a894 88 #define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
mbed_official 579:53297373a894 89 #define PORT_SLEWLIM 0 // SLEWLIM supported
mbed_official 579:53297373a894 90 #define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
mbed_official 579:53297373a894 91 #define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
mbed_official 579:53297373a894 92
mbed_official 579:53297373a894 93 #endif /* _SAMD21_PORT_INSTANCE_ */