marcus chiou / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_adc.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_ADC_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_ADC_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for ADC peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */
mbed_official 579:53297373a894 7 #define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */
mbed_official 579:53297373a894 8 #define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */
mbed_official 579:53297373a894 9 #define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */
mbed_official 579:53297373a894 10 #define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */
mbed_official 579:53297373a894 11 #define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */
mbed_official 579:53297373a894 12 #define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */
mbed_official 579:53297373a894 13 #define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */
mbed_official 579:53297373a894 14 #define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */
mbed_official 579:53297373a894 15 #define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
mbed_official 579:53297373a894 16 #define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
mbed_official 579:53297373a894 17 #define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 18 #define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */
mbed_official 579:53297373a894 19 #define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */
mbed_official 579:53297373a894 20 #define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
mbed_official 579:53297373a894 21 #define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
mbed_official 579:53297373a894 22 #define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */
mbed_official 579:53297373a894 23 #define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */
mbed_official 579:53297373a894 24 #define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */
mbed_official 579:53297373a894 25 #define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */
mbed_official 579:53297373a894 26 #else
mbed_official 579:53297373a894 27 #define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
mbed_official 579:53297373a894 28 #define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
mbed_official 579:53297373a894 29 #define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
mbed_official 579:53297373a894 30 #define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
mbed_official 579:53297373a894 31 #define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
mbed_official 579:53297373a894 32 #define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
mbed_official 579:53297373a894 33 #define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
mbed_official 579:53297373a894 34 #define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */
mbed_official 579:53297373a894 35 #define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
mbed_official 579:53297373a894 36 #define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
mbed_official 579:53297373a894 37 #define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
mbed_official 579:53297373a894 38 #define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 39 #define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
mbed_official 579:53297373a894 40 #define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
mbed_official 579:53297373a894 41 #define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
mbed_official 579:53297373a894 42 #define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
mbed_official 579:53297373a894 43 #define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
mbed_official 579:53297373a894 44 #define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
mbed_official 579:53297373a894 45 #define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
mbed_official 579:53297373a894 46 #define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
mbed_official 579:53297373a894 47 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 48
mbed_official 579:53297373a894 49 /* ========== Instance parameters for ADC peripheral ========== */
mbed_official 579:53297373a894 50 #define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger
mbed_official 579:53297373a894 51 #define ADC_EXTCHANNEL_MSB 19 // Number of external channels
mbed_official 579:53297373a894 52 #define ADC_GCLK_ID 30 // Index of Generic Clock
mbed_official 579:53297373a894 53 #define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield
mbed_official 579:53297373a894 54 #define ADC_RESULT_MSB 15 // Size of Result
mbed_official 579:53297373a894 55
mbed_official 579:53297373a894 56 #endif /* _SAMD21_ADC_INSTANCE_ */