mbed library sources
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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_rtc.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_RTC_COMPONENT_ |
mbed_official | 579:53297373a894 | 2 | #define _SAMD21_RTC_COMPONENT_ |
mbed_official | 579:53297373a894 | 3 | |
mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR RTC */ |
mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_RTC Real-Time Counter */ |
mbed_official | 579:53297373a894 | 8 | /*@{*/ |
mbed_official | 579:53297373a894 | 9 | |
mbed_official | 579:53297373a894 | 10 | #define RTC_U2202 |
mbed_official | 579:53297373a894 | 11 | #define REV_RTC 0x101 |
mbed_official | 579:53297373a894 | 12 | |
mbed_official | 579:53297373a894 | 13 | /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ |
mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 15 | typedef union { |
mbed_official | 579:53297373a894 | 16 | struct { |
mbed_official | 579:53297373a894 | 17 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 18 | uint16_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 19 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ |
mbed_official | 579:53297373a894 | 20 | uint16_t :3; /*!< bit: 4.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 21 | uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ |
mbed_official | 579:53297373a894 | 22 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ |
mbed_official | 579:53297373a894 | 23 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
mbed_official | 579:53297373a894 | 24 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 25 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 26 | } RTC_MODE0_CTRL_Type; |
mbed_official | 579:53297373a894 | 27 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 28 | |
mbed_official | 579:53297373a894 | 29 | #define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */ |
mbed_official | 579:53297373a894 | 30 | #define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */ |
mbed_official | 579:53297373a894 | 31 | |
mbed_official | 579:53297373a894 | 32 | #define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */ |
mbed_official | 579:53297373a894 | 33 | #define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos) |
mbed_official | 579:53297373a894 | 34 | #define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */ |
mbed_official | 579:53297373a894 | 35 | #define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 36 | #define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */ |
mbed_official | 579:53297373a894 | 37 | #define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 38 | #define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))) |
mbed_official | 579:53297373a894 | 39 | #define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */ |
mbed_official | 579:53297373a894 | 40 | #define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */ |
mbed_official | 579:53297373a894 | 41 | #define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */ |
mbed_official | 579:53297373a894 | 42 | #define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 43 | #define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 44 | #define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 45 | #define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */ |
mbed_official | 579:53297373a894 | 46 | #define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos) |
mbed_official | 579:53297373a894 | 47 | #define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */ |
mbed_official | 579:53297373a894 | 48 | #define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 49 | #define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))) |
mbed_official | 579:53297373a894 | 50 | #define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ |
mbed_official | 579:53297373a894 | 51 | #define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ |
mbed_official | 579:53297373a894 | 52 | #define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ |
mbed_official | 579:53297373a894 | 53 | #define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ |
mbed_official | 579:53297373a894 | 54 | #define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ |
mbed_official | 579:53297373a894 | 55 | #define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ |
mbed_official | 579:53297373a894 | 56 | #define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ |
mbed_official | 579:53297373a894 | 57 | #define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ |
mbed_official | 579:53297373a894 | 58 | #define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ |
mbed_official | 579:53297373a894 | 59 | #define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ |
mbed_official | 579:53297373a894 | 60 | #define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ |
mbed_official | 579:53297373a894 | 61 | #define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 62 | #define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 63 | #define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 64 | #define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 65 | #define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 66 | #define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 67 | #define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 68 | #define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 69 | #define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 70 | #define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 71 | #define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 72 | #define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 73 | |
mbed_official | 579:53297373a894 | 74 | /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ |
mbed_official | 579:53297373a894 | 75 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 76 | typedef union { |
mbed_official | 579:53297373a894 | 77 | struct { |
mbed_official | 579:53297373a894 | 78 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 79 | uint16_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 80 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ |
mbed_official | 579:53297373a894 | 81 | uint16_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 82 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ |
mbed_official | 579:53297373a894 | 83 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
mbed_official | 579:53297373a894 | 84 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 85 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 86 | } RTC_MODE1_CTRL_Type; |
mbed_official | 579:53297373a894 | 87 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 88 | |
mbed_official | 579:53297373a894 | 89 | #define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */ |
mbed_official | 579:53297373a894 | 90 | #define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */ |
mbed_official | 579:53297373a894 | 91 | |
mbed_official | 579:53297373a894 | 92 | #define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */ |
mbed_official | 579:53297373a894 | 93 | #define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos) |
mbed_official | 579:53297373a894 | 94 | #define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */ |
mbed_official | 579:53297373a894 | 95 | #define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 96 | #define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */ |
mbed_official | 579:53297373a894 | 97 | #define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 98 | #define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))) |
mbed_official | 579:53297373a894 | 99 | #define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */ |
mbed_official | 579:53297373a894 | 100 | #define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */ |
mbed_official | 579:53297373a894 | 101 | #define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */ |
mbed_official | 579:53297373a894 | 102 | #define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 103 | #define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 104 | #define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 105 | #define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */ |
mbed_official | 579:53297373a894 | 106 | #define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 107 | #define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))) |
mbed_official | 579:53297373a894 | 108 | #define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ |
mbed_official | 579:53297373a894 | 109 | #define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ |
mbed_official | 579:53297373a894 | 110 | #define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ |
mbed_official | 579:53297373a894 | 111 | #define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ |
mbed_official | 579:53297373a894 | 112 | #define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ |
mbed_official | 579:53297373a894 | 113 | #define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ |
mbed_official | 579:53297373a894 | 114 | #define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ |
mbed_official | 579:53297373a894 | 115 | #define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ |
mbed_official | 579:53297373a894 | 116 | #define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ |
mbed_official | 579:53297373a894 | 117 | #define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ |
mbed_official | 579:53297373a894 | 118 | #define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ |
mbed_official | 579:53297373a894 | 119 | #define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 120 | #define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 121 | #define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 122 | #define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 123 | #define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 124 | #define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 125 | #define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 126 | #define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 127 | #define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 128 | #define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 129 | #define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 130 | #define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 131 | |
mbed_official | 579:53297373a894 | 132 | /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ |
mbed_official | 579:53297373a894 | 133 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 134 | typedef union { |
mbed_official | 579:53297373a894 | 135 | struct { |
mbed_official | 579:53297373a894 | 136 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 137 | uint16_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 138 | uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ |
mbed_official | 579:53297373a894 | 139 | uint16_t :2; /*!< bit: 4.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 140 | uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ |
mbed_official | 579:53297373a894 | 141 | uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ |
mbed_official | 579:53297373a894 | 142 | uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ |
mbed_official | 579:53297373a894 | 143 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
mbed_official | 579:53297373a894 | 144 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 145 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 146 | } RTC_MODE2_CTRL_Type; |
mbed_official | 579:53297373a894 | 147 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 148 | |
mbed_official | 579:53297373a894 | 149 | #define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */ |
mbed_official | 579:53297373a894 | 150 | #define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */ |
mbed_official | 579:53297373a894 | 151 | |
mbed_official | 579:53297373a894 | 152 | #define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */ |
mbed_official | 579:53297373a894 | 153 | #define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos) |
mbed_official | 579:53297373a894 | 154 | #define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */ |
mbed_official | 579:53297373a894 | 155 | #define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 156 | #define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */ |
mbed_official | 579:53297373a894 | 157 | #define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 158 | #define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))) |
mbed_official | 579:53297373a894 | 159 | #define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */ |
mbed_official | 579:53297373a894 | 160 | #define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */ |
mbed_official | 579:53297373a894 | 161 | #define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */ |
mbed_official | 579:53297373a894 | 162 | #define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 163 | #define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 164 | #define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos) |
mbed_official | 579:53297373a894 | 165 | #define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */ |
mbed_official | 579:53297373a894 | 166 | #define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos) |
mbed_official | 579:53297373a894 | 167 | #define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */ |
mbed_official | 579:53297373a894 | 168 | #define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos) |
mbed_official | 579:53297373a894 | 169 | #define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */ |
mbed_official | 579:53297373a894 | 170 | #define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 171 | #define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))) |
mbed_official | 579:53297373a894 | 172 | #define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ |
mbed_official | 579:53297373a894 | 173 | #define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ |
mbed_official | 579:53297373a894 | 174 | #define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ |
mbed_official | 579:53297373a894 | 175 | #define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ |
mbed_official | 579:53297373a894 | 176 | #define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ |
mbed_official | 579:53297373a894 | 177 | #define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ |
mbed_official | 579:53297373a894 | 178 | #define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ |
mbed_official | 579:53297373a894 | 179 | #define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ |
mbed_official | 579:53297373a894 | 180 | #define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ |
mbed_official | 579:53297373a894 | 181 | #define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ |
mbed_official | 579:53297373a894 | 182 | #define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ |
mbed_official | 579:53297373a894 | 183 | #define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 184 | #define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 185 | #define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 186 | #define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 187 | #define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 188 | #define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 189 | #define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 190 | #define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 191 | #define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 192 | #define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 193 | #define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos) |
mbed_official | 579:53297373a894 | 194 | #define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 195 | |
mbed_official | 579:53297373a894 | 196 | /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ |
mbed_official | 579:53297373a894 | 197 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 198 | typedef union { |
mbed_official | 579:53297373a894 | 199 | struct { |
mbed_official | 579:53297373a894 | 200 | uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ |
mbed_official | 579:53297373a894 | 201 | uint16_t :8; /*!< bit: 6..13 Reserved */ |
mbed_official | 579:53297373a894 | 202 | uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ |
mbed_official | 579:53297373a894 | 203 | uint16_t RREQ:1; /*!< bit: 15 Read Request */ |
mbed_official | 579:53297373a894 | 204 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 205 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 206 | } RTC_READREQ_Type; |
mbed_official | 579:53297373a894 | 207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 208 | |
mbed_official | 579:53297373a894 | 209 | #define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */ |
mbed_official | 579:53297373a894 | 210 | #define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */ |
mbed_official | 579:53297373a894 | 211 | |
mbed_official | 579:53297373a894 | 212 | #define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */ |
mbed_official | 579:53297373a894 | 213 | #define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos) |
mbed_official | 579:53297373a894 | 214 | #define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))) |
mbed_official | 579:53297373a894 | 215 | #define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */ |
mbed_official | 579:53297373a894 | 216 | #define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos) |
mbed_official | 579:53297373a894 | 217 | #define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */ |
mbed_official | 579:53297373a894 | 218 | #define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos) |
mbed_official | 579:53297373a894 | 219 | #define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */ |
mbed_official | 579:53297373a894 | 220 | |
mbed_official | 579:53297373a894 | 221 | /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ |
mbed_official | 579:53297373a894 | 222 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 223 | typedef union { |
mbed_official | 579:53297373a894 | 224 | struct { |
mbed_official | 579:53297373a894 | 225 | uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 226 | uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 227 | uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 228 | uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 229 | uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 230 | uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 231 | uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 232 | uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 233 | uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 234 | uint16_t :6; /*!< bit: 9..14 Reserved */ |
mbed_official | 579:53297373a894 | 235 | uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ |
mbed_official | 579:53297373a894 | 236 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 237 | struct { |
mbed_official | 579:53297373a894 | 238 | uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ |
mbed_official | 579:53297373a894 | 239 | uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ |
mbed_official | 579:53297373a894 | 240 | uint16_t :7; /*!< bit: 9..15 Reserved */ |
mbed_official | 579:53297373a894 | 241 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 242 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 243 | } RTC_MODE0_EVCTRL_Type; |
mbed_official | 579:53297373a894 | 244 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 245 | |
mbed_official | 579:53297373a894 | 246 | #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ |
mbed_official | 579:53297373a894 | 247 | #define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ |
mbed_official | 579:53297373a894 | 248 | |
mbed_official | 579:53297373a894 | 249 | #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 250 | #define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos) |
mbed_official | 579:53297373a894 | 251 | #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 252 | #define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos) |
mbed_official | 579:53297373a894 | 253 | #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 254 | #define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos) |
mbed_official | 579:53297373a894 | 255 | #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 256 | #define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos) |
mbed_official | 579:53297373a894 | 257 | #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 258 | #define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos) |
mbed_official | 579:53297373a894 | 259 | #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 260 | #define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos) |
mbed_official | 579:53297373a894 | 261 | #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 262 | #define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos) |
mbed_official | 579:53297373a894 | 263 | #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 264 | #define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos) |
mbed_official | 579:53297373a894 | 265 | #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ |
mbed_official | 579:53297373a894 | 266 | #define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos) |
mbed_official | 579:53297373a894 | 267 | #define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))) |
mbed_official | 579:53297373a894 | 268 | #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 269 | #define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos) |
mbed_official | 579:53297373a894 | 270 | #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ |
mbed_official | 579:53297373a894 | 271 | #define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos) |
mbed_official | 579:53297373a894 | 272 | #define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))) |
mbed_official | 579:53297373a894 | 273 | #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ |
mbed_official | 579:53297373a894 | 274 | #define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos) |
mbed_official | 579:53297373a894 | 275 | #define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 276 | |
mbed_official | 579:53297373a894 | 277 | /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ |
mbed_official | 579:53297373a894 | 278 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 279 | typedef union { |
mbed_official | 579:53297373a894 | 280 | struct { |
mbed_official | 579:53297373a894 | 281 | uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 282 | uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 283 | uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 284 | uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 285 | uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 286 | uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 287 | uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 288 | uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 289 | uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 290 | uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 291 | uint16_t :5; /*!< bit: 10..14 Reserved */ |
mbed_official | 579:53297373a894 | 292 | uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ |
mbed_official | 579:53297373a894 | 293 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 294 | struct { |
mbed_official | 579:53297373a894 | 295 | uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ |
mbed_official | 579:53297373a894 | 296 | uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ |
mbed_official | 579:53297373a894 | 297 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
mbed_official | 579:53297373a894 | 298 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 299 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 300 | } RTC_MODE1_EVCTRL_Type; |
mbed_official | 579:53297373a894 | 301 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 302 | |
mbed_official | 579:53297373a894 | 303 | #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ |
mbed_official | 579:53297373a894 | 304 | #define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ |
mbed_official | 579:53297373a894 | 305 | |
mbed_official | 579:53297373a894 | 306 | #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 307 | #define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos) |
mbed_official | 579:53297373a894 | 308 | #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 309 | #define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos) |
mbed_official | 579:53297373a894 | 310 | #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 311 | #define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos) |
mbed_official | 579:53297373a894 | 312 | #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 313 | #define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos) |
mbed_official | 579:53297373a894 | 314 | #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 315 | #define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos) |
mbed_official | 579:53297373a894 | 316 | #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 317 | #define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos) |
mbed_official | 579:53297373a894 | 318 | #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 319 | #define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos) |
mbed_official | 579:53297373a894 | 320 | #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 321 | #define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos) |
mbed_official | 579:53297373a894 | 322 | #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ |
mbed_official | 579:53297373a894 | 323 | #define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos) |
mbed_official | 579:53297373a894 | 324 | #define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))) |
mbed_official | 579:53297373a894 | 325 | #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 326 | #define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos) |
mbed_official | 579:53297373a894 | 327 | #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 328 | #define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos) |
mbed_official | 579:53297373a894 | 329 | #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ |
mbed_official | 579:53297373a894 | 330 | #define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos) |
mbed_official | 579:53297373a894 | 331 | #define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))) |
mbed_official | 579:53297373a894 | 332 | #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ |
mbed_official | 579:53297373a894 | 333 | #define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos) |
mbed_official | 579:53297373a894 | 334 | #define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 335 | |
mbed_official | 579:53297373a894 | 336 | /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ |
mbed_official | 579:53297373a894 | 337 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 338 | typedef union { |
mbed_official | 579:53297373a894 | 339 | struct { |
mbed_official | 579:53297373a894 | 340 | uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 341 | uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 342 | uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 343 | uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 344 | uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 345 | uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 346 | uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 347 | uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 348 | uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 349 | uint16_t :6; /*!< bit: 9..14 Reserved */ |
mbed_official | 579:53297373a894 | 350 | uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ |
mbed_official | 579:53297373a894 | 351 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 352 | struct { |
mbed_official | 579:53297373a894 | 353 | uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ |
mbed_official | 579:53297373a894 | 354 | uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ |
mbed_official | 579:53297373a894 | 355 | uint16_t :7; /*!< bit: 9..15 Reserved */ |
mbed_official | 579:53297373a894 | 356 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 357 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 358 | } RTC_MODE2_EVCTRL_Type; |
mbed_official | 579:53297373a894 | 359 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 360 | |
mbed_official | 579:53297373a894 | 361 | #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ |
mbed_official | 579:53297373a894 | 362 | #define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ |
mbed_official | 579:53297373a894 | 363 | |
mbed_official | 579:53297373a894 | 364 | #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 365 | #define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos) |
mbed_official | 579:53297373a894 | 366 | #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 367 | #define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos) |
mbed_official | 579:53297373a894 | 368 | #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 369 | #define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos) |
mbed_official | 579:53297373a894 | 370 | #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 371 | #define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos) |
mbed_official | 579:53297373a894 | 372 | #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 373 | #define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos) |
mbed_official | 579:53297373a894 | 374 | #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 375 | #define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos) |
mbed_official | 579:53297373a894 | 376 | #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 377 | #define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos) |
mbed_official | 579:53297373a894 | 378 | #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 379 | #define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos) |
mbed_official | 579:53297373a894 | 380 | #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ |
mbed_official | 579:53297373a894 | 381 | #define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos) |
mbed_official | 579:53297373a894 | 382 | #define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))) |
mbed_official | 579:53297373a894 | 383 | #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 384 | #define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos) |
mbed_official | 579:53297373a894 | 385 | #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ |
mbed_official | 579:53297373a894 | 386 | #define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos) |
mbed_official | 579:53297373a894 | 387 | #define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))) |
mbed_official | 579:53297373a894 | 388 | #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ |
mbed_official | 579:53297373a894 | 389 | #define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos) |
mbed_official | 579:53297373a894 | 390 | #define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 391 | |
mbed_official | 579:53297373a894 | 392 | /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 393 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 394 | typedef union { |
mbed_official | 579:53297373a894 | 395 | struct { |
mbed_official | 579:53297373a894 | 396 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 397 | uint8_t :5; /*!< bit: 1.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 398 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 399 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 400 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 401 | struct { |
mbed_official | 579:53297373a894 | 402 | uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 403 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 404 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 405 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 406 | } RTC_MODE0_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 407 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 408 | |
mbed_official | 579:53297373a894 | 409 | #define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 410 | #define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 411 | |
mbed_official | 579:53297373a894 | 412 | #define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 413 | #define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos) |
mbed_official | 579:53297373a894 | 414 | #define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 415 | #define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos) |
mbed_official | 579:53297373a894 | 416 | #define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))) |
mbed_official | 579:53297373a894 | 417 | #define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 418 | #define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 419 | #define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 420 | #define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos) |
mbed_official | 579:53297373a894 | 421 | #define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 422 | |
mbed_official | 579:53297373a894 | 423 | /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 424 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 425 | typedef union { |
mbed_official | 579:53297373a894 | 426 | struct { |
mbed_official | 579:53297373a894 | 427 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 428 | uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 429 | uint8_t :4; /*!< bit: 2.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 430 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 431 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 432 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 433 | struct { |
mbed_official | 579:53297373a894 | 434 | uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 435 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 436 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 437 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 438 | } RTC_MODE1_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 439 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 440 | |
mbed_official | 579:53297373a894 | 441 | #define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 442 | #define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 443 | |
mbed_official | 579:53297373a894 | 444 | #define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 445 | #define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos) |
mbed_official | 579:53297373a894 | 446 | #define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 447 | #define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos) |
mbed_official | 579:53297373a894 | 448 | #define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 449 | #define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos) |
mbed_official | 579:53297373a894 | 450 | #define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))) |
mbed_official | 579:53297373a894 | 451 | #define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 452 | #define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 453 | #define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 454 | #define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos) |
mbed_official | 579:53297373a894 | 455 | #define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 456 | |
mbed_official | 579:53297373a894 | 457 | /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 458 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 459 | typedef union { |
mbed_official | 579:53297373a894 | 460 | struct { |
mbed_official | 579:53297373a894 | 461 | uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 462 | uint8_t :5; /*!< bit: 1.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 463 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 464 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 465 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 466 | struct { |
mbed_official | 579:53297373a894 | 467 | uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 468 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 469 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 470 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 471 | } RTC_MODE2_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 472 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 473 | |
mbed_official | 579:53297373a894 | 474 | #define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 475 | #define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 476 | |
mbed_official | 579:53297373a894 | 477 | #define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 478 | #define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos) |
mbed_official | 579:53297373a894 | 479 | #define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 480 | #define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos) |
mbed_official | 579:53297373a894 | 481 | #define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))) |
mbed_official | 579:53297373a894 | 482 | #define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 483 | #define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 484 | #define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 485 | #define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos) |
mbed_official | 579:53297373a894 | 486 | #define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 487 | |
mbed_official | 579:53297373a894 | 488 | /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 489 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 490 | typedef union { |
mbed_official | 579:53297373a894 | 491 | struct { |
mbed_official | 579:53297373a894 | 492 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 493 | uint8_t :5; /*!< bit: 1.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 494 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 495 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 496 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 497 | struct { |
mbed_official | 579:53297373a894 | 498 | uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 499 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 500 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 501 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 502 | } RTC_MODE0_INTENSET_Type; |
mbed_official | 579:53297373a894 | 503 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 504 | |
mbed_official | 579:53297373a894 | 505 | #define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 506 | #define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 507 | |
mbed_official | 579:53297373a894 | 508 | #define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 509 | #define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos) |
mbed_official | 579:53297373a894 | 510 | #define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 511 | #define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos) |
mbed_official | 579:53297373a894 | 512 | #define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))) |
mbed_official | 579:53297373a894 | 513 | #define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 514 | #define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 515 | #define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 516 | #define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos) |
mbed_official | 579:53297373a894 | 517 | #define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 518 | |
mbed_official | 579:53297373a894 | 519 | /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 520 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 521 | typedef union { |
mbed_official | 579:53297373a894 | 522 | struct { |
mbed_official | 579:53297373a894 | 523 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 524 | uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 525 | uint8_t :4; /*!< bit: 2.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 526 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 527 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 528 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 529 | struct { |
mbed_official | 579:53297373a894 | 530 | uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 531 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 532 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 533 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 534 | } RTC_MODE1_INTENSET_Type; |
mbed_official | 579:53297373a894 | 535 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 536 | |
mbed_official | 579:53297373a894 | 537 | #define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 538 | #define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 539 | |
mbed_official | 579:53297373a894 | 540 | #define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 541 | #define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos) |
mbed_official | 579:53297373a894 | 542 | #define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 543 | #define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos) |
mbed_official | 579:53297373a894 | 544 | #define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 545 | #define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos) |
mbed_official | 579:53297373a894 | 546 | #define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))) |
mbed_official | 579:53297373a894 | 547 | #define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 548 | #define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 549 | #define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 550 | #define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos) |
mbed_official | 579:53297373a894 | 551 | #define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 552 | |
mbed_official | 579:53297373a894 | 553 | /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 554 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 555 | typedef union { |
mbed_official | 579:53297373a894 | 556 | struct { |
mbed_official | 579:53297373a894 | 557 | uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 558 | uint8_t :5; /*!< bit: 1.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 559 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 560 | uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 561 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 562 | struct { |
mbed_official | 579:53297373a894 | 563 | uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 564 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 565 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 566 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 567 | } RTC_MODE2_INTENSET_Type; |
mbed_official | 579:53297373a894 | 568 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 569 | |
mbed_official | 579:53297373a894 | 570 | #define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 571 | #define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 572 | |
mbed_official | 579:53297373a894 | 573 | #define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ |
mbed_official | 579:53297373a894 | 574 | #define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos) |
mbed_official | 579:53297373a894 | 575 | #define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ |
mbed_official | 579:53297373a894 | 576 | #define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos) |
mbed_official | 579:53297373a894 | 577 | #define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))) |
mbed_official | 579:53297373a894 | 578 | #define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */ |
mbed_official | 579:53297373a894 | 579 | #define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 580 | #define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ |
mbed_official | 579:53297373a894 | 581 | #define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos) |
mbed_official | 579:53297373a894 | 582 | #define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 583 | |
mbed_official | 579:53297373a894 | 584 | /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 585 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 586 | typedef union { |
mbed_official | 579:53297373a894 | 587 | struct { |
mbed_official | 579:53297373a894 | 588 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ |
mbed_official | 579:53297373a894 | 589 | uint8_t :5; /*!< bit: 1.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 590 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ |
mbed_official | 579:53297373a894 | 591 | uint8_t OVF:1; /*!< bit: 7 Overflow */ |
mbed_official | 579:53297373a894 | 592 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 593 | struct { |
mbed_official | 579:53297373a894 | 594 | uint8_t CMP:1; /*!< bit: 0 Compare x */ |
mbed_official | 579:53297373a894 | 595 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 596 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 597 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 598 | } RTC_MODE0_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 599 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 600 | |
mbed_official | 579:53297373a894 | 601 | #define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 602 | #define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 603 | |
mbed_official | 579:53297373a894 | 604 | #define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ |
mbed_official | 579:53297373a894 | 605 | #define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos) |
mbed_official | 579:53297373a894 | 606 | #define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ |
mbed_official | 579:53297373a894 | 607 | #define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos) |
mbed_official | 579:53297373a894 | 608 | #define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))) |
mbed_official | 579:53297373a894 | 609 | #define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */ |
mbed_official | 579:53297373a894 | 610 | #define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 611 | #define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ |
mbed_official | 579:53297373a894 | 612 | #define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos) |
mbed_official | 579:53297373a894 | 613 | #define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 614 | |
mbed_official | 579:53297373a894 | 615 | /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 616 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 617 | typedef union { |
mbed_official | 579:53297373a894 | 618 | struct { |
mbed_official | 579:53297373a894 | 619 | uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ |
mbed_official | 579:53297373a894 | 620 | uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ |
mbed_official | 579:53297373a894 | 621 | uint8_t :4; /*!< bit: 2.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 622 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ |
mbed_official | 579:53297373a894 | 623 | uint8_t OVF:1; /*!< bit: 7 Overflow */ |
mbed_official | 579:53297373a894 | 624 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 625 | struct { |
mbed_official | 579:53297373a894 | 626 | uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ |
mbed_official | 579:53297373a894 | 627 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 628 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 629 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 630 | } RTC_MODE1_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 631 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 632 | |
mbed_official | 579:53297373a894 | 633 | #define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 634 | #define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 635 | |
mbed_official | 579:53297373a894 | 636 | #define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ |
mbed_official | 579:53297373a894 | 637 | #define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos) |
mbed_official | 579:53297373a894 | 638 | #define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ |
mbed_official | 579:53297373a894 | 639 | #define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos) |
mbed_official | 579:53297373a894 | 640 | #define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ |
mbed_official | 579:53297373a894 | 641 | #define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos) |
mbed_official | 579:53297373a894 | 642 | #define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))) |
mbed_official | 579:53297373a894 | 643 | #define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */ |
mbed_official | 579:53297373a894 | 644 | #define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 645 | #define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ |
mbed_official | 579:53297373a894 | 646 | #define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos) |
mbed_official | 579:53297373a894 | 647 | #define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 648 | |
mbed_official | 579:53297373a894 | 649 | /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 650 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 651 | typedef union { |
mbed_official | 579:53297373a894 | 652 | struct { |
mbed_official | 579:53297373a894 | 653 | uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ |
mbed_official | 579:53297373a894 | 654 | uint8_t :5; /*!< bit: 1.. 5 Reserved */ |
mbed_official | 579:53297373a894 | 655 | uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ |
mbed_official | 579:53297373a894 | 656 | uint8_t OVF:1; /*!< bit: 7 Overflow */ |
mbed_official | 579:53297373a894 | 657 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 658 | struct { |
mbed_official | 579:53297373a894 | 659 | uint8_t ALARM:1; /*!< bit: 0 Alarm x */ |
mbed_official | 579:53297373a894 | 660 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 661 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 662 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 663 | } RTC_MODE2_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 664 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 665 | |
mbed_official | 579:53297373a894 | 666 | #define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 667 | #define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 668 | |
mbed_official | 579:53297373a894 | 669 | #define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ |
mbed_official | 579:53297373a894 | 670 | #define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos) |
mbed_official | 579:53297373a894 | 671 | #define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ |
mbed_official | 579:53297373a894 | 672 | #define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos) |
mbed_official | 579:53297373a894 | 673 | #define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))) |
mbed_official | 579:53297373a894 | 674 | #define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */ |
mbed_official | 579:53297373a894 | 675 | #define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos) |
mbed_official | 579:53297373a894 | 676 | #define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ |
mbed_official | 579:53297373a894 | 677 | #define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos) |
mbed_official | 579:53297373a894 | 678 | #define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 679 | |
mbed_official | 579:53297373a894 | 680 | /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ |
mbed_official | 579:53297373a894 | 681 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 682 | typedef union { |
mbed_official | 579:53297373a894 | 683 | struct { |
mbed_official | 579:53297373a894 | 684 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 685 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ |
mbed_official | 579:53297373a894 | 686 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 687 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 688 | } RTC_STATUS_Type; |
mbed_official | 579:53297373a894 | 689 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 690 | |
mbed_official | 579:53297373a894 | 691 | #define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */ |
mbed_official | 579:53297373a894 | 692 | #define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */ |
mbed_official | 579:53297373a894 | 693 | |
mbed_official | 579:53297373a894 | 694 | #define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */ |
mbed_official | 579:53297373a894 | 695 | #define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos) |
mbed_official | 579:53297373a894 | 696 | #define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 697 | |
mbed_official | 579:53297373a894 | 698 | /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ |
mbed_official | 579:53297373a894 | 699 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 700 | typedef union { |
mbed_official | 579:53297373a894 | 701 | struct { |
mbed_official | 579:53297373a894 | 702 | uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ |
mbed_official | 579:53297373a894 | 703 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 704 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 705 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 706 | } RTC_DBGCTRL_Type; |
mbed_official | 579:53297373a894 | 707 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 708 | |
mbed_official | 579:53297373a894 | 709 | #define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */ |
mbed_official | 579:53297373a894 | 710 | #define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ |
mbed_official | 579:53297373a894 | 711 | |
mbed_official | 579:53297373a894 | 712 | #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ |
mbed_official | 579:53297373a894 | 713 | #define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos) |
mbed_official | 579:53297373a894 | 714 | #define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 715 | |
mbed_official | 579:53297373a894 | 716 | /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ |
mbed_official | 579:53297373a894 | 717 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 718 | typedef union { |
mbed_official | 579:53297373a894 | 719 | struct { |
mbed_official | 579:53297373a894 | 720 | uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ |
mbed_official | 579:53297373a894 | 721 | uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ |
mbed_official | 579:53297373a894 | 722 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 723 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 724 | } RTC_FREQCORR_Type; |
mbed_official | 579:53297373a894 | 725 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 726 | |
mbed_official | 579:53297373a894 | 727 | #define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */ |
mbed_official | 579:53297373a894 | 728 | #define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ |
mbed_official | 579:53297373a894 | 729 | |
mbed_official | 579:53297373a894 | 730 | #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ |
mbed_official | 579:53297373a894 | 731 | #define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos) |
mbed_official | 579:53297373a894 | 732 | #define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))) |
mbed_official | 579:53297373a894 | 733 | #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ |
mbed_official | 579:53297373a894 | 734 | #define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos) |
mbed_official | 579:53297373a894 | 735 | #define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */ |
mbed_official | 579:53297373a894 | 736 | |
mbed_official | 579:53297373a894 | 737 | /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ |
mbed_official | 579:53297373a894 | 738 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 739 | typedef union { |
mbed_official | 579:53297373a894 | 740 | struct { |
mbed_official | 579:53297373a894 | 741 | uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ |
mbed_official | 579:53297373a894 | 742 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 743 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 744 | } RTC_MODE0_COUNT_Type; |
mbed_official | 579:53297373a894 | 745 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 746 | |
mbed_official | 579:53297373a894 | 747 | #define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ |
mbed_official | 579:53297373a894 | 748 | #define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ |
mbed_official | 579:53297373a894 | 749 | |
mbed_official | 579:53297373a894 | 750 | #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ |
mbed_official | 579:53297373a894 | 751 | #define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos) |
mbed_official | 579:53297373a894 | 752 | #define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))) |
mbed_official | 579:53297373a894 | 753 | #define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */ |
mbed_official | 579:53297373a894 | 754 | |
mbed_official | 579:53297373a894 | 755 | /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ |
mbed_official | 579:53297373a894 | 756 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 757 | typedef union { |
mbed_official | 579:53297373a894 | 758 | struct { |
mbed_official | 579:53297373a894 | 759 | uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ |
mbed_official | 579:53297373a894 | 760 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 761 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 762 | } RTC_MODE1_COUNT_Type; |
mbed_official | 579:53297373a894 | 763 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 764 | |
mbed_official | 579:53297373a894 | 765 | #define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ |
mbed_official | 579:53297373a894 | 766 | #define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ |
mbed_official | 579:53297373a894 | 767 | |
mbed_official | 579:53297373a894 | 768 | #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ |
mbed_official | 579:53297373a894 | 769 | #define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos) |
mbed_official | 579:53297373a894 | 770 | #define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))) |
mbed_official | 579:53297373a894 | 771 | #define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */ |
mbed_official | 579:53297373a894 | 772 | |
mbed_official | 579:53297373a894 | 773 | /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ |
mbed_official | 579:53297373a894 | 774 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 775 | typedef union { |
mbed_official | 579:53297373a894 | 776 | struct { |
mbed_official | 579:53297373a894 | 777 | uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ |
mbed_official | 579:53297373a894 | 778 | uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ |
mbed_official | 579:53297373a894 | 779 | uint32_t HOUR:5; /*!< bit: 12..16 Hour */ |
mbed_official | 579:53297373a894 | 780 | uint32_t DAY:5; /*!< bit: 17..21 Day */ |
mbed_official | 579:53297373a894 | 781 | uint32_t MONTH:4; /*!< bit: 22..25 Month */ |
mbed_official | 579:53297373a894 | 782 | uint32_t YEAR:6; /*!< bit: 26..31 Year */ |
mbed_official | 579:53297373a894 | 783 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 784 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 785 | } RTC_MODE2_CLOCK_Type; |
mbed_official | 579:53297373a894 | 786 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 787 | |
mbed_official | 579:53297373a894 | 788 | #define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ |
mbed_official | 579:53297373a894 | 789 | #define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ |
mbed_official | 579:53297373a894 | 790 | |
mbed_official | 579:53297373a894 | 791 | #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ |
mbed_official | 579:53297373a894 | 792 | #define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos) |
mbed_official | 579:53297373a894 | 793 | #define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))) |
mbed_official | 579:53297373a894 | 794 | #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ |
mbed_official | 579:53297373a894 | 795 | #define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos) |
mbed_official | 579:53297373a894 | 796 | #define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))) |
mbed_official | 579:53297373a894 | 797 | #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ |
mbed_official | 579:53297373a894 | 798 | #define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos) |
mbed_official | 579:53297373a894 | 799 | #define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))) |
mbed_official | 579:53297373a894 | 800 | #define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */ |
mbed_official | 579:53297373a894 | 801 | #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos) |
mbed_official | 579:53297373a894 | 802 | #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ |
mbed_official | 579:53297373a894 | 803 | #define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos) |
mbed_official | 579:53297373a894 | 804 | #define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))) |
mbed_official | 579:53297373a894 | 805 | #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ |
mbed_official | 579:53297373a894 | 806 | #define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos) |
mbed_official | 579:53297373a894 | 807 | #define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))) |
mbed_official | 579:53297373a894 | 808 | #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ |
mbed_official | 579:53297373a894 | 809 | #define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos) |
mbed_official | 579:53297373a894 | 810 | #define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))) |
mbed_official | 579:53297373a894 | 811 | #define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */ |
mbed_official | 579:53297373a894 | 812 | |
mbed_official | 579:53297373a894 | 813 | /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ |
mbed_official | 579:53297373a894 | 814 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 815 | typedef union { |
mbed_official | 579:53297373a894 | 816 | struct { |
mbed_official | 579:53297373a894 | 817 | uint16_t PER:16; /*!< bit: 0..15 Counter Period */ |
mbed_official | 579:53297373a894 | 818 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 819 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 820 | } RTC_MODE1_PER_Type; |
mbed_official | 579:53297373a894 | 821 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 822 | |
mbed_official | 579:53297373a894 | 823 | #define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ |
mbed_official | 579:53297373a894 | 824 | #define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ |
mbed_official | 579:53297373a894 | 825 | |
mbed_official | 579:53297373a894 | 826 | #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ |
mbed_official | 579:53297373a894 | 827 | #define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos) |
mbed_official | 579:53297373a894 | 828 | #define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))) |
mbed_official | 579:53297373a894 | 829 | #define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */ |
mbed_official | 579:53297373a894 | 830 | |
mbed_official | 579:53297373a894 | 831 | /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ |
mbed_official | 579:53297373a894 | 832 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 833 | typedef union { |
mbed_official | 579:53297373a894 | 834 | struct { |
mbed_official | 579:53297373a894 | 835 | uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ |
mbed_official | 579:53297373a894 | 836 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 837 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 838 | } RTC_MODE0_COMP_Type; |
mbed_official | 579:53297373a894 | 839 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 840 | |
mbed_official | 579:53297373a894 | 841 | #define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ |
mbed_official | 579:53297373a894 | 842 | #define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ |
mbed_official | 579:53297373a894 | 843 | |
mbed_official | 579:53297373a894 | 844 | #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ |
mbed_official | 579:53297373a894 | 845 | #define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos) |
mbed_official | 579:53297373a894 | 846 | #define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))) |
mbed_official | 579:53297373a894 | 847 | #define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */ |
mbed_official | 579:53297373a894 | 848 | |
mbed_official | 579:53297373a894 | 849 | /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ |
mbed_official | 579:53297373a894 | 850 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 851 | typedef union { |
mbed_official | 579:53297373a894 | 852 | struct { |
mbed_official | 579:53297373a894 | 853 | uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ |
mbed_official | 579:53297373a894 | 854 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 855 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 856 | } RTC_MODE1_COMP_Type; |
mbed_official | 579:53297373a894 | 857 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 858 | |
mbed_official | 579:53297373a894 | 859 | #define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ |
mbed_official | 579:53297373a894 | 860 | #define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ |
mbed_official | 579:53297373a894 | 861 | |
mbed_official | 579:53297373a894 | 862 | #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ |
mbed_official | 579:53297373a894 | 863 | #define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos) |
mbed_official | 579:53297373a894 | 864 | #define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))) |
mbed_official | 579:53297373a894 | 865 | #define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */ |
mbed_official | 579:53297373a894 | 866 | |
mbed_official | 579:53297373a894 | 867 | /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ |
mbed_official | 579:53297373a894 | 868 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 869 | typedef union { |
mbed_official | 579:53297373a894 | 870 | struct { |
mbed_official | 579:53297373a894 | 871 | uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ |
mbed_official | 579:53297373a894 | 872 | uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ |
mbed_official | 579:53297373a894 | 873 | uint32_t HOUR:5; /*!< bit: 12..16 Hour */ |
mbed_official | 579:53297373a894 | 874 | uint32_t DAY:5; /*!< bit: 17..21 Day */ |
mbed_official | 579:53297373a894 | 875 | uint32_t MONTH:4; /*!< bit: 22..25 Month */ |
mbed_official | 579:53297373a894 | 876 | uint32_t YEAR:6; /*!< bit: 26..31 Year */ |
mbed_official | 579:53297373a894 | 877 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 878 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 879 | } RTC_MODE2_ALARM_Type; |
mbed_official | 579:53297373a894 | 880 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 881 | |
mbed_official | 579:53297373a894 | 882 | #define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ |
mbed_official | 579:53297373a894 | 883 | #define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ |
mbed_official | 579:53297373a894 | 884 | |
mbed_official | 579:53297373a894 | 885 | #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ |
mbed_official | 579:53297373a894 | 886 | #define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos) |
mbed_official | 579:53297373a894 | 887 | #define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))) |
mbed_official | 579:53297373a894 | 888 | #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ |
mbed_official | 579:53297373a894 | 889 | #define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos) |
mbed_official | 579:53297373a894 | 890 | #define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))) |
mbed_official | 579:53297373a894 | 891 | #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ |
mbed_official | 579:53297373a894 | 892 | #define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos) |
mbed_official | 579:53297373a894 | 893 | #define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))) |
mbed_official | 579:53297373a894 | 894 | #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ |
mbed_official | 579:53297373a894 | 895 | #define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos) |
mbed_official | 579:53297373a894 | 896 | #define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))) |
mbed_official | 579:53297373a894 | 897 | #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ |
mbed_official | 579:53297373a894 | 898 | #define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos) |
mbed_official | 579:53297373a894 | 899 | #define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))) |
mbed_official | 579:53297373a894 | 900 | #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ |
mbed_official | 579:53297373a894 | 901 | #define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos) |
mbed_official | 579:53297373a894 | 902 | #define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))) |
mbed_official | 579:53297373a894 | 903 | #define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */ |
mbed_official | 579:53297373a894 | 904 | |
mbed_official | 579:53297373a894 | 905 | /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ |
mbed_official | 579:53297373a894 | 906 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 907 | typedef union { |
mbed_official | 579:53297373a894 | 908 | struct { |
mbed_official | 579:53297373a894 | 909 | uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ |
mbed_official | 579:53297373a894 | 910 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 911 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 912 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 913 | } RTC_MODE2_MASK_Type; |
mbed_official | 579:53297373a894 | 914 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 915 | |
mbed_official | 579:53297373a894 | 916 | #define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ |
mbed_official | 579:53297373a894 | 917 | #define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ |
mbed_official | 579:53297373a894 | 918 | |
mbed_official | 579:53297373a894 | 919 | #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ |
mbed_official | 579:53297373a894 | 920 | #define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 921 | #define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))) |
mbed_official | 579:53297373a894 | 922 | #define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ |
mbed_official | 579:53297373a894 | 923 | #define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */ |
mbed_official | 579:53297373a894 | 924 | #define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ |
mbed_official | 579:53297373a894 | 925 | #define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ |
mbed_official | 579:53297373a894 | 926 | #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ |
mbed_official | 579:53297373a894 | 927 | #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ |
mbed_official | 579:53297373a894 | 928 | #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ |
mbed_official | 579:53297373a894 | 929 | #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 930 | #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 931 | #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 932 | #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 933 | #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 934 | #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 935 | #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) |
mbed_official | 579:53297373a894 | 936 | #define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */ |
mbed_official | 579:53297373a894 | 937 | |
mbed_official | 579:53297373a894 | 938 | /** \brief RtcMode2Alarm hardware registers */ |
mbed_official | 579:53297373a894 | 939 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 940 | typedef struct { |
mbed_official | 579:53297373a894 | 941 | __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ |
mbed_official | 579:53297373a894 | 942 | __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ |
mbed_official | 579:53297373a894 | 943 | RoReg8 Reserved1[0x3]; |
mbed_official | 579:53297373a894 | 944 | } RtcMode2Alarm; |
mbed_official | 579:53297373a894 | 945 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 946 | |
mbed_official | 579:53297373a894 | 947 | /** \brief RTC_MODE0 hardware registers */ |
mbed_official | 579:53297373a894 | 948 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 949 | typedef struct { /* 32-bit Counter with Single 32-bit Compare */ |
mbed_official | 579:53297373a894 | 950 | __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ |
mbed_official | 579:53297373a894 | 951 | __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ |
mbed_official | 579:53297373a894 | 952 | __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ |
mbed_official | 579:53297373a894 | 953 | __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 954 | __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 955 | __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 956 | RoReg8 Reserved1[0x1]; |
mbed_official | 579:53297373a894 | 957 | __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ |
mbed_official | 579:53297373a894 | 958 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ |
mbed_official | 579:53297373a894 | 959 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ |
mbed_official | 579:53297373a894 | 960 | RoReg8 Reserved2[0x3]; |
mbed_official | 579:53297373a894 | 961 | __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ |
mbed_official | 579:53297373a894 | 962 | RoReg8 Reserved3[0x4]; |
mbed_official | 579:53297373a894 | 963 | __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ |
mbed_official | 579:53297373a894 | 964 | } RtcMode0; |
mbed_official | 579:53297373a894 | 965 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 966 | |
mbed_official | 579:53297373a894 | 967 | /** \brief RTC_MODE1 hardware registers */ |
mbed_official | 579:53297373a894 | 968 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 969 | typedef struct { /* 16-bit Counter with Two 16-bit Compares */ |
mbed_official | 579:53297373a894 | 970 | __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ |
mbed_official | 579:53297373a894 | 971 | __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ |
mbed_official | 579:53297373a894 | 972 | __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ |
mbed_official | 579:53297373a894 | 973 | __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 974 | __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 975 | __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 976 | RoReg8 Reserved1[0x1]; |
mbed_official | 579:53297373a894 | 977 | __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ |
mbed_official | 579:53297373a894 | 978 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ |
mbed_official | 579:53297373a894 | 979 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ |
mbed_official | 579:53297373a894 | 980 | RoReg8 Reserved2[0x3]; |
mbed_official | 579:53297373a894 | 981 | __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ |
mbed_official | 579:53297373a894 | 982 | RoReg8 Reserved3[0x2]; |
mbed_official | 579:53297373a894 | 983 | __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ |
mbed_official | 579:53297373a894 | 984 | RoReg8 Reserved4[0x2]; |
mbed_official | 579:53297373a894 | 985 | __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ |
mbed_official | 579:53297373a894 | 986 | } RtcMode1; |
mbed_official | 579:53297373a894 | 987 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 988 | |
mbed_official | 579:53297373a894 | 989 | /** \brief RTC_MODE2 hardware registers */ |
mbed_official | 579:53297373a894 | 990 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 991 | typedef struct { /* Clock/Calendar with Alarm */ |
mbed_official | 579:53297373a894 | 992 | __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ |
mbed_official | 579:53297373a894 | 993 | __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ |
mbed_official | 579:53297373a894 | 994 | __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ |
mbed_official | 579:53297373a894 | 995 | __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 996 | __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 997 | __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 998 | RoReg8 Reserved1[0x1]; |
mbed_official | 579:53297373a894 | 999 | __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ |
mbed_official | 579:53297373a894 | 1000 | __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ |
mbed_official | 579:53297373a894 | 1001 | __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ |
mbed_official | 579:53297373a894 | 1002 | RoReg8 Reserved2[0x3]; |
mbed_official | 579:53297373a894 | 1003 | __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ |
mbed_official | 579:53297373a894 | 1004 | RoReg8 Reserved3[0x4]; |
mbed_official | 579:53297373a894 | 1005 | RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ |
mbed_official | 579:53297373a894 | 1006 | } RtcMode2; |
mbed_official | 579:53297373a894 | 1007 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1008 | |
mbed_official | 579:53297373a894 | 1009 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1010 | typedef union { |
mbed_official | 579:53297373a894 | 1011 | RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ |
mbed_official | 579:53297373a894 | 1012 | RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ |
mbed_official | 579:53297373a894 | 1013 | RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ |
mbed_official | 579:53297373a894 | 1014 | } Rtc; |
mbed_official | 579:53297373a894 | 1015 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1016 | |
mbed_official | 579:53297373a894 | 1017 | /*@}*/ |
mbed_official | 579:53297373a894 | 1018 | |
mbed_official | 579:53297373a894 | 1019 | #endif /* _SAMD21_RTC_COMPONENT_ */ |