mbed library sources
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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_eic.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_EIC_COMPONENT_ |
mbed_official | 579:53297373a894 | 2 | #define _SAMD21_EIC_COMPONENT_ |
mbed_official | 579:53297373a894 | 3 | |
mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR EIC */ |
mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_EIC External Interrupt Controller */ |
mbed_official | 579:53297373a894 | 8 | /*@{*/ |
mbed_official | 579:53297373a894 | 9 | |
mbed_official | 579:53297373a894 | 10 | #define EIC_U2217 |
mbed_official | 579:53297373a894 | 11 | #define REV_EIC 0x101 |
mbed_official | 579:53297373a894 | 12 | |
mbed_official | 579:53297373a894 | 13 | /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */ |
mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 15 | typedef union { |
mbed_official | 579:53297373a894 | 16 | struct { |
mbed_official | 579:53297373a894 | 17 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 18 | uint8_t ENABLE:1; /*!< bit: 1 Enable */ |
mbed_official | 579:53297373a894 | 19 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 20 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 21 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 22 | } EIC_CTRL_Type; |
mbed_official | 579:53297373a894 | 23 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 24 | |
mbed_official | 579:53297373a894 | 25 | #define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */ |
mbed_official | 579:53297373a894 | 26 | #define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */ |
mbed_official | 579:53297373a894 | 27 | |
mbed_official | 579:53297373a894 | 28 | #define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */ |
mbed_official | 579:53297373a894 | 29 | #define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos) |
mbed_official | 579:53297373a894 | 30 | #define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */ |
mbed_official | 579:53297373a894 | 31 | #define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 32 | #define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 33 | |
mbed_official | 579:53297373a894 | 34 | /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */ |
mbed_official | 579:53297373a894 | 35 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 36 | typedef union { |
mbed_official | 579:53297373a894 | 37 | struct { |
mbed_official | 579:53297373a894 | 38 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 39 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ |
mbed_official | 579:53297373a894 | 40 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 41 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 42 | } EIC_STATUS_Type; |
mbed_official | 579:53297373a894 | 43 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 44 | |
mbed_official | 579:53297373a894 | 45 | #define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */ |
mbed_official | 579:53297373a894 | 46 | #define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */ |
mbed_official | 579:53297373a894 | 47 | |
mbed_official | 579:53297373a894 | 48 | #define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */ |
mbed_official | 579:53297373a894 | 49 | #define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos) |
mbed_official | 579:53297373a894 | 50 | #define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 51 | |
mbed_official | 579:53297373a894 | 52 | /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */ |
mbed_official | 579:53297373a894 | 53 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 54 | typedef union { |
mbed_official | 579:53297373a894 | 55 | struct { |
mbed_official | 579:53297373a894 | 56 | uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ |
mbed_official | 579:53297373a894 | 57 | uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ |
mbed_official | 579:53297373a894 | 58 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 59 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 60 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 61 | } EIC_NMICTRL_Type; |
mbed_official | 579:53297373a894 | 62 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 63 | |
mbed_official | 579:53297373a894 | 64 | #define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */ |
mbed_official | 579:53297373a894 | 65 | #define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */ |
mbed_official | 579:53297373a894 | 66 | |
mbed_official | 579:53297373a894 | 67 | #define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */ |
mbed_official | 579:53297373a894 | 68 | #define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos) |
mbed_official | 579:53297373a894 | 69 | #define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))) |
mbed_official | 579:53297373a894 | 70 | #define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */ |
mbed_official | 579:53297373a894 | 71 | #define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */ |
mbed_official | 579:53297373a894 | 72 | #define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */ |
mbed_official | 579:53297373a894 | 73 | #define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */ |
mbed_official | 579:53297373a894 | 74 | #define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */ |
mbed_official | 579:53297373a894 | 75 | #define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */ |
mbed_official | 579:53297373a894 | 76 | #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) |
mbed_official | 579:53297373a894 | 77 | #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) |
mbed_official | 579:53297373a894 | 78 | #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) |
mbed_official | 579:53297373a894 | 79 | #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) |
mbed_official | 579:53297373a894 | 80 | #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) |
mbed_official | 579:53297373a894 | 81 | #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) |
mbed_official | 579:53297373a894 | 82 | #define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */ |
mbed_official | 579:53297373a894 | 83 | #define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos) |
mbed_official | 579:53297373a894 | 84 | #define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 85 | |
mbed_official | 579:53297373a894 | 86 | /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 87 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 88 | typedef union { |
mbed_official | 579:53297373a894 | 89 | struct { |
mbed_official | 579:53297373a894 | 90 | uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ |
mbed_official | 579:53297373a894 | 91 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 92 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 93 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 94 | } EIC_NMIFLAG_Type; |
mbed_official | 579:53297373a894 | 95 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 96 | |
mbed_official | 579:53297373a894 | 97 | #define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 98 | #define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 99 | |
mbed_official | 579:53297373a894 | 100 | #define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */ |
mbed_official | 579:53297373a894 | 101 | #define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos) |
mbed_official | 579:53297373a894 | 102 | #define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 103 | |
mbed_official | 579:53297373a894 | 104 | /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */ |
mbed_official | 579:53297373a894 | 105 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 106 | typedef union { |
mbed_official | 579:53297373a894 | 107 | struct { |
mbed_official | 579:53297373a894 | 108 | uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 109 | uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 110 | uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 111 | uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 112 | uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 113 | uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 114 | uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 115 | uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 116 | uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ |
mbed_official | 579:53297373a894 | 117 | uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ |
mbed_official | 579:53297373a894 | 118 | uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ |
mbed_official | 579:53297373a894 | 119 | uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ |
mbed_official | 579:53297373a894 | 120 | uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ |
mbed_official | 579:53297373a894 | 121 | uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ |
mbed_official | 579:53297373a894 | 122 | uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ |
mbed_official | 579:53297373a894 | 123 | uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ |
mbed_official | 579:53297373a894 | 124 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 125 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 126 | struct { |
mbed_official | 579:53297373a894 | 127 | uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ |
mbed_official | 579:53297373a894 | 128 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 129 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 130 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 131 | } EIC_EVCTRL_Type; |
mbed_official | 579:53297373a894 | 132 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 133 | |
mbed_official | 579:53297373a894 | 134 | #define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */ |
mbed_official | 579:53297373a894 | 135 | #define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */ |
mbed_official | 579:53297373a894 | 136 | |
mbed_official | 579:53297373a894 | 137 | #define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */ |
mbed_official | 579:53297373a894 | 138 | #define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos) |
mbed_official | 579:53297373a894 | 139 | #define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */ |
mbed_official | 579:53297373a894 | 140 | #define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos) |
mbed_official | 579:53297373a894 | 141 | #define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */ |
mbed_official | 579:53297373a894 | 142 | #define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos) |
mbed_official | 579:53297373a894 | 143 | #define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */ |
mbed_official | 579:53297373a894 | 144 | #define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos) |
mbed_official | 579:53297373a894 | 145 | #define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */ |
mbed_official | 579:53297373a894 | 146 | #define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos) |
mbed_official | 579:53297373a894 | 147 | #define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */ |
mbed_official | 579:53297373a894 | 148 | #define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos) |
mbed_official | 579:53297373a894 | 149 | #define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */ |
mbed_official | 579:53297373a894 | 150 | #define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos) |
mbed_official | 579:53297373a894 | 151 | #define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */ |
mbed_official | 579:53297373a894 | 152 | #define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos) |
mbed_official | 579:53297373a894 | 153 | #define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */ |
mbed_official | 579:53297373a894 | 154 | #define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos) |
mbed_official | 579:53297373a894 | 155 | #define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */ |
mbed_official | 579:53297373a894 | 156 | #define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos) |
mbed_official | 579:53297373a894 | 157 | #define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */ |
mbed_official | 579:53297373a894 | 158 | #define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos) |
mbed_official | 579:53297373a894 | 159 | #define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */ |
mbed_official | 579:53297373a894 | 160 | #define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos) |
mbed_official | 579:53297373a894 | 161 | #define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */ |
mbed_official | 579:53297373a894 | 162 | #define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos) |
mbed_official | 579:53297373a894 | 163 | #define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */ |
mbed_official | 579:53297373a894 | 164 | #define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos) |
mbed_official | 579:53297373a894 | 165 | #define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */ |
mbed_official | 579:53297373a894 | 166 | #define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos) |
mbed_official | 579:53297373a894 | 167 | #define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */ |
mbed_official | 579:53297373a894 | 168 | #define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos) |
mbed_official | 579:53297373a894 | 169 | #define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */ |
mbed_official | 579:53297373a894 | 170 | #define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos) |
mbed_official | 579:53297373a894 | 171 | #define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))) |
mbed_official | 579:53297373a894 | 172 | #define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 173 | |
mbed_official | 579:53297373a894 | 174 | /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 175 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 176 | typedef union { |
mbed_official | 579:53297373a894 | 177 | struct { |
mbed_official | 579:53297373a894 | 178 | uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ |
mbed_official | 579:53297373a894 | 179 | uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ |
mbed_official | 579:53297373a894 | 180 | uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ |
mbed_official | 579:53297373a894 | 181 | uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ |
mbed_official | 579:53297373a894 | 182 | uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ |
mbed_official | 579:53297373a894 | 183 | uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ |
mbed_official | 579:53297373a894 | 184 | uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ |
mbed_official | 579:53297373a894 | 185 | uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ |
mbed_official | 579:53297373a894 | 186 | uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ |
mbed_official | 579:53297373a894 | 187 | uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ |
mbed_official | 579:53297373a894 | 188 | uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ |
mbed_official | 579:53297373a894 | 189 | uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ |
mbed_official | 579:53297373a894 | 190 | uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ |
mbed_official | 579:53297373a894 | 191 | uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ |
mbed_official | 579:53297373a894 | 192 | uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ |
mbed_official | 579:53297373a894 | 193 | uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ |
mbed_official | 579:53297373a894 | 194 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 195 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 196 | struct { |
mbed_official | 579:53297373a894 | 197 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ |
mbed_official | 579:53297373a894 | 198 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 199 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 200 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 201 | } EIC_INTENCLR_Type; |
mbed_official | 579:53297373a894 | 202 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 203 | |
mbed_official | 579:53297373a894 | 204 | #define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 205 | #define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 206 | |
mbed_official | 579:53297373a894 | 207 | #define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */ |
mbed_official | 579:53297373a894 | 208 | #define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos) |
mbed_official | 579:53297373a894 | 209 | #define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */ |
mbed_official | 579:53297373a894 | 210 | #define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos) |
mbed_official | 579:53297373a894 | 211 | #define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */ |
mbed_official | 579:53297373a894 | 212 | #define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos) |
mbed_official | 579:53297373a894 | 213 | #define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */ |
mbed_official | 579:53297373a894 | 214 | #define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos) |
mbed_official | 579:53297373a894 | 215 | #define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */ |
mbed_official | 579:53297373a894 | 216 | #define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos) |
mbed_official | 579:53297373a894 | 217 | #define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */ |
mbed_official | 579:53297373a894 | 218 | #define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos) |
mbed_official | 579:53297373a894 | 219 | #define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */ |
mbed_official | 579:53297373a894 | 220 | #define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos) |
mbed_official | 579:53297373a894 | 221 | #define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */ |
mbed_official | 579:53297373a894 | 222 | #define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos) |
mbed_official | 579:53297373a894 | 223 | #define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */ |
mbed_official | 579:53297373a894 | 224 | #define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos) |
mbed_official | 579:53297373a894 | 225 | #define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */ |
mbed_official | 579:53297373a894 | 226 | #define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos) |
mbed_official | 579:53297373a894 | 227 | #define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */ |
mbed_official | 579:53297373a894 | 228 | #define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos) |
mbed_official | 579:53297373a894 | 229 | #define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */ |
mbed_official | 579:53297373a894 | 230 | #define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos) |
mbed_official | 579:53297373a894 | 231 | #define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */ |
mbed_official | 579:53297373a894 | 232 | #define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos) |
mbed_official | 579:53297373a894 | 233 | #define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */ |
mbed_official | 579:53297373a894 | 234 | #define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos) |
mbed_official | 579:53297373a894 | 235 | #define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */ |
mbed_official | 579:53297373a894 | 236 | #define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos) |
mbed_official | 579:53297373a894 | 237 | #define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */ |
mbed_official | 579:53297373a894 | 238 | #define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos) |
mbed_official | 579:53297373a894 | 239 | #define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */ |
mbed_official | 579:53297373a894 | 240 | #define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos) |
mbed_official | 579:53297373a894 | 241 | #define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))) |
mbed_official | 579:53297373a894 | 242 | #define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 243 | |
mbed_official | 579:53297373a894 | 244 | /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 245 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 246 | typedef union { |
mbed_official | 579:53297373a894 | 247 | struct { |
mbed_official | 579:53297373a894 | 248 | uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ |
mbed_official | 579:53297373a894 | 249 | uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ |
mbed_official | 579:53297373a894 | 250 | uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ |
mbed_official | 579:53297373a894 | 251 | uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ |
mbed_official | 579:53297373a894 | 252 | uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ |
mbed_official | 579:53297373a894 | 253 | uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ |
mbed_official | 579:53297373a894 | 254 | uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ |
mbed_official | 579:53297373a894 | 255 | uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ |
mbed_official | 579:53297373a894 | 256 | uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ |
mbed_official | 579:53297373a894 | 257 | uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ |
mbed_official | 579:53297373a894 | 258 | uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ |
mbed_official | 579:53297373a894 | 259 | uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ |
mbed_official | 579:53297373a894 | 260 | uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ |
mbed_official | 579:53297373a894 | 261 | uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ |
mbed_official | 579:53297373a894 | 262 | uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ |
mbed_official | 579:53297373a894 | 263 | uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ |
mbed_official | 579:53297373a894 | 264 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 265 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 266 | struct { |
mbed_official | 579:53297373a894 | 267 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ |
mbed_official | 579:53297373a894 | 268 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 269 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 270 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 271 | } EIC_INTENSET_Type; |
mbed_official | 579:53297373a894 | 272 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 273 | |
mbed_official | 579:53297373a894 | 274 | #define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 275 | #define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 276 | |
mbed_official | 579:53297373a894 | 277 | #define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */ |
mbed_official | 579:53297373a894 | 278 | #define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos) |
mbed_official | 579:53297373a894 | 279 | #define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */ |
mbed_official | 579:53297373a894 | 280 | #define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos) |
mbed_official | 579:53297373a894 | 281 | #define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */ |
mbed_official | 579:53297373a894 | 282 | #define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos) |
mbed_official | 579:53297373a894 | 283 | #define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */ |
mbed_official | 579:53297373a894 | 284 | #define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos) |
mbed_official | 579:53297373a894 | 285 | #define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */ |
mbed_official | 579:53297373a894 | 286 | #define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos) |
mbed_official | 579:53297373a894 | 287 | #define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */ |
mbed_official | 579:53297373a894 | 288 | #define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos) |
mbed_official | 579:53297373a894 | 289 | #define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */ |
mbed_official | 579:53297373a894 | 290 | #define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos) |
mbed_official | 579:53297373a894 | 291 | #define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */ |
mbed_official | 579:53297373a894 | 292 | #define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos) |
mbed_official | 579:53297373a894 | 293 | #define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */ |
mbed_official | 579:53297373a894 | 294 | #define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos) |
mbed_official | 579:53297373a894 | 295 | #define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */ |
mbed_official | 579:53297373a894 | 296 | #define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos) |
mbed_official | 579:53297373a894 | 297 | #define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */ |
mbed_official | 579:53297373a894 | 298 | #define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos) |
mbed_official | 579:53297373a894 | 299 | #define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */ |
mbed_official | 579:53297373a894 | 300 | #define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos) |
mbed_official | 579:53297373a894 | 301 | #define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */ |
mbed_official | 579:53297373a894 | 302 | #define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos) |
mbed_official | 579:53297373a894 | 303 | #define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */ |
mbed_official | 579:53297373a894 | 304 | #define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos) |
mbed_official | 579:53297373a894 | 305 | #define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */ |
mbed_official | 579:53297373a894 | 306 | #define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos) |
mbed_official | 579:53297373a894 | 307 | #define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */ |
mbed_official | 579:53297373a894 | 308 | #define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos) |
mbed_official | 579:53297373a894 | 309 | #define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */ |
mbed_official | 579:53297373a894 | 310 | #define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos) |
mbed_official | 579:53297373a894 | 311 | #define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))) |
mbed_official | 579:53297373a894 | 312 | #define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 313 | |
mbed_official | 579:53297373a894 | 314 | /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 315 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 316 | typedef union { |
mbed_official | 579:53297373a894 | 317 | struct { |
mbed_official | 579:53297373a894 | 318 | uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ |
mbed_official | 579:53297373a894 | 319 | uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ |
mbed_official | 579:53297373a894 | 320 | uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ |
mbed_official | 579:53297373a894 | 321 | uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ |
mbed_official | 579:53297373a894 | 322 | uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ |
mbed_official | 579:53297373a894 | 323 | uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ |
mbed_official | 579:53297373a894 | 324 | uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ |
mbed_official | 579:53297373a894 | 325 | uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ |
mbed_official | 579:53297373a894 | 326 | uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ |
mbed_official | 579:53297373a894 | 327 | uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ |
mbed_official | 579:53297373a894 | 328 | uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ |
mbed_official | 579:53297373a894 | 329 | uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ |
mbed_official | 579:53297373a894 | 330 | uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ |
mbed_official | 579:53297373a894 | 331 | uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ |
mbed_official | 579:53297373a894 | 332 | uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ |
mbed_official | 579:53297373a894 | 333 | uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ |
mbed_official | 579:53297373a894 | 334 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 335 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 336 | struct { |
mbed_official | 579:53297373a894 | 337 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ |
mbed_official | 579:53297373a894 | 338 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 339 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 340 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 341 | } EIC_INTFLAG_Type; |
mbed_official | 579:53297373a894 | 342 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 343 | |
mbed_official | 579:53297373a894 | 344 | #define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 345 | #define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 346 | |
mbed_official | 579:53297373a894 | 347 | #define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */ |
mbed_official | 579:53297373a894 | 348 | #define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos) |
mbed_official | 579:53297373a894 | 349 | #define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */ |
mbed_official | 579:53297373a894 | 350 | #define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos) |
mbed_official | 579:53297373a894 | 351 | #define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */ |
mbed_official | 579:53297373a894 | 352 | #define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos) |
mbed_official | 579:53297373a894 | 353 | #define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */ |
mbed_official | 579:53297373a894 | 354 | #define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos) |
mbed_official | 579:53297373a894 | 355 | #define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */ |
mbed_official | 579:53297373a894 | 356 | #define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos) |
mbed_official | 579:53297373a894 | 357 | #define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */ |
mbed_official | 579:53297373a894 | 358 | #define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos) |
mbed_official | 579:53297373a894 | 359 | #define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */ |
mbed_official | 579:53297373a894 | 360 | #define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos) |
mbed_official | 579:53297373a894 | 361 | #define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */ |
mbed_official | 579:53297373a894 | 362 | #define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos) |
mbed_official | 579:53297373a894 | 363 | #define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */ |
mbed_official | 579:53297373a894 | 364 | #define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos) |
mbed_official | 579:53297373a894 | 365 | #define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */ |
mbed_official | 579:53297373a894 | 366 | #define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos) |
mbed_official | 579:53297373a894 | 367 | #define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */ |
mbed_official | 579:53297373a894 | 368 | #define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos) |
mbed_official | 579:53297373a894 | 369 | #define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */ |
mbed_official | 579:53297373a894 | 370 | #define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos) |
mbed_official | 579:53297373a894 | 371 | #define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */ |
mbed_official | 579:53297373a894 | 372 | #define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos) |
mbed_official | 579:53297373a894 | 373 | #define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */ |
mbed_official | 579:53297373a894 | 374 | #define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos) |
mbed_official | 579:53297373a894 | 375 | #define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */ |
mbed_official | 579:53297373a894 | 376 | #define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos) |
mbed_official | 579:53297373a894 | 377 | #define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */ |
mbed_official | 579:53297373a894 | 378 | #define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos) |
mbed_official | 579:53297373a894 | 379 | #define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */ |
mbed_official | 579:53297373a894 | 380 | #define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos) |
mbed_official | 579:53297373a894 | 381 | #define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))) |
mbed_official | 579:53297373a894 | 382 | #define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 383 | |
mbed_official | 579:53297373a894 | 384 | /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */ |
mbed_official | 579:53297373a894 | 385 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 386 | typedef union { |
mbed_official | 579:53297373a894 | 387 | struct { |
mbed_official | 579:53297373a894 | 388 | uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 389 | uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 390 | uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 391 | uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 392 | uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 393 | uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 394 | uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 395 | uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 396 | uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 397 | uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 398 | uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 399 | uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 400 | uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 401 | uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 402 | uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 403 | uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 404 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 405 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 406 | struct { |
mbed_official | 579:53297373a894 | 407 | uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ |
mbed_official | 579:53297373a894 | 408 | uint32_t :16; /*!< bit: 16..31 Reserved */ |
mbed_official | 579:53297373a894 | 409 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 410 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 411 | } EIC_WAKEUP_Type; |
mbed_official | 579:53297373a894 | 412 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 413 | |
mbed_official | 579:53297373a894 | 414 | #define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */ |
mbed_official | 579:53297373a894 | 415 | #define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */ |
mbed_official | 579:53297373a894 | 416 | |
mbed_official | 579:53297373a894 | 417 | #define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 418 | #define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos) |
mbed_official | 579:53297373a894 | 419 | #define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 420 | #define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos) |
mbed_official | 579:53297373a894 | 421 | #define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 422 | #define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos) |
mbed_official | 579:53297373a894 | 423 | #define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 424 | #define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos) |
mbed_official | 579:53297373a894 | 425 | #define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 426 | #define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos) |
mbed_official | 579:53297373a894 | 427 | #define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 428 | #define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos) |
mbed_official | 579:53297373a894 | 429 | #define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 430 | #define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos) |
mbed_official | 579:53297373a894 | 431 | #define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 432 | #define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos) |
mbed_official | 579:53297373a894 | 433 | #define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 434 | #define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos) |
mbed_official | 579:53297373a894 | 435 | #define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 436 | #define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos) |
mbed_official | 579:53297373a894 | 437 | #define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 438 | #define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos) |
mbed_official | 579:53297373a894 | 439 | #define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 440 | #define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos) |
mbed_official | 579:53297373a894 | 441 | #define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 442 | #define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos) |
mbed_official | 579:53297373a894 | 443 | #define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 444 | #define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos) |
mbed_official | 579:53297373a894 | 445 | #define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 446 | #define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos) |
mbed_official | 579:53297373a894 | 447 | #define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */ |
mbed_official | 579:53297373a894 | 448 | #define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos) |
mbed_official | 579:53297373a894 | 449 | #define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */ |
mbed_official | 579:53297373a894 | 450 | #define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos) |
mbed_official | 579:53297373a894 | 451 | #define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))) |
mbed_official | 579:53297373a894 | 452 | #define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */ |
mbed_official | 579:53297373a894 | 453 | |
mbed_official | 579:53297373a894 | 454 | /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */ |
mbed_official | 579:53297373a894 | 455 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 456 | typedef union { |
mbed_official | 579:53297373a894 | 457 | struct { |
mbed_official | 579:53297373a894 | 458 | uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ |
mbed_official | 579:53297373a894 | 459 | uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ |
mbed_official | 579:53297373a894 | 460 | uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ |
mbed_official | 579:53297373a894 | 461 | uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ |
mbed_official | 579:53297373a894 | 462 | uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ |
mbed_official | 579:53297373a894 | 463 | uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ |
mbed_official | 579:53297373a894 | 464 | uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ |
mbed_official | 579:53297373a894 | 465 | uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ |
mbed_official | 579:53297373a894 | 466 | uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ |
mbed_official | 579:53297373a894 | 467 | uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ |
mbed_official | 579:53297373a894 | 468 | uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ |
mbed_official | 579:53297373a894 | 469 | uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ |
mbed_official | 579:53297373a894 | 470 | uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ |
mbed_official | 579:53297373a894 | 471 | uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ |
mbed_official | 579:53297373a894 | 472 | uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ |
mbed_official | 579:53297373a894 | 473 | uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ |
mbed_official | 579:53297373a894 | 474 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 475 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 476 | } EIC_CONFIG_Type; |
mbed_official | 579:53297373a894 | 477 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 478 | |
mbed_official | 579:53297373a894 | 479 | #define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */ |
mbed_official | 579:53297373a894 | 480 | #define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */ |
mbed_official | 579:53297373a894 | 481 | |
mbed_official | 579:53297373a894 | 482 | #define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */ |
mbed_official | 579:53297373a894 | 483 | #define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos) |
mbed_official | 579:53297373a894 | 484 | #define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))) |
mbed_official | 579:53297373a894 | 485 | #define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 486 | #define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */ |
mbed_official | 579:53297373a894 | 487 | #define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */ |
mbed_official | 579:53297373a894 | 488 | #define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */ |
mbed_official | 579:53297373a894 | 489 | #define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */ |
mbed_official | 579:53297373a894 | 490 | #define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */ |
mbed_official | 579:53297373a894 | 491 | #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) |
mbed_official | 579:53297373a894 | 492 | #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) |
mbed_official | 579:53297373a894 | 493 | #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) |
mbed_official | 579:53297373a894 | 494 | #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) |
mbed_official | 579:53297373a894 | 495 | #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) |
mbed_official | 579:53297373a894 | 496 | #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) |
mbed_official | 579:53297373a894 | 497 | #define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */ |
mbed_official | 579:53297373a894 | 498 | #define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos) |
mbed_official | 579:53297373a894 | 499 | #define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */ |
mbed_official | 579:53297373a894 | 500 | #define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos) |
mbed_official | 579:53297373a894 | 501 | #define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))) |
mbed_official | 579:53297373a894 | 502 | #define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 503 | #define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ |
mbed_official | 579:53297373a894 | 504 | #define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ |
mbed_official | 579:53297373a894 | 505 | #define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ |
mbed_official | 579:53297373a894 | 506 | #define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ |
mbed_official | 579:53297373a894 | 507 | #define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ |
mbed_official | 579:53297373a894 | 508 | #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) |
mbed_official | 579:53297373a894 | 509 | #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) |
mbed_official | 579:53297373a894 | 510 | #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) |
mbed_official | 579:53297373a894 | 511 | #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) |
mbed_official | 579:53297373a894 | 512 | #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) |
mbed_official | 579:53297373a894 | 513 | #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) |
mbed_official | 579:53297373a894 | 514 | #define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */ |
mbed_official | 579:53297373a894 | 515 | #define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos) |
mbed_official | 579:53297373a894 | 516 | #define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */ |
mbed_official | 579:53297373a894 | 517 | #define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos) |
mbed_official | 579:53297373a894 | 518 | #define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))) |
mbed_official | 579:53297373a894 | 519 | #define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 520 | #define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ |
mbed_official | 579:53297373a894 | 521 | #define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ |
mbed_official | 579:53297373a894 | 522 | #define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ |
mbed_official | 579:53297373a894 | 523 | #define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ |
mbed_official | 579:53297373a894 | 524 | #define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ |
mbed_official | 579:53297373a894 | 525 | #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) |
mbed_official | 579:53297373a894 | 526 | #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) |
mbed_official | 579:53297373a894 | 527 | #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) |
mbed_official | 579:53297373a894 | 528 | #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) |
mbed_official | 579:53297373a894 | 529 | #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) |
mbed_official | 579:53297373a894 | 530 | #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) |
mbed_official | 579:53297373a894 | 531 | #define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */ |
mbed_official | 579:53297373a894 | 532 | #define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos) |
mbed_official | 579:53297373a894 | 533 | #define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */ |
mbed_official | 579:53297373a894 | 534 | #define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos) |
mbed_official | 579:53297373a894 | 535 | #define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))) |
mbed_official | 579:53297373a894 | 536 | #define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 537 | #define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ |
mbed_official | 579:53297373a894 | 538 | #define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ |
mbed_official | 579:53297373a894 | 539 | #define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ |
mbed_official | 579:53297373a894 | 540 | #define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ |
mbed_official | 579:53297373a894 | 541 | #define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ |
mbed_official | 579:53297373a894 | 542 | #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) |
mbed_official | 579:53297373a894 | 543 | #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) |
mbed_official | 579:53297373a894 | 544 | #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) |
mbed_official | 579:53297373a894 | 545 | #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) |
mbed_official | 579:53297373a894 | 546 | #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) |
mbed_official | 579:53297373a894 | 547 | #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) |
mbed_official | 579:53297373a894 | 548 | #define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */ |
mbed_official | 579:53297373a894 | 549 | #define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos) |
mbed_official | 579:53297373a894 | 550 | #define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */ |
mbed_official | 579:53297373a894 | 551 | #define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos) |
mbed_official | 579:53297373a894 | 552 | #define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))) |
mbed_official | 579:53297373a894 | 553 | #define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 554 | #define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ |
mbed_official | 579:53297373a894 | 555 | #define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ |
mbed_official | 579:53297373a894 | 556 | #define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ |
mbed_official | 579:53297373a894 | 557 | #define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ |
mbed_official | 579:53297373a894 | 558 | #define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ |
mbed_official | 579:53297373a894 | 559 | #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) |
mbed_official | 579:53297373a894 | 560 | #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) |
mbed_official | 579:53297373a894 | 561 | #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) |
mbed_official | 579:53297373a894 | 562 | #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) |
mbed_official | 579:53297373a894 | 563 | #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) |
mbed_official | 579:53297373a894 | 564 | #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) |
mbed_official | 579:53297373a894 | 565 | #define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */ |
mbed_official | 579:53297373a894 | 566 | #define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos) |
mbed_official | 579:53297373a894 | 567 | #define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */ |
mbed_official | 579:53297373a894 | 568 | #define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos) |
mbed_official | 579:53297373a894 | 569 | #define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))) |
mbed_official | 579:53297373a894 | 570 | #define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 571 | #define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ |
mbed_official | 579:53297373a894 | 572 | #define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ |
mbed_official | 579:53297373a894 | 573 | #define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ |
mbed_official | 579:53297373a894 | 574 | #define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ |
mbed_official | 579:53297373a894 | 575 | #define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ |
mbed_official | 579:53297373a894 | 576 | #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) |
mbed_official | 579:53297373a894 | 577 | #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) |
mbed_official | 579:53297373a894 | 578 | #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) |
mbed_official | 579:53297373a894 | 579 | #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) |
mbed_official | 579:53297373a894 | 580 | #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) |
mbed_official | 579:53297373a894 | 581 | #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) |
mbed_official | 579:53297373a894 | 582 | #define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */ |
mbed_official | 579:53297373a894 | 583 | #define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos) |
mbed_official | 579:53297373a894 | 584 | #define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */ |
mbed_official | 579:53297373a894 | 585 | #define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos) |
mbed_official | 579:53297373a894 | 586 | #define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))) |
mbed_official | 579:53297373a894 | 587 | #define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 588 | #define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ |
mbed_official | 579:53297373a894 | 589 | #define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ |
mbed_official | 579:53297373a894 | 590 | #define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ |
mbed_official | 579:53297373a894 | 591 | #define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ |
mbed_official | 579:53297373a894 | 592 | #define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ |
mbed_official | 579:53297373a894 | 593 | #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) |
mbed_official | 579:53297373a894 | 594 | #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) |
mbed_official | 579:53297373a894 | 595 | #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) |
mbed_official | 579:53297373a894 | 596 | #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) |
mbed_official | 579:53297373a894 | 597 | #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) |
mbed_official | 579:53297373a894 | 598 | #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) |
mbed_official | 579:53297373a894 | 599 | #define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */ |
mbed_official | 579:53297373a894 | 600 | #define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos) |
mbed_official | 579:53297373a894 | 601 | #define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */ |
mbed_official | 579:53297373a894 | 602 | #define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos) |
mbed_official | 579:53297373a894 | 603 | #define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))) |
mbed_official | 579:53297373a894 | 604 | #define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */ |
mbed_official | 579:53297373a894 | 605 | #define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */ |
mbed_official | 579:53297373a894 | 606 | #define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */ |
mbed_official | 579:53297373a894 | 607 | #define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */ |
mbed_official | 579:53297373a894 | 608 | #define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */ |
mbed_official | 579:53297373a894 | 609 | #define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */ |
mbed_official | 579:53297373a894 | 610 | #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) |
mbed_official | 579:53297373a894 | 611 | #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) |
mbed_official | 579:53297373a894 | 612 | #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) |
mbed_official | 579:53297373a894 | 613 | #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) |
mbed_official | 579:53297373a894 | 614 | #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) |
mbed_official | 579:53297373a894 | 615 | #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) |
mbed_official | 579:53297373a894 | 616 | #define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */ |
mbed_official | 579:53297373a894 | 617 | #define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos) |
mbed_official | 579:53297373a894 | 618 | #define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */ |
mbed_official | 579:53297373a894 | 619 | |
mbed_official | 579:53297373a894 | 620 | /** \brief EIC hardware registers */ |
mbed_official | 579:53297373a894 | 621 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 622 | typedef struct { |
mbed_official | 579:53297373a894 | 623 | __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ |
mbed_official | 579:53297373a894 | 624 | __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ |
mbed_official | 579:53297373a894 | 625 | __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ |
mbed_official | 579:53297373a894 | 626 | __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 627 | __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ |
mbed_official | 579:53297373a894 | 628 | __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 629 | __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 630 | __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 631 | __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ |
mbed_official | 579:53297373a894 | 632 | __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ |
mbed_official | 579:53297373a894 | 633 | } Eic; |
mbed_official | 579:53297373a894 | 634 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 635 | |
mbed_official | 579:53297373a894 | 636 | /*@}*/ |
mbed_official | 579:53297373a894 | 637 | |
mbed_official | 579:53297373a894 | 638 | #endif /* _SAMD21_EIC_COMPONENT_ */ |