marcus chiou
mbed library sources
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_tc.h@579:53297373a894, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Revision:
- 579:53297373a894
- Child:
- 592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | /** |
| mbed_official | 579:53297373a894 | 2 | * \file |
| mbed_official | 579:53297373a894 | 3 | * |
| mbed_official | 579:53297373a894 | 4 | * \brief Component description for TC |
| mbed_official | 579:53297373a894 | 5 | * |
| mbed_official | 579:53297373a894 | 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved. |
| mbed_official | 579:53297373a894 | 7 | * |
| mbed_official | 579:53297373a894 | 8 | * \asf_license_start |
| mbed_official | 579:53297373a894 | 9 | * |
| mbed_official | 579:53297373a894 | 10 | * \page License |
| mbed_official | 579:53297373a894 | 11 | * |
| mbed_official | 579:53297373a894 | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 579:53297373a894 | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 579:53297373a894 | 14 | * |
| mbed_official | 579:53297373a894 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 579:53297373a894 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 579:53297373a894 | 17 | * |
| mbed_official | 579:53297373a894 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 579:53297373a894 | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 579:53297373a894 | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 579:53297373a894 | 21 | * |
| mbed_official | 579:53297373a894 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| mbed_official | 579:53297373a894 | 23 | * from this software without specific prior written permission. |
| mbed_official | 579:53297373a894 | 24 | * |
| mbed_official | 579:53297373a894 | 25 | * 4. This software may only be redistributed and used in connection with an |
| mbed_official | 579:53297373a894 | 26 | * Atmel microcontroller product. |
| mbed_official | 579:53297373a894 | 27 | * |
| mbed_official | 579:53297373a894 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| mbed_official | 579:53297373a894 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| mbed_official | 579:53297373a894 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| mbed_official | 579:53297373a894 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| mbed_official | 579:53297373a894 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 579:53297373a894 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| mbed_official | 579:53297373a894 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| mbed_official | 579:53297373a894 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| mbed_official | 579:53297373a894 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| mbed_official | 579:53297373a894 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| mbed_official | 579:53297373a894 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 579:53297373a894 | 39 | * |
| mbed_official | 579:53297373a894 | 40 | * \asf_license_stop |
| mbed_official | 579:53297373a894 | 41 | * |
| mbed_official | 579:53297373a894 | 42 | */ |
| mbed_official | 579:53297373a894 | 43 | /** |
| mbed_official | 579:53297373a894 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
| mbed_official | 579:53297373a894 | 45 | */ |
| mbed_official | 579:53297373a894 | 46 | |
| mbed_official | 579:53297373a894 | 47 | #ifndef _SAMD21_TC_COMPONENT_ |
| mbed_official | 579:53297373a894 | 48 | #define _SAMD21_TC_COMPONENT_ |
| mbed_official | 579:53297373a894 | 49 | |
| mbed_official | 579:53297373a894 | 50 | /* ========================================================================== */ |
| mbed_official | 579:53297373a894 | 51 | /** SOFTWARE API DEFINITION FOR TC */ |
| mbed_official | 579:53297373a894 | 52 | /* ========================================================================== */ |
| mbed_official | 579:53297373a894 | 53 | /** \addtogroup SAMD21_TC Basic Timer Counter */ |
| mbed_official | 579:53297373a894 | 54 | /*@{*/ |
| mbed_official | 579:53297373a894 | 55 | |
| mbed_official | 579:53297373a894 | 56 | #define TC_U2212 |
| mbed_official | 579:53297373a894 | 57 | #define REV_TC 0x121 |
| mbed_official | 579:53297373a894 | 58 | |
| mbed_official | 579:53297373a894 | 59 | /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ |
| mbed_official | 579:53297373a894 | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 61 | typedef union { |
| mbed_official | 579:53297373a894 | 62 | struct { |
| mbed_official | 579:53297373a894 | 63 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */ |
| mbed_official | 579:53297373a894 | 64 | uint16_t ENABLE:1; /*!< bit: 1 Enable */ |
| mbed_official | 579:53297373a894 | 65 | uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ |
| mbed_official | 579:53297373a894 | 66 | uint16_t :1; /*!< bit: 4 Reserved */ |
| mbed_official | 579:53297373a894 | 67 | uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ |
| mbed_official | 579:53297373a894 | 68 | uint16_t :1; /*!< bit: 7 Reserved */ |
| mbed_official | 579:53297373a894 | 69 | uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ |
| mbed_official | 579:53297373a894 | 70 | uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ |
| mbed_official | 579:53297373a894 | 71 | uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ |
| mbed_official | 579:53297373a894 | 72 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
| mbed_official | 579:53297373a894 | 73 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 74 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 75 | } TC_CTRLA_Type; |
| mbed_official | 579:53297373a894 | 76 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 77 | |
| mbed_official | 579:53297373a894 | 78 | #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ |
| mbed_official | 579:53297373a894 | 79 | #define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */ |
| mbed_official | 579:53297373a894 | 80 | |
| mbed_official | 579:53297373a894 | 81 | #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ |
| mbed_official | 579:53297373a894 | 82 | #define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos) |
| mbed_official | 579:53297373a894 | 83 | #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ |
| mbed_official | 579:53297373a894 | 84 | #define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) |
| mbed_official | 579:53297373a894 | 85 | #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */ |
| mbed_official | 579:53297373a894 | 86 | #define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos) |
| mbed_official | 579:53297373a894 | 87 | #define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))) |
| mbed_official | 579:53297373a894 | 88 | #define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */ |
| mbed_official | 579:53297373a894 | 89 | #define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */ |
| mbed_official | 579:53297373a894 | 90 | #define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */ |
| mbed_official | 579:53297373a894 | 91 | #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) |
| mbed_official | 579:53297373a894 | 92 | #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) |
| mbed_official | 579:53297373a894 | 93 | #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) |
| mbed_official | 579:53297373a894 | 94 | #define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */ |
| mbed_official | 579:53297373a894 | 95 | #define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos) |
| mbed_official | 579:53297373a894 | 96 | #define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))) |
| mbed_official | 579:53297373a894 | 97 | #define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */ |
| mbed_official | 579:53297373a894 | 98 | #define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */ |
| mbed_official | 579:53297373a894 | 99 | #define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */ |
| mbed_official | 579:53297373a894 | 100 | #define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */ |
| mbed_official | 579:53297373a894 | 101 | #define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos) |
| mbed_official | 579:53297373a894 | 102 | #define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos) |
| mbed_official | 579:53297373a894 | 103 | #define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos) |
| mbed_official | 579:53297373a894 | 104 | #define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos) |
| mbed_official | 579:53297373a894 | 105 | #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ |
| mbed_official | 579:53297373a894 | 106 | #define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 107 | #define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))) |
| mbed_official | 579:53297373a894 | 108 | #define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ |
| mbed_official | 579:53297373a894 | 109 | #define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ |
| mbed_official | 579:53297373a894 | 110 | #define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ |
| mbed_official | 579:53297373a894 | 111 | #define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ |
| mbed_official | 579:53297373a894 | 112 | #define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ |
| mbed_official | 579:53297373a894 | 113 | #define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ |
| mbed_official | 579:53297373a894 | 114 | #define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ |
| mbed_official | 579:53297373a894 | 115 | #define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ |
| mbed_official | 579:53297373a894 | 116 | #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 117 | #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 118 | #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 119 | #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 120 | #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 121 | #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 122 | #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 123 | #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 124 | #define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */ |
| mbed_official | 579:53297373a894 | 125 | #define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos) |
| mbed_official | 579:53297373a894 | 126 | #define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ |
| mbed_official | 579:53297373a894 | 127 | #define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos) |
| mbed_official | 579:53297373a894 | 128 | #define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))) |
| mbed_official | 579:53297373a894 | 129 | #define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ |
| mbed_official | 579:53297373a894 | 130 | #define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ |
| mbed_official | 579:53297373a894 | 131 | #define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */ |
| mbed_official | 579:53297373a894 | 132 | #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) |
| mbed_official | 579:53297373a894 | 133 | #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) |
| mbed_official | 579:53297373a894 | 134 | #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) |
| mbed_official | 579:53297373a894 | 135 | #define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */ |
| mbed_official | 579:53297373a894 | 136 | |
| mbed_official | 579:53297373a894 | 137 | /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ |
| mbed_official | 579:53297373a894 | 138 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 139 | typedef union { |
| mbed_official | 579:53297373a894 | 140 | struct { |
| mbed_official | 579:53297373a894 | 141 | uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ |
| mbed_official | 579:53297373a894 | 142 | uint16_t :9; /*!< bit: 5..13 Reserved */ |
| mbed_official | 579:53297373a894 | 143 | uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ |
| mbed_official | 579:53297373a894 | 144 | uint16_t RREQ:1; /*!< bit: 15 Read Request */ |
| mbed_official | 579:53297373a894 | 145 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 146 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 147 | } TC_READREQ_Type; |
| mbed_official | 579:53297373a894 | 148 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 149 | |
| mbed_official | 579:53297373a894 | 150 | #define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */ |
| mbed_official | 579:53297373a894 | 151 | #define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */ |
| mbed_official | 579:53297373a894 | 152 | |
| mbed_official | 579:53297373a894 | 153 | #define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */ |
| mbed_official | 579:53297373a894 | 154 | #define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos) |
| mbed_official | 579:53297373a894 | 155 | #define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))) |
| mbed_official | 579:53297373a894 | 156 | #define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */ |
| mbed_official | 579:53297373a894 | 157 | #define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos) |
| mbed_official | 579:53297373a894 | 158 | #define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */ |
| mbed_official | 579:53297373a894 | 159 | #define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos) |
| mbed_official | 579:53297373a894 | 160 | #define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */ |
| mbed_official | 579:53297373a894 | 161 | |
| mbed_official | 579:53297373a894 | 162 | /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ |
| mbed_official | 579:53297373a894 | 163 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 164 | typedef union { |
| mbed_official | 579:53297373a894 | 165 | struct { |
| mbed_official | 579:53297373a894 | 166 | uint8_t DIR:1; /*!< bit: 0 Counter Direction */ |
| mbed_official | 579:53297373a894 | 167 | uint8_t :1; /*!< bit: 1 Reserved */ |
| mbed_official | 579:53297373a894 | 168 | uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ |
| mbed_official | 579:53297373a894 | 169 | uint8_t :3; /*!< bit: 3.. 5 Reserved */ |
| mbed_official | 579:53297373a894 | 170 | uint8_t CMD:2; /*!< bit: 6.. 7 Command */ |
| mbed_official | 579:53297373a894 | 171 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 172 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 173 | } TC_CTRLBCLR_Type; |
| mbed_official | 579:53297373a894 | 174 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 175 | |
| mbed_official | 579:53297373a894 | 176 | #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ |
| mbed_official | 579:53297373a894 | 177 | #define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ |
| mbed_official | 579:53297373a894 | 178 | |
| mbed_official | 579:53297373a894 | 179 | #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ |
| mbed_official | 579:53297373a894 | 180 | #define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos) |
| mbed_official | 579:53297373a894 | 181 | #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */ |
| mbed_official | 579:53297373a894 | 182 | #define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos) |
| mbed_official | 579:53297373a894 | 183 | #define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */ |
| mbed_official | 579:53297373a894 | 184 | #define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos) |
| mbed_official | 579:53297373a894 | 185 | #define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))) |
| mbed_official | 579:53297373a894 | 186 | #define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */ |
| mbed_official | 579:53297373a894 | 187 | #define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ |
| mbed_official | 579:53297373a894 | 188 | #define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */ |
| mbed_official | 579:53297373a894 | 189 | #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) |
| mbed_official | 579:53297373a894 | 190 | #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) |
| mbed_official | 579:53297373a894 | 191 | #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) |
| mbed_official | 579:53297373a894 | 192 | #define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */ |
| mbed_official | 579:53297373a894 | 193 | |
| mbed_official | 579:53297373a894 | 194 | /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ |
| mbed_official | 579:53297373a894 | 195 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 196 | typedef union { |
| mbed_official | 579:53297373a894 | 197 | struct { |
| mbed_official | 579:53297373a894 | 198 | uint8_t DIR:1; /*!< bit: 0 Counter Direction */ |
| mbed_official | 579:53297373a894 | 199 | uint8_t :1; /*!< bit: 1 Reserved */ |
| mbed_official | 579:53297373a894 | 200 | uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ |
| mbed_official | 579:53297373a894 | 201 | uint8_t :3; /*!< bit: 3.. 5 Reserved */ |
| mbed_official | 579:53297373a894 | 202 | uint8_t CMD:2; /*!< bit: 6.. 7 Command */ |
| mbed_official | 579:53297373a894 | 203 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 204 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 205 | } TC_CTRLBSET_Type; |
| mbed_official | 579:53297373a894 | 206 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 207 | |
| mbed_official | 579:53297373a894 | 208 | #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ |
| mbed_official | 579:53297373a894 | 209 | #define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */ |
| mbed_official | 579:53297373a894 | 210 | |
| mbed_official | 579:53297373a894 | 211 | #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ |
| mbed_official | 579:53297373a894 | 212 | #define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos) |
| mbed_official | 579:53297373a894 | 213 | #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */ |
| mbed_official | 579:53297373a894 | 214 | #define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos) |
| mbed_official | 579:53297373a894 | 215 | #define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */ |
| mbed_official | 579:53297373a894 | 216 | #define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos) |
| mbed_official | 579:53297373a894 | 217 | #define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))) |
| mbed_official | 579:53297373a894 | 218 | #define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */ |
| mbed_official | 579:53297373a894 | 219 | #define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ |
| mbed_official | 579:53297373a894 | 220 | #define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */ |
| mbed_official | 579:53297373a894 | 221 | #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) |
| mbed_official | 579:53297373a894 | 222 | #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) |
| mbed_official | 579:53297373a894 | 223 | #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) |
| mbed_official | 579:53297373a894 | 224 | #define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */ |
| mbed_official | 579:53297373a894 | 225 | |
| mbed_official | 579:53297373a894 | 226 | /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ |
| mbed_official | 579:53297373a894 | 227 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 228 | typedef union { |
| mbed_official | 579:53297373a894 | 229 | struct { |
| mbed_official | 579:53297373a894 | 230 | uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ |
| mbed_official | 579:53297373a894 | 231 | uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ |
| mbed_official | 579:53297373a894 | 232 | uint8_t :2; /*!< bit: 2.. 3 Reserved */ |
| mbed_official | 579:53297373a894 | 233 | uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ |
| mbed_official | 579:53297373a894 | 234 | uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ |
| mbed_official | 579:53297373a894 | 235 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 236 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 237 | struct { |
| mbed_official | 579:53297373a894 | 238 | uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ |
| mbed_official | 579:53297373a894 | 239 | uint8_t :2; /*!< bit: 2.. 3 Reserved */ |
| mbed_official | 579:53297373a894 | 240 | uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ |
| mbed_official | 579:53297373a894 | 241 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 242 | } vec; /*!< Structure used for vec access */ |
| mbed_official | 579:53297373a894 | 243 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 244 | } TC_CTRLC_Type; |
| mbed_official | 579:53297373a894 | 245 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 246 | |
| mbed_official | 579:53297373a894 | 247 | #define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */ |
| mbed_official | 579:53297373a894 | 248 | #define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */ |
| mbed_official | 579:53297373a894 | 249 | |
| mbed_official | 579:53297373a894 | 250 | #define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */ |
| mbed_official | 579:53297373a894 | 251 | #define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos) |
| mbed_official | 579:53297373a894 | 252 | #define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */ |
| mbed_official | 579:53297373a894 | 253 | #define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos) |
| mbed_official | 579:53297373a894 | 254 | #define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */ |
| mbed_official | 579:53297373a894 | 255 | #define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos) |
| mbed_official | 579:53297373a894 | 256 | #define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))) |
| mbed_official | 579:53297373a894 | 257 | #define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */ |
| mbed_official | 579:53297373a894 | 258 | #define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos) |
| mbed_official | 579:53297373a894 | 259 | #define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */ |
| mbed_official | 579:53297373a894 | 260 | #define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos) |
| mbed_official | 579:53297373a894 | 261 | #define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */ |
| mbed_official | 579:53297373a894 | 262 | #define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos) |
| mbed_official | 579:53297373a894 | 263 | #define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))) |
| mbed_official | 579:53297373a894 | 264 | #define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */ |
| mbed_official | 579:53297373a894 | 265 | |
| mbed_official | 579:53297373a894 | 266 | /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ |
| mbed_official | 579:53297373a894 | 267 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 268 | typedef union { |
| mbed_official | 579:53297373a894 | 269 | struct { |
| mbed_official | 579:53297373a894 | 270 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ |
| mbed_official | 579:53297373a894 | 271 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 272 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 273 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 274 | } TC_DBGCTRL_Type; |
| mbed_official | 579:53297373a894 | 275 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 276 | |
| mbed_official | 579:53297373a894 | 277 | #define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */ |
| mbed_official | 579:53297373a894 | 278 | #define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */ |
| mbed_official | 579:53297373a894 | 279 | |
| mbed_official | 579:53297373a894 | 280 | #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */ |
| mbed_official | 579:53297373a894 | 281 | #define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos) |
| mbed_official | 579:53297373a894 | 282 | #define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 283 | |
| mbed_official | 579:53297373a894 | 284 | /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ |
| mbed_official | 579:53297373a894 | 285 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 286 | typedef union { |
| mbed_official | 579:53297373a894 | 287 | struct { |
| mbed_official | 579:53297373a894 | 288 | uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ |
| mbed_official | 579:53297373a894 | 289 | uint16_t :1; /*!< bit: 3 Reserved */ |
| mbed_official | 579:53297373a894 | 290 | uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ |
| mbed_official | 579:53297373a894 | 291 | uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ |
| mbed_official | 579:53297373a894 | 292 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 293 | uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ |
| mbed_official | 579:53297373a894 | 294 | uint16_t :3; /*!< bit: 9..11 Reserved */ |
| mbed_official | 579:53297373a894 | 295 | uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ |
| mbed_official | 579:53297373a894 | 296 | uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ |
| mbed_official | 579:53297373a894 | 297 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
| mbed_official | 579:53297373a894 | 298 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 299 | struct { |
| mbed_official | 579:53297373a894 | 300 | uint16_t :12; /*!< bit: 0..11 Reserved */ |
| mbed_official | 579:53297373a894 | 301 | uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ |
| mbed_official | 579:53297373a894 | 302 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
| mbed_official | 579:53297373a894 | 303 | } vec; /*!< Structure used for vec access */ |
| mbed_official | 579:53297373a894 | 304 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 305 | } TC_EVCTRL_Type; |
| mbed_official | 579:53297373a894 | 306 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 307 | |
| mbed_official | 579:53297373a894 | 308 | #define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */ |
| mbed_official | 579:53297373a894 | 309 | #define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */ |
| mbed_official | 579:53297373a894 | 310 | |
| mbed_official | 579:53297373a894 | 311 | #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ |
| mbed_official | 579:53297373a894 | 312 | #define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos) |
| mbed_official | 579:53297373a894 | 313 | #define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))) |
| mbed_official | 579:53297373a894 | 314 | #define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */ |
| mbed_official | 579:53297373a894 | 315 | #define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ |
| mbed_official | 579:53297373a894 | 316 | #define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */ |
| mbed_official | 579:53297373a894 | 317 | #define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */ |
| mbed_official | 579:53297373a894 | 318 | #define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */ |
| mbed_official | 579:53297373a894 | 319 | #define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */ |
| mbed_official | 579:53297373a894 | 320 | #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) |
| mbed_official | 579:53297373a894 | 321 | #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) |
| mbed_official | 579:53297373a894 | 322 | #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) |
| mbed_official | 579:53297373a894 | 323 | #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) |
| mbed_official | 579:53297373a894 | 324 | #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) |
| mbed_official | 579:53297373a894 | 325 | #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) |
| mbed_official | 579:53297373a894 | 326 | #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */ |
| mbed_official | 579:53297373a894 | 327 | #define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos) |
| mbed_official | 579:53297373a894 | 328 | #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */ |
| mbed_official | 579:53297373a894 | 329 | #define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos) |
| mbed_official | 579:53297373a894 | 330 | #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */ |
| mbed_official | 579:53297373a894 | 331 | #define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos) |
| mbed_official | 579:53297373a894 | 332 | #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ |
| mbed_official | 579:53297373a894 | 333 | #define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) |
| mbed_official | 579:53297373a894 | 334 | #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ |
| mbed_official | 579:53297373a894 | 335 | #define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) |
| mbed_official | 579:53297373a894 | 336 | #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */ |
| mbed_official | 579:53297373a894 | 337 | #define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos) |
| mbed_official | 579:53297373a894 | 338 | #define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))) |
| mbed_official | 579:53297373a894 | 339 | #define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 340 | |
| mbed_official | 579:53297373a894 | 341 | /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ |
| mbed_official | 579:53297373a894 | 342 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 343 | typedef union { |
| mbed_official | 579:53297373a894 | 344 | struct { |
| mbed_official | 579:53297373a894 | 345 | uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 346 | uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 347 | uint8_t :1; /*!< bit: 2 Reserved */ |
| mbed_official | 579:53297373a894 | 348 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 349 | uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 350 | uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 351 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 352 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 353 | struct { |
| mbed_official | 579:53297373a894 | 354 | uint8_t :4; /*!< bit: 0.. 3 Reserved */ |
| mbed_official | 579:53297373a894 | 355 | uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 356 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 357 | } vec; /*!< Structure used for vec access */ |
| mbed_official | 579:53297373a894 | 358 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 359 | } TC_INTENCLR_Type; |
| mbed_official | 579:53297373a894 | 360 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 361 | |
| mbed_official | 579:53297373a894 | 362 | #define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 363 | #define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 364 | |
| mbed_official | 579:53297373a894 | 365 | #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 366 | #define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos) |
| mbed_official | 579:53297373a894 | 367 | #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 368 | #define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos) |
| mbed_official | 579:53297373a894 | 369 | #define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 370 | #define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos) |
| mbed_official | 579:53297373a894 | 371 | #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 372 | #define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) |
| mbed_official | 579:53297373a894 | 373 | #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 374 | #define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) |
| mbed_official | 579:53297373a894 | 375 | #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 376 | #define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos) |
| mbed_official | 579:53297373a894 | 377 | #define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))) |
| mbed_official | 579:53297373a894 | 378 | #define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */ |
| mbed_official | 579:53297373a894 | 379 | |
| mbed_official | 579:53297373a894 | 380 | /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ |
| mbed_official | 579:53297373a894 | 381 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 382 | typedef union { |
| mbed_official | 579:53297373a894 | 383 | struct { |
| mbed_official | 579:53297373a894 | 384 | uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 385 | uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 386 | uint8_t :1; /*!< bit: 2 Reserved */ |
| mbed_official | 579:53297373a894 | 387 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 388 | uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 389 | uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 390 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 391 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 392 | struct { |
| mbed_official | 579:53297373a894 | 393 | uint8_t :4; /*!< bit: 0.. 3 Reserved */ |
| mbed_official | 579:53297373a894 | 394 | uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 395 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 396 | } vec; /*!< Structure used for vec access */ |
| mbed_official | 579:53297373a894 | 397 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 398 | } TC_INTENSET_Type; |
| mbed_official | 579:53297373a894 | 399 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 400 | |
| mbed_official | 579:53297373a894 | 401 | #define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 402 | #define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 403 | |
| mbed_official | 579:53297373a894 | 404 | #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 405 | #define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos) |
| mbed_official | 579:53297373a894 | 406 | #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 407 | #define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos) |
| mbed_official | 579:53297373a894 | 408 | #define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 409 | #define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos) |
| mbed_official | 579:53297373a894 | 410 | #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 411 | #define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) |
| mbed_official | 579:53297373a894 | 412 | #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 413 | #define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) |
| mbed_official | 579:53297373a894 | 414 | #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 415 | #define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos) |
| mbed_official | 579:53297373a894 | 416 | #define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))) |
| mbed_official | 579:53297373a894 | 417 | #define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */ |
| mbed_official | 579:53297373a894 | 418 | |
| mbed_official | 579:53297373a894 | 419 | /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ |
| mbed_official | 579:53297373a894 | 420 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 421 | typedef union { |
| mbed_official | 579:53297373a894 | 422 | struct { |
| mbed_official | 579:53297373a894 | 423 | uint8_t OVF:1; /*!< bit: 0 Overflow */ |
| mbed_official | 579:53297373a894 | 424 | uint8_t ERR:1; /*!< bit: 1 Error */ |
| mbed_official | 579:53297373a894 | 425 | uint8_t :1; /*!< bit: 2 Reserved */ |
| mbed_official | 579:53297373a894 | 426 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ |
| mbed_official | 579:53297373a894 | 427 | uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ |
| mbed_official | 579:53297373a894 | 428 | uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ |
| mbed_official | 579:53297373a894 | 429 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 430 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 431 | struct { |
| mbed_official | 579:53297373a894 | 432 | uint8_t :4; /*!< bit: 0.. 3 Reserved */ |
| mbed_official | 579:53297373a894 | 433 | uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ |
| mbed_official | 579:53297373a894 | 434 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 435 | } vec; /*!< Structure used for vec access */ |
| mbed_official | 579:53297373a894 | 436 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 437 | } TC_INTFLAG_Type; |
| mbed_official | 579:53297373a894 | 438 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 439 | |
| mbed_official | 579:53297373a894 | 440 | #define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 441 | #define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 442 | |
| mbed_official | 579:53297373a894 | 443 | #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */ |
| mbed_official | 579:53297373a894 | 444 | #define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos) |
| mbed_official | 579:53297373a894 | 445 | #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */ |
| mbed_official | 579:53297373a894 | 446 | #define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos) |
| mbed_official | 579:53297373a894 | 447 | #define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */ |
| mbed_official | 579:53297373a894 | 448 | #define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos) |
| mbed_official | 579:53297373a894 | 449 | #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */ |
| mbed_official | 579:53297373a894 | 450 | #define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) |
| mbed_official | 579:53297373a894 | 451 | #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */ |
| mbed_official | 579:53297373a894 | 452 | #define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) |
| mbed_official | 579:53297373a894 | 453 | #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */ |
| mbed_official | 579:53297373a894 | 454 | #define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos) |
| mbed_official | 579:53297373a894 | 455 | #define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))) |
| mbed_official | 579:53297373a894 | 456 | #define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */ |
| mbed_official | 579:53297373a894 | 457 | |
| mbed_official | 579:53297373a894 | 458 | /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ |
| mbed_official | 579:53297373a894 | 459 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 460 | typedef union { |
| mbed_official | 579:53297373a894 | 461 | struct { |
| mbed_official | 579:53297373a894 | 462 | uint8_t :3; /*!< bit: 0.. 2 Reserved */ |
| mbed_official | 579:53297373a894 | 463 | uint8_t STOP:1; /*!< bit: 3 Stop */ |
| mbed_official | 579:53297373a894 | 464 | uint8_t SLAVE:1; /*!< bit: 4 Slave */ |
| mbed_official | 579:53297373a894 | 465 | uint8_t :2; /*!< bit: 5.. 6 Reserved */ |
| mbed_official | 579:53297373a894 | 466 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ |
| mbed_official | 579:53297373a894 | 467 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 468 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 469 | } TC_STATUS_Type; |
| mbed_official | 579:53297373a894 | 470 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 471 | |
| mbed_official | 579:53297373a894 | 472 | #define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */ |
| mbed_official | 579:53297373a894 | 473 | #define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */ |
| mbed_official | 579:53297373a894 | 474 | |
| mbed_official | 579:53297373a894 | 475 | #define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */ |
| mbed_official | 579:53297373a894 | 476 | #define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos) |
| mbed_official | 579:53297373a894 | 477 | #define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */ |
| mbed_official | 579:53297373a894 | 478 | #define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos) |
| mbed_official | 579:53297373a894 | 479 | #define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */ |
| mbed_official | 579:53297373a894 | 480 | #define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos) |
| mbed_official | 579:53297373a894 | 481 | #define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */ |
| mbed_official | 579:53297373a894 | 482 | |
| mbed_official | 579:53297373a894 | 483 | /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ |
| mbed_official | 579:53297373a894 | 484 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 485 | typedef union { |
| mbed_official | 579:53297373a894 | 486 | struct { |
| mbed_official | 579:53297373a894 | 487 | uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ |
| mbed_official | 579:53297373a894 | 488 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 489 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 490 | } TC_COUNT16_COUNT_Type; |
| mbed_official | 579:53297373a894 | 491 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 492 | |
| mbed_official | 579:53297373a894 | 493 | #define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */ |
| mbed_official | 579:53297373a894 | 494 | #define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */ |
| mbed_official | 579:53297373a894 | 495 | |
| mbed_official | 579:53297373a894 | 496 | #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */ |
| mbed_official | 579:53297373a894 | 497 | #define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos) |
| mbed_official | 579:53297373a894 | 498 | #define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))) |
| mbed_official | 579:53297373a894 | 499 | #define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */ |
| mbed_official | 579:53297373a894 | 500 | |
| mbed_official | 579:53297373a894 | 501 | /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ |
| mbed_official | 579:53297373a894 | 502 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 503 | typedef union { |
| mbed_official | 579:53297373a894 | 504 | struct { |
| mbed_official | 579:53297373a894 | 505 | uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ |
| mbed_official | 579:53297373a894 | 506 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 507 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 508 | } TC_COUNT32_COUNT_Type; |
| mbed_official | 579:53297373a894 | 509 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 510 | |
| mbed_official | 579:53297373a894 | 511 | #define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */ |
| mbed_official | 579:53297373a894 | 512 | #define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */ |
| mbed_official | 579:53297373a894 | 513 | |
| mbed_official | 579:53297373a894 | 514 | #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */ |
| mbed_official | 579:53297373a894 | 515 | #define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos) |
| mbed_official | 579:53297373a894 | 516 | #define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))) |
| mbed_official | 579:53297373a894 | 517 | #define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */ |
| mbed_official | 579:53297373a894 | 518 | |
| mbed_official | 579:53297373a894 | 519 | /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ |
| mbed_official | 579:53297373a894 | 520 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 521 | typedef union { |
| mbed_official | 579:53297373a894 | 522 | struct { |
| mbed_official | 579:53297373a894 | 523 | uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ |
| mbed_official | 579:53297373a894 | 524 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 525 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 526 | } TC_COUNT8_COUNT_Type; |
| mbed_official | 579:53297373a894 | 527 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 528 | |
| mbed_official | 579:53297373a894 | 529 | #define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */ |
| mbed_official | 579:53297373a894 | 530 | #define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */ |
| mbed_official | 579:53297373a894 | 531 | |
| mbed_official | 579:53297373a894 | 532 | #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ |
| mbed_official | 579:53297373a894 | 533 | #define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos) |
| mbed_official | 579:53297373a894 | 534 | #define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))) |
| mbed_official | 579:53297373a894 | 535 | #define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */ |
| mbed_official | 579:53297373a894 | 536 | |
| mbed_official | 579:53297373a894 | 537 | /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ |
| mbed_official | 579:53297373a894 | 538 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 539 | typedef union { |
| mbed_official | 579:53297373a894 | 540 | struct { |
| mbed_official | 579:53297373a894 | 541 | uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ |
| mbed_official | 579:53297373a894 | 542 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 543 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 544 | } TC_COUNT8_PER_Type; |
| mbed_official | 579:53297373a894 | 545 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 546 | |
| mbed_official | 579:53297373a894 | 547 | #define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */ |
| mbed_official | 579:53297373a894 | 548 | #define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */ |
| mbed_official | 579:53297373a894 | 549 | |
| mbed_official | 579:53297373a894 | 550 | #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ |
| mbed_official | 579:53297373a894 | 551 | #define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos) |
| mbed_official | 579:53297373a894 | 552 | #define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))) |
| mbed_official | 579:53297373a894 | 553 | #define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */ |
| mbed_official | 579:53297373a894 | 554 | |
| mbed_official | 579:53297373a894 | 555 | /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ |
| mbed_official | 579:53297373a894 | 556 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 557 | typedef union { |
| mbed_official | 579:53297373a894 | 558 | struct { |
| mbed_official | 579:53297373a894 | 559 | uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ |
| mbed_official | 579:53297373a894 | 560 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 561 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 562 | } TC_COUNT16_CC_Type; |
| mbed_official | 579:53297373a894 | 563 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 564 | |
| mbed_official | 579:53297373a894 | 565 | #define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 566 | #define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 567 | |
| mbed_official | 579:53297373a894 | 568 | #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */ |
| mbed_official | 579:53297373a894 | 569 | #define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos) |
| mbed_official | 579:53297373a894 | 570 | #define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))) |
| mbed_official | 579:53297373a894 | 571 | #define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */ |
| mbed_official | 579:53297373a894 | 572 | |
| mbed_official | 579:53297373a894 | 573 | /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ |
| mbed_official | 579:53297373a894 | 574 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 575 | typedef union { |
| mbed_official | 579:53297373a894 | 576 | struct { |
| mbed_official | 579:53297373a894 | 577 | uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ |
| mbed_official | 579:53297373a894 | 578 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 579 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 580 | } TC_COUNT32_CC_Type; |
| mbed_official | 579:53297373a894 | 581 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 582 | |
| mbed_official | 579:53297373a894 | 583 | #define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 584 | #define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 585 | |
| mbed_official | 579:53297373a894 | 586 | #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */ |
| mbed_official | 579:53297373a894 | 587 | #define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos) |
| mbed_official | 579:53297373a894 | 588 | #define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))) |
| mbed_official | 579:53297373a894 | 589 | #define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */ |
| mbed_official | 579:53297373a894 | 590 | |
| mbed_official | 579:53297373a894 | 591 | /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ |
| mbed_official | 579:53297373a894 | 592 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 593 | typedef union { |
| mbed_official | 579:53297373a894 | 594 | struct { |
| mbed_official | 579:53297373a894 | 595 | uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ |
| mbed_official | 579:53297373a894 | 596 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 597 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 598 | } TC_COUNT8_CC_Type; |
| mbed_official | 579:53297373a894 | 599 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 600 | |
| mbed_official | 579:53297373a894 | 601 | #define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 602 | #define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 603 | |
| mbed_official | 579:53297373a894 | 604 | #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */ |
| mbed_official | 579:53297373a894 | 605 | #define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos) |
| mbed_official | 579:53297373a894 | 606 | #define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))) |
| mbed_official | 579:53297373a894 | 607 | #define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */ |
| mbed_official | 579:53297373a894 | 608 | |
| mbed_official | 579:53297373a894 | 609 | /** \brief TC_COUNT8 hardware registers */ |
| mbed_official | 579:53297373a894 | 610 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 611 | typedef struct { /* 8-bit Counter Mode */ |
| mbed_official | 579:53297373a894 | 612 | __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ |
| mbed_official | 579:53297373a894 | 613 | __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ |
| mbed_official | 579:53297373a894 | 614 | __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ |
| mbed_official | 579:53297373a894 | 615 | __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ |
| mbed_official | 579:53297373a894 | 616 | __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ |
| mbed_official | 579:53297373a894 | 617 | RoReg8 Reserved1[0x1]; |
| mbed_official | 579:53297373a894 | 618 | __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ |
| mbed_official | 579:53297373a894 | 619 | RoReg8 Reserved2[0x1]; |
| mbed_official | 579:53297373a894 | 620 | __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ |
| mbed_official | 579:53297373a894 | 621 | __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 622 | __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 623 | __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 624 | __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ |
| mbed_official | 579:53297373a894 | 625 | __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ |
| mbed_official | 579:53297373a894 | 626 | RoReg8 Reserved3[0x3]; |
| mbed_official | 579:53297373a894 | 627 | __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ |
| mbed_official | 579:53297373a894 | 628 | RoReg8 Reserved4[0x3]; |
| mbed_official | 579:53297373a894 | 629 | __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 630 | } TcCount8; |
| mbed_official | 579:53297373a894 | 631 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 632 | |
| mbed_official | 579:53297373a894 | 633 | /** \brief TC_COUNT16 hardware registers */ |
| mbed_official | 579:53297373a894 | 634 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 635 | typedef struct { /* 16-bit Counter Mode */ |
| mbed_official | 579:53297373a894 | 636 | __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ |
| mbed_official | 579:53297373a894 | 637 | __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ |
| mbed_official | 579:53297373a894 | 638 | __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ |
| mbed_official | 579:53297373a894 | 639 | __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ |
| mbed_official | 579:53297373a894 | 640 | __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ |
| mbed_official | 579:53297373a894 | 641 | RoReg8 Reserved1[0x1]; |
| mbed_official | 579:53297373a894 | 642 | __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ |
| mbed_official | 579:53297373a894 | 643 | RoReg8 Reserved2[0x1]; |
| mbed_official | 579:53297373a894 | 644 | __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ |
| mbed_official | 579:53297373a894 | 645 | __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 646 | __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 647 | __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 648 | __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ |
| mbed_official | 579:53297373a894 | 649 | __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ |
| mbed_official | 579:53297373a894 | 650 | RoReg8 Reserved3[0x6]; |
| mbed_official | 579:53297373a894 | 651 | __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 652 | } TcCount16; |
| mbed_official | 579:53297373a894 | 653 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 654 | |
| mbed_official | 579:53297373a894 | 655 | /** \brief TC_COUNT32 hardware registers */ |
| mbed_official | 579:53297373a894 | 656 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 657 | typedef struct { /* 32-bit Counter Mode */ |
| mbed_official | 579:53297373a894 | 658 | __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ |
| mbed_official | 579:53297373a894 | 659 | __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ |
| mbed_official | 579:53297373a894 | 660 | __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ |
| mbed_official | 579:53297373a894 | 661 | __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ |
| mbed_official | 579:53297373a894 | 662 | __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ |
| mbed_official | 579:53297373a894 | 663 | RoReg8 Reserved1[0x1]; |
| mbed_official | 579:53297373a894 | 664 | __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ |
| mbed_official | 579:53297373a894 | 665 | RoReg8 Reserved2[0x1]; |
| mbed_official | 579:53297373a894 | 666 | __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ |
| mbed_official | 579:53297373a894 | 667 | __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 668 | __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 669 | __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 670 | __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ |
| mbed_official | 579:53297373a894 | 671 | __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ |
| mbed_official | 579:53297373a894 | 672 | RoReg8 Reserved3[0x4]; |
| mbed_official | 579:53297373a894 | 673 | __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ |
| mbed_official | 579:53297373a894 | 674 | } TcCount32; |
| mbed_official | 579:53297373a894 | 675 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 676 | |
| mbed_official | 579:53297373a894 | 677 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 678 | typedef union { |
| mbed_official | 579:53297373a894 | 679 | TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ |
| mbed_official | 579:53297373a894 | 680 | TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ |
| mbed_official | 579:53297373a894 | 681 | TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ |
| mbed_official | 579:53297373a894 | 682 | } Tc; |
| mbed_official | 579:53297373a894 | 683 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 684 | |
| mbed_official | 579:53297373a894 | 685 | /*@}*/ |
| mbed_official | 579:53297373a894 | 686 | |
| mbed_official | 579:53297373a894 | 687 | #endif /* _SAMD21_TC_COMPONENT_ */ |