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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h@380:510f0c3515e3, 2014-11-03 (annotated)

Committer:: mbed_official
Date:: Mon Nov 03 10:15:07 2014 +0000
Revision:: 380:510f0c3515e3
Parent:: targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.h@369:2e96f1b71984
Child:: 532:fe11edbda85c

Synchronized with git revision 417f470ba9f4882d7079611cbc576afd9c49b0ef

Full URL: https://github.com/mbedmicro/mbed/commit/417f470ba9f4882d7079611cbc576afd9c49b0ef/

Targets: Factorisation of NUCLEO_F401RE and F411RE cmsis folders

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_tim.h
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	369:2e96f1b71984	5	* @version V1.1.0
mbed_official	369:2e96f1b71984	6	* @date 19-June-2014
mbed_official	87:085cde657901	7	* @brief Header file of TIM HAL module.
mbed_official	87:085cde657901	8	******************************************************************************
mbed_official	87:085cde657901	9	* @attention
mbed_official	87:085cde657901	10	*
mbed_official	87:085cde657901	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	12	*
mbed_official	87:085cde657901	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	14	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	16	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	19	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	21	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	22	* without specific prior written permission.
mbed_official	87:085cde657901	23	*
mbed_official	87:085cde657901	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	34	*
mbed_official	87:085cde657901	35	******************************************************************************
mbed_official	87:085cde657901	36	*/
mbed_official	87:085cde657901	37
mbed_official	87:085cde657901	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	87:085cde657901	39	#ifndef __STM32F4xx_HAL_TIM_H
mbed_official	87:085cde657901	40	#define __STM32F4xx_HAL_TIM_H
mbed_official	87:085cde657901	41
mbed_official	87:085cde657901	42	#ifdef __cplusplus
mbed_official	87:085cde657901	43	extern "C" {
mbed_official	87:085cde657901	44	#endif
mbed_official	87:085cde657901	45
mbed_official	87:085cde657901	46	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	47	#include "stm32f4xx_hal_def.h"
mbed_official	87:085cde657901	48
mbed_official	87:085cde657901	49	/** @addtogroup STM32F4xx_HAL
mbed_official	87:085cde657901	50	* @{
mbed_official	87:085cde657901	51	*/
mbed_official	87:085cde657901	52
mbed_official	87:085cde657901	53	/** @addtogroup TIM
mbed_official	87:085cde657901	54	* @{
mbed_official	226:b062af740e40	55	*/
mbed_official	87:085cde657901	56
mbed_official	226:b062af740e40	57	/* Exported types ------------------------------------------------------------*/
mbed_official	87:085cde657901	58
mbed_official	87:085cde657901	59	/**
mbed_official	87:085cde657901	60	* @brief TIM Time base Configuration Structure definition
mbed_official	87:085cde657901	61	*/
mbed_official	87:085cde657901	62	typedef struct
mbed_official	87:085cde657901	63	{
mbed_official	87:085cde657901	64	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	87:085cde657901	65	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	87:085cde657901	66
mbed_official	87:085cde657901	67	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	87:085cde657901	68	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	87:085cde657901	69
mbed_official	87:085cde657901	70	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	87:085cde657901	71	Auto-Reload Register at the next update event.
mbed_official	226:b062af740e40	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	87:085cde657901	73
mbed_official	87:085cde657901	74	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	87:085cde657901	75	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	87:085cde657901	76
mbed_official	87:085cde657901	77	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
mbed_official	87:085cde657901	78	reaches zero, an update event is generated and counting restarts
mbed_official	87:085cde657901	79	from the RCR value (N).
mbed_official	87:085cde657901	80	This means in PWM mode that (N+1) corresponds to:
mbed_official	87:085cde657901	81	- the number of PWM periods in edge-aligned mode
mbed_official	87:085cde657901	82	- the number of half PWM period in center-aligned mode
mbed_official	87:085cde657901	83	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
mbed_official	87:085cde657901	84	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	85	} TIM_Base_InitTypeDef;
mbed_official	87:085cde657901	86
mbed_official	87:085cde657901	87	/**
mbed_official	87:085cde657901	88	* @brief TIM Output Compare Configuration Structure definition
mbed_official	87:085cde657901	89	*/
mbed_official	87:085cde657901	90
mbed_official	87:085cde657901	91	typedef struct
mbed_official	226:b062af740e40	92	{
mbed_official	87:085cde657901	93	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	87:085cde657901	94	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	87:085cde657901	95
mbed_official	87:085cde657901	96	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	226:b062af740e40	97	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	87:085cde657901	98
mbed_official	87:085cde657901	99	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	87:085cde657901	100	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	87:085cde657901	101
mbed_official	87:085cde657901	102	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	87:085cde657901	103	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	87:085cde657901	104	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	105
mbed_official	87:085cde657901	106	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	87:085cde657901	107	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	87:085cde657901	108	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	87:085cde657901	109
mbed_official	87:085cde657901	110
mbed_official	87:085cde657901	111	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	112	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	87:085cde657901	113	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	114
mbed_official	87:085cde657901	115	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	116	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	87:085cde657901	117	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	118	} TIM_OC_InitTypeDef;
mbed_official	87:085cde657901	119
mbed_official	87:085cde657901	120	/**
mbed_official	87:085cde657901	121	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	87:085cde657901	122	*/
mbed_official	87:085cde657901	123	typedef struct
mbed_official	226:b062af740e40	124	{
mbed_official	87:085cde657901	125	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	87:085cde657901	126	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	87:085cde657901	127
mbed_official	87:085cde657901	128	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	226:b062af740e40	129	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	87:085cde657901	130
mbed_official	87:085cde657901	131	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	87:085cde657901	132	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	87:085cde657901	133
mbed_official	87:085cde657901	134	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	87:085cde657901	135	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	87:085cde657901	136	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	137
mbed_official	87:085cde657901	138	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	139	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	87:085cde657901	140	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	141
mbed_official	87:085cde657901	142	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	87:085cde657901	143	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	87:085cde657901	144	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	87:085cde657901	145
mbed_official	87:085cde657901	146	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	147	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	148
mbed_official	87:085cde657901	149	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	87:085cde657901	150	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	151
mbed_official	87:085cde657901	152	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	87:085cde657901	153	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	154	} TIM_OnePulse_InitTypeDef;
mbed_official	87:085cde657901	155
mbed_official	87:085cde657901	156
mbed_official	87:085cde657901	157	/**
mbed_official	87:085cde657901	158	* @brief TIM Input Capture Configuration Structure definition
mbed_official	87:085cde657901	159	*/
mbed_official	87:085cde657901	160
mbed_official	87:085cde657901	161	typedef struct
mbed_official	226:b062af740e40	162	{
mbed_official	87:085cde657901	163	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	164	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	165
mbed_official	87:085cde657901	166	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	87:085cde657901	167	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	168
mbed_official	87:085cde657901	169	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	87:085cde657901	170	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	87:085cde657901	171
mbed_official	87:085cde657901	172	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	87:085cde657901	173	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	174	} TIM_IC_InitTypeDef;
mbed_official	87:085cde657901	175
mbed_official	87:085cde657901	176	/**
mbed_official	87:085cde657901	177	* @brief TIM Encoder Configuration Structure definition
mbed_official	87:085cde657901	178	*/
mbed_official	87:085cde657901	179
mbed_official	87:085cde657901	180	typedef struct
mbed_official	87:085cde657901	181	{
mbed_official	87:085cde657901	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	183	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	87:085cde657901	184
mbed_official	87:085cde657901	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	187
mbed_official	87:085cde657901	188	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	87:085cde657901	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	190
mbed_official	87:085cde657901	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	87:085cde657901	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	87:085cde657901	193
mbed_official	87:085cde657901	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	87:085cde657901	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	196
mbed_official	87:085cde657901	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	87:085cde657901	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	87:085cde657901	199
mbed_official	87:085cde657901	200	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	87:085cde657901	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	87:085cde657901	202
mbed_official	87:085cde657901	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	87:085cde657901	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	87:085cde657901	205
mbed_official	87:085cde657901	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	226:b062af740e40	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	208	} TIM_Encoder_InitTypeDef;
mbed_official	87:085cde657901	209
mbed_official	87:085cde657901	210	/**
mbed_official	87:085cde657901	211	* @brief Clock Configuration Handle Structure definition
mbed_official	87:085cde657901	212	*/
mbed_official	87:085cde657901	213	typedef struct
mbed_official	87:085cde657901	214	{
mbed_official	226:b062af740e40	215	uint32_t ClockSource; /*!< TIM clock sources.
mbed_official	87:085cde657901	216	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	226:b062af740e40	217	uint32_t ClockPolarity; /*!< TIM clock polarity.
mbed_official	87:085cde657901	218	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	226:b062af740e40	219	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
mbed_official	87:085cde657901	220	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	226:b062af740e40	221	uint32_t ClockFilter; /*!< TIM clock filter.
mbed_official	226:b062af740e40	222	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	223	}TIM_ClockConfigTypeDef;
mbed_official	87:085cde657901	224
mbed_official	87:085cde657901	225	/**
mbed_official	87:085cde657901	226	* @brief Clear Input Configuration Handle Structure definition
mbed_official	87:085cde657901	227	*/
mbed_official	87:085cde657901	228	typedef struct
mbed_official	87:085cde657901	229	{
mbed_official	226:b062af740e40	230	uint32_t ClearInputState; /*!< TIM clear Input state.
mbed_official	87:085cde657901	231	This parameter can be ENABLE or DISABLE */
mbed_official	226:b062af740e40	232	uint32_t ClearInputSource; /*!< TIM clear Input sources.
mbed_official	87:085cde657901	233	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	226:b062af740e40	234	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
mbed_official	87:085cde657901	235	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	226:b062af740e40	236	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
mbed_official	87:085cde657901	237	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	226:b062af740e40	238	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
mbed_official	226:b062af740e40	239	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	240	}TIM_ClearInputConfigTypeDef;
mbed_official	87:085cde657901	241
mbed_official	87:085cde657901	242	/**
mbed_official	87:085cde657901	243	* @brief TIM Slave configuration Structure definition
mbed_official	87:085cde657901	244	*/
mbed_official	87:085cde657901	245	typedef struct {
mbed_official	87:085cde657901	246	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	87:085cde657901	247	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	87:085cde657901	248	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	87:085cde657901	249	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	87:085cde657901	250	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	87:085cde657901	251	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	87:085cde657901	252	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	87:085cde657901	253	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	87:085cde657901	254	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	226:b062af740e40	255	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	87:085cde657901	256
mbed_official	87:085cde657901	257	}TIM_SlaveConfigTypeDef;
mbed_official	87:085cde657901	258
mbed_official	87:085cde657901	259	/**
mbed_official	87:085cde657901	260	* @brief HAL State structures definition
mbed_official	87:085cde657901	261	*/
mbed_official	87:085cde657901	262	typedef enum
mbed_official	87:085cde657901	263	{
mbed_official	87:085cde657901	264	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	87:085cde657901	265	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	226:b062af740e40	266	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	226:b062af740e40	267	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	226:b062af740e40	268	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	87:085cde657901	269	}HAL_TIM_StateTypeDef;
mbed_official	87:085cde657901	270
mbed_official	87:085cde657901	271	/**
mbed_official	87:085cde657901	272	* @brief HAL Active channel structures definition
mbed_official	87:085cde657901	273	*/
mbed_official	87:085cde657901	274	typedef enum
mbed_official	87:085cde657901	275	{
mbed_official	87:085cde657901	276	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	87:085cde657901	277	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	226:b062af740e40	278	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	87:085cde657901	279	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	226:b062af740e40	280	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	87:085cde657901	281	}HAL_TIM_ActiveChannel;
mbed_official	87:085cde657901	282
mbed_official	87:085cde657901	283	/**
mbed_official	87:085cde657901	284	* @brief TIM Time Base Handle Structure definition
mbed_official	87:085cde657901	285	*/
mbed_official	87:085cde657901	286	typedef struct
mbed_official	87:085cde657901	287	{
mbed_official	226:b062af740e40	288	TIM_TypeDef Instance; /!< Register base address */
mbed_official	87:085cde657901	289	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	226:b062af740e40	290	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	87:085cde657901	291	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	87:085cde657901	292	This array is accessed by a @ref DMA_Handle_index */
mbed_official	87:085cde657901	293	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	226:b062af740e40	294	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	87:085cde657901	295	}TIM_HandleTypeDef;
mbed_official	87:085cde657901	296
mbed_official	87:085cde657901	297	/* Exported constants --------------------------------------------------------*/
mbed_official	87:085cde657901	298	/** @defgroup TIM_Exported_Constants
mbed_official	87:085cde657901	299	* @{
mbed_official	87:085cde657901	300	*/
mbed_official	87:085cde657901	301
mbed_official	87:085cde657901	302	/** @defgroup TIM_Input_Channel_Polarity
mbed_official	87:085cde657901	303	* @{
mbed_official	87:085cde657901	304	*/
mbed_official	87:085cde657901	305	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	87:085cde657901	306	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	87:085cde657901	307	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	87:085cde657901	308	/**
mbed_official	87:085cde657901	309	* @}
mbed_official	87:085cde657901	310	*/
mbed_official	87:085cde657901	311
mbed_official	87:085cde657901	312	/** @defgroup TIM_ETR_Polarity
mbed_official	87:085cde657901	313	* @{
mbed_official	87:085cde657901	314	*/
mbed_official	226:b062af740e40	315	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	226:b062af740e40	316	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	87:085cde657901	317	/**
mbed_official	87:085cde657901	318	* @}
mbed_official	87:085cde657901	319	*/
mbed_official	87:085cde657901	320
mbed_official	87:085cde657901	321	/** @defgroup TIM_ETR_Prescaler
mbed_official	87:085cde657901	322	* @{
mbed_official	226:b062af740e40	323	*/
mbed_official	87:085cde657901	324	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	87:085cde657901	325	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	87:085cde657901	326	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	87:085cde657901	327	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	87:085cde657901	328	/**
mbed_official	87:085cde657901	329	* @}
mbed_official	87:085cde657901	330	*/
mbed_official	87:085cde657901	331
mbed_official	87:085cde657901	332	/** @defgroup TIM_Counter_Mode
mbed_official	87:085cde657901	333	* @{
mbed_official	87:085cde657901	334	*/
mbed_official	87:085cde657901	335	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	87:085cde657901	336	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	87:085cde657901	337	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	87:085cde657901	338	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	87:085cde657901	339	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	87:085cde657901	340
mbed_official	87:085cde657901	341	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	87:085cde657901	342	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	87:085cde657901	343	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	87:085cde657901	344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	87:085cde657901	345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	87:085cde657901	346	/**
mbed_official	87:085cde657901	347	* @}
mbed_official	226:b062af740e40	348	*/
mbed_official	226:b062af740e40	349
mbed_official	87:085cde657901	350	/** @defgroup TIM_ClockDivision
mbed_official	87:085cde657901	351	* @{
mbed_official	87:085cde657901	352	*/
mbed_official	87:085cde657901	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	87:085cde657901	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	87:085cde657901	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	87:085cde657901	356
mbed_official	87:085cde657901	357	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	87:085cde657901	358	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	87:085cde657901	359	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	87:085cde657901	360	/**
mbed_official	87:085cde657901	361	* @}
mbed_official	87:085cde657901	362	*/
mbed_official	87:085cde657901	363
mbed_official	87:085cde657901	364	/** @defgroup TIM_Output_Compare_and_PWM_modes
mbed_official	87:085cde657901	365	* @{
mbed_official	87:085cde657901	366	*/
mbed_official	87:085cde657901	367	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	87:085cde657901	368	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	87:085cde657901	369	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	87:085cde657901	370	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	87:085cde657901	371	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	87:085cde657901	372	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	87:085cde657901	373	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	87:085cde657901	374	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	87:085cde657901	375
mbed_official	87:085cde657901	376	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
mbed_official	87:085cde657901	377	((MODE) == TIM_OCMODE_PWM2))
mbed_official	87:085cde657901	378
mbed_official	87:085cde657901	379	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
mbed_official	87:085cde657901	380	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	87:085cde657901	381	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	87:085cde657901	382	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	87:085cde657901	383	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	87:085cde657901	384	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	87:085cde657901	385	/**
mbed_official	87:085cde657901	386	* @}
mbed_official	87:085cde657901	387	*/
mbed_official	87:085cde657901	388
mbed_official	87:085cde657901	389	/** @defgroup TIM_Output_Compare_State
mbed_official	87:085cde657901	390	* @{
mbed_official	87:085cde657901	391	*/
mbed_official	87:085cde657901	392	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	393	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
mbed_official	87:085cde657901	394
mbed_official	87:085cde657901	395	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
mbed_official	87:085cde657901	396	((STATE) == TIM_OUTPUTSTATE_ENABLE))
mbed_official	87:085cde657901	397	/**
mbed_official	87:085cde657901	398	* @}
mbed_official	226:b062af740e40	399	*/
mbed_official	226:b062af740e40	400
mbed_official	87:085cde657901	401	/** @defgroup TIM_Output_Fast_State
mbed_official	87:085cde657901	402	* @{
mbed_official	87:085cde657901	403	*/
mbed_official	87:085cde657901	404	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	405	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	87:085cde657901	406
mbed_official	87:085cde657901	407	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	87:085cde657901	408	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	87:085cde657901	409	/**
mbed_official	87:085cde657901	410	* @}
mbed_official	226:b062af740e40	411	*/
mbed_official	226:b062af740e40	412
mbed_official	87:085cde657901	413	/** @defgroup TIM_Output_Compare_N_State
mbed_official	87:085cde657901	414	* @{
mbed_official	87:085cde657901	415	*/
mbed_official	87:085cde657901	416	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	417	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
mbed_official	87:085cde657901	418
mbed_official	87:085cde657901	419	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
mbed_official	87:085cde657901	420	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
mbed_official	87:085cde657901	421	/**
mbed_official	87:085cde657901	422	* @}
mbed_official	87:085cde657901	423	*/
mbed_official	226:b062af740e40	424
mbed_official	87:085cde657901	425	/** @defgroup TIM_Output_Compare_Polarity
mbed_official	87:085cde657901	426	* @{
mbed_official	87:085cde657901	427	*/
mbed_official	87:085cde657901	428	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	87:085cde657901	429	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	87:085cde657901	430
mbed_official	87:085cde657901	431	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	87:085cde657901	432	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	87:085cde657901	433	/**
mbed_official	87:085cde657901	434	* @}
mbed_official	87:085cde657901	435	*/
mbed_official	87:085cde657901	436
mbed_official	87:085cde657901	437	/** @defgroup TIM_Output_Compare_N_Polarity
mbed_official	87:085cde657901	438	* @{
mbed_official	87:085cde657901	439	*/
mbed_official	87:085cde657901	440	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	87:085cde657901	441	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
mbed_official	87:085cde657901	442
mbed_official	87:085cde657901	443	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
mbed_official	87:085cde657901	444	((POLARITY) == TIM_OCNPOLARITY_LOW))
mbed_official	87:085cde657901	445	/**
mbed_official	87:085cde657901	446	* @}
mbed_official	87:085cde657901	447	*/
mbed_official	87:085cde657901	448
mbed_official	87:085cde657901	449	/** @defgroup TIM_Output_Compare_Idle_State
mbed_official	87:085cde657901	450	* @{
mbed_official	87:085cde657901	451	*/
mbed_official	87:085cde657901	452	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
mbed_official	87:085cde657901	453	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	87:085cde657901	454	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
mbed_official	87:085cde657901	455	((STATE) == TIM_OCIDLESTATE_RESET))
mbed_official	87:085cde657901	456	/**
mbed_official	87:085cde657901	457	* @}
mbed_official	87:085cde657901	458	*/
mbed_official	87:085cde657901	459
mbed_official	87:085cde657901	460	/** @defgroup TIM_Output_Compare_N_Idle_State
mbed_official	87:085cde657901	461	* @{
mbed_official	87:085cde657901	462	*/
mbed_official	87:085cde657901	463	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
mbed_official	87:085cde657901	464	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	87:085cde657901	465	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
mbed_official	87:085cde657901	466	((STATE) == TIM_OCNIDLESTATE_RESET))
mbed_official	87:085cde657901	467	/**
mbed_official	87:085cde657901	468	* @}
mbed_official	87:085cde657901	469	*/
mbed_official	87:085cde657901	470
mbed_official	87:085cde657901	471	/** @defgroup TIM_Channel
mbed_official	87:085cde657901	472	* @{
mbed_official	87:085cde657901	473	*/
mbed_official	87:085cde657901	474	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	87:085cde657901	475	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	87:085cde657901	476	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	87:085cde657901	477	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	87:085cde657901	478	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	87:085cde657901	479
mbed_official	87:085cde657901	480	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	87:085cde657901	481	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	87:085cde657901	482	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	87:085cde657901	483	((CHANNEL) == TIM_CHANNEL_4) \|\| \
mbed_official	87:085cde657901	484	((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official	87:085cde657901	485
mbed_official	87:085cde657901	486	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	87:085cde657901	487	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	87:085cde657901	488
mbed_official	87:085cde657901	489	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	226:b062af740e40	490	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	87:085cde657901	491
mbed_official	87:085cde657901	492	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	87:085cde657901	493	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	87:085cde657901	494	((CHANNEL) == TIM_CHANNEL_3))
mbed_official	87:085cde657901	495	/**
mbed_official	87:085cde657901	496	* @}
mbed_official	226:b062af740e40	497	*/
mbed_official	87:085cde657901	498
mbed_official	87:085cde657901	499	/** @defgroup TIM_Input_Capture_Polarity
mbed_official	87:085cde657901	500	* @{
mbed_official	87:085cde657901	501	*/
mbed_official	87:085cde657901	502	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	87:085cde657901	503	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	87:085cde657901	504	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	226:b062af740e40	505
mbed_official	87:085cde657901	506	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	87:085cde657901	507	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	87:085cde657901	508	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	87:085cde657901	509	/**
mbed_official	87:085cde657901	510	* @}
mbed_official	226:b062af740e40	511	*/
mbed_official	87:085cde657901	512
mbed_official	87:085cde657901	513	/** @defgroup TIM_Input_Capture_Selection
mbed_official	87:085cde657901	514	* @{
mbed_official	87:085cde657901	515	*/
mbed_official	87:085cde657901	516	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	87:085cde657901	517	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	87:085cde657901	518	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	87:085cde657901	519	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	87:085cde657901	520	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	87:085cde657901	521
mbed_official	87:085cde657901	522	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	87:085cde657901	523	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	87:085cde657901	524	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	87:085cde657901	525	/**
mbed_official	87:085cde657901	526	* @}
mbed_official	226:b062af740e40	527	*/
mbed_official	87:085cde657901	528
mbed_official	87:085cde657901	529	/** @defgroup TIM_Input_Capture_Prescaler
mbed_official	87:085cde657901	530	* @{
mbed_official	87:085cde657901	531	*/
mbed_official	87:085cde657901	532	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	87:085cde657901	533	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	87:085cde657901	534	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	87:085cde657901	535	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	87:085cde657901	536
mbed_official	87:085cde657901	537	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	87:085cde657901	538	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	87:085cde657901	539	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	87:085cde657901	540	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	87:085cde657901	541	/**
mbed_official	87:085cde657901	542	* @}
mbed_official	87:085cde657901	543	*/
mbed_official	87:085cde657901	544
mbed_official	87:085cde657901	545	/** @defgroup TIM_One_Pulse_Mode
mbed_official	87:085cde657901	546	* @{
mbed_official	87:085cde657901	547	*/
mbed_official	87:085cde657901	548	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	87:085cde657901	549	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	87:085cde657901	550	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	87:085cde657901	551	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	87:085cde657901	552	/**
mbed_official	87:085cde657901	553	* @}
mbed_official	226:b062af740e40	554	*/
mbed_official	226:b062af740e40	555
mbed_official	87:085cde657901	556	/** @defgroup TIM_Encoder_Mode
mbed_official	87:085cde657901	557	* @{
mbed_official	226:b062af740e40	558	*/
mbed_official	87:085cde657901	559	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	87:085cde657901	560	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	87:085cde657901	561	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	87:085cde657901	562	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	87:085cde657901	563	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	87:085cde657901	564	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	87:085cde657901	565	/**
mbed_official	87:085cde657901	566	* @}
mbed_official	226:b062af740e40	567	*/
mbed_official	226:b062af740e40	568
mbed_official	87:085cde657901	569	/** @defgroup TIM_Interrupt_definition
mbed_official	87:085cde657901	570	* @{
mbed_official	87:085cde657901	571	*/
mbed_official	87:085cde657901	572	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	87:085cde657901	573	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	87:085cde657901	574	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	87:085cde657901	575	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	87:085cde657901	576	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	87:085cde657901	577	#define TIM_IT_COM (TIM_DIER_COMIE)
mbed_official	87:085cde657901	578	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	87:085cde657901	579	#define TIM_IT_BREAK (TIM_DIER_BIE)
mbed_official	87:085cde657901	580
mbed_official	87:085cde657901	581	#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
mbed_official	87:085cde657901	582
mbed_official	87:085cde657901	583	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) \|\| \
mbed_official	87:085cde657901	584	((IT) == TIM_IT_CC1) \|\| \
mbed_official	87:085cde657901	585	((IT) == TIM_IT_CC2) \|\| \
mbed_official	87:085cde657901	586	((IT) == TIM_IT_CC3) \|\| \
mbed_official	87:085cde657901	587	((IT) == TIM_IT_CC4) \|\| \
mbed_official	87:085cde657901	588	((IT) == TIM_IT_COM) \|\| \
mbed_official	87:085cde657901	589	((IT) == TIM_IT_TRIGGER) \|\| \
mbed_official	226:b062af740e40	590	((IT) == TIM_IT_BREAK))
mbed_official	87:085cde657901	591	/**
mbed_official	87:085cde657901	592	* @}
mbed_official	87:085cde657901	593	*/
mbed_official	369:2e96f1b71984	594	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
mbed_official	369:2e96f1b71984	595	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
mbed_official	87:085cde657901	596
mbed_official	87:085cde657901	597	/** @defgroup TIM_DMA_sources
mbed_official	87:085cde657901	598	* @{
mbed_official	87:085cde657901	599	*/
mbed_official	87:085cde657901	600	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	87:085cde657901	601	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	87:085cde657901	602	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	87:085cde657901	603	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	87:085cde657901	604	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	87:085cde657901	605	#define TIM_DMA_COM (TIM_DIER_COMDE)
mbed_official	87:085cde657901	606	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	87:085cde657901	607	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	87:085cde657901	608	/**
mbed_official	87:085cde657901	609	* @}
mbed_official	87:085cde657901	610	*/
mbed_official	226:b062af740e40	611
mbed_official	87:085cde657901	612	/** @defgroup TIM_Event_Source
mbed_official	87:085cde657901	613	* @{
mbed_official	87:085cde657901	614	*/
mbed_official	87:085cde657901	615	#define TIM_EventSource_Update TIM_EGR_UG
mbed_official	87:085cde657901	616	#define TIM_EventSource_CC1 TIM_EGR_CC1G
mbed_official	87:085cde657901	617	#define TIM_EventSource_CC2 TIM_EGR_CC2G
mbed_official	87:085cde657901	618	#define TIM_EventSource_CC3 TIM_EGR_CC3G
mbed_official	87:085cde657901	619	#define TIM_EventSource_CC4 TIM_EGR_CC4G
mbed_official	87:085cde657901	620	#define TIM_EventSource_COM TIM_EGR_COMG
mbed_official	87:085cde657901	621	#define TIM_EventSource_Trigger TIM_EGR_TG
mbed_official	87:085cde657901	622	#define TIM_EventSource_Break TIM_EGR_BG
mbed_official	226:b062af740e40	623	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	87:085cde657901	624	/**
mbed_official	87:085cde657901	625	* @}
mbed_official	226:b062af740e40	626	*/
mbed_official	87:085cde657901	627
mbed_official	87:085cde657901	628	/** @defgroup TIM_Flag_definition
mbed_official	87:085cde657901	629	* @{
mbed_official	226:b062af740e40	630	*/
mbed_official	87:085cde657901	631	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	87:085cde657901	632	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	87:085cde657901	633	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	87:085cde657901	634	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	87:085cde657901	635	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	87:085cde657901	636	#define TIM_FLAG_COM (TIM_SR_COMIF)
mbed_official	87:085cde657901	637	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	87:085cde657901	638	#define TIM_FLAG_BREAK (TIM_SR_BIF)
mbed_official	87:085cde657901	639	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	87:085cde657901	640	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	87:085cde657901	641	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	87:085cde657901	642	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	87:085cde657901	643
mbed_official	87:085cde657901	644	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
mbed_official	87:085cde657901	645	((FLAG) == TIM_FLAG_CC1) \|\| \
mbed_official	87:085cde657901	646	((FLAG) == TIM_FLAG_CC2) \|\| \
mbed_official	87:085cde657901	647	((FLAG) == TIM_FLAG_CC3) \|\| \
mbed_official	87:085cde657901	648	((FLAG) == TIM_FLAG_CC4) \|\| \
mbed_official	87:085cde657901	649	((FLAG) == TIM_FLAG_COM) \|\| \
mbed_official	87:085cde657901	650	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
mbed_official	87:085cde657901	651	((FLAG) == TIM_FLAG_BREAK) \|\| \
mbed_official	87:085cde657901	652	((FLAG) == TIM_FLAG_CC1OF) \|\| \
mbed_official	87:085cde657901	653	((FLAG) == TIM_FLAG_CC2OF) \|\| \
mbed_official	87:085cde657901	654	((FLAG) == TIM_FLAG_CC3OF) \|\| \
mbed_official	226:b062af740e40	655	((FLAG) == TIM_FLAG_CC4OF))
mbed_official	87:085cde657901	656	/**
mbed_official	87:085cde657901	657	* @}
mbed_official	87:085cde657901	658	*/
mbed_official	87:085cde657901	659
mbed_official	87:085cde657901	660	/** @defgroup TIM_Clock_Source
mbed_official	87:085cde657901	661	* @{
mbed_official	226:b062af740e40	662	*/
mbed_official	87:085cde657901	663	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	87:085cde657901	664	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	87:085cde657901	665	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	87:085cde657901	666	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	87:085cde657901	667	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	87:085cde657901	668	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	87:085cde657901	669	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	87:085cde657901	670	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	87:085cde657901	671	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	87:085cde657901	672	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	87:085cde657901	673
mbed_official	87:085cde657901	674	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	87:085cde657901	675	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	87:085cde657901	676	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	87:085cde657901	677	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	87:085cde657901	678	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	87:085cde657901	679	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	87:085cde657901	680	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	87:085cde657901	681	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	87:085cde657901	682	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	87:085cde657901	683	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	87:085cde657901	684	/**
mbed_official	87:085cde657901	685	* @}
mbed_official	226:b062af740e40	686	*/
mbed_official	87:085cde657901	687
mbed_official	87:085cde657901	688	/** @defgroup TIM_Clock_Polarity
mbed_official	87:085cde657901	689	* @{
mbed_official	87:085cde657901	690	*/
mbed_official	87:085cde657901	691	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	87:085cde657901	692	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	87:085cde657901	693	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	87:085cde657901	694	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	87:085cde657901	695	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	87:085cde657901	696
mbed_official	87:085cde657901	697	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	87:085cde657901	698	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	87:085cde657901	699	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	87:085cde657901	700	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	87:085cde657901	701	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	87:085cde657901	702	/**
mbed_official	87:085cde657901	703	* @}
mbed_official	87:085cde657901	704	*/
mbed_official	226:b062af740e40	705
mbed_official	87:085cde657901	706	/** @defgroup TIM_Clock_Prescaler
mbed_official	87:085cde657901	707	* @{
mbed_official	226:b062af740e40	708	*/
mbed_official	87:085cde657901	709	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	87:085cde657901	710	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	87:085cde657901	711	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	87:085cde657901	712	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	87:085cde657901	713
mbed_official	87:085cde657901	714	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	87:085cde657901	715	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	87:085cde657901	716	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	87:085cde657901	717	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	87:085cde657901	718	/**
mbed_official	87:085cde657901	719	* @}
mbed_official	226:b062af740e40	720	*/
mbed_official	226:b062af740e40	721
mbed_official	87:085cde657901	722	/** @defgroup TIM_Clock_Filter
mbed_official	87:085cde657901	723	* @{
mbed_official	87:085cde657901	724	*/
mbed_official	87:085cde657901	725	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	87:085cde657901	726	/**
mbed_official	87:085cde657901	727	* @}
mbed_official	226:b062af740e40	728	*/
mbed_official	87:085cde657901	729
mbed_official	87:085cde657901	730	/** @defgroup TIM_ClearInput_Source
mbed_official	87:085cde657901	731	* @{
mbed_official	87:085cde657901	732	*/
mbed_official	87:085cde657901	733	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	87:085cde657901	734	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	87:085cde657901	735
mbed_official	87:085cde657901	736	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
mbed_official	87:085cde657901	737	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official	87:085cde657901	738	/**
mbed_official	87:085cde657901	739	* @}
mbed_official	87:085cde657901	740	*/
mbed_official	87:085cde657901	741
mbed_official	87:085cde657901	742	/** @defgroup TIM_ClearInput_Polarity
mbed_official	87:085cde657901	743	* @{
mbed_official	87:085cde657901	744	*/
mbed_official	87:085cde657901	745	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	87:085cde657901	746	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	87:085cde657901	747	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	87:085cde657901	748	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	87:085cde657901	749	/**
mbed_official	87:085cde657901	750	* @}
mbed_official	226:b062af740e40	751	*/
mbed_official	87:085cde657901	752
mbed_official	87:085cde657901	753	/** @defgroup TIM_ClearInput_Prescaler
mbed_official	87:085cde657901	754	* @{
mbed_official	87:085cde657901	755	*/
mbed_official	87:085cde657901	756	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	87:085cde657901	757	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	87:085cde657901	758	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	87:085cde657901	759	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	87:085cde657901	760	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	87:085cde657901	761	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	87:085cde657901	762	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	87:085cde657901	763	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	87:085cde657901	764	/**
mbed_official	87:085cde657901	765	* @}
mbed_official	87:085cde657901	766	*/
mbed_official	226:b062af740e40	767
mbed_official	87:085cde657901	768	/** @defgroup TIM_ClearInput_Filter
mbed_official	87:085cde657901	769	* @{
mbed_official	87:085cde657901	770	*/
mbed_official	87:085cde657901	771	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	87:085cde657901	772	/**
mbed_official	87:085cde657901	773	* @}
mbed_official	87:085cde657901	774	*/
mbed_official	87:085cde657901	775
mbed_official	369:2e96f1b71984	776	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
mbed_official	369:2e96f1b71984	777	* @{
mbed_official	369:2e96f1b71984	778	*/
mbed_official	369:2e96f1b71984	779	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
mbed_official	369:2e96f1b71984	780	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	781
mbed_official	369:2e96f1b71984	782	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
mbed_official	369:2e96f1b71984	783	((STATE) == TIM_OSSR_DISABLE))
mbed_official	369:2e96f1b71984	784	/**
mbed_official	369:2e96f1b71984	785	* @}
mbed_official	369:2e96f1b71984	786	*/
mbed_official	369:2e96f1b71984	787
mbed_official	369:2e96f1b71984	788	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
mbed_official	369:2e96f1b71984	789	* @{
mbed_official	369:2e96f1b71984	790	*/
mbed_official	369:2e96f1b71984	791	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
mbed_official	369:2e96f1b71984	792	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	793
mbed_official	369:2e96f1b71984	794	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
mbed_official	369:2e96f1b71984	795	((STATE) == TIM_OSSI_DISABLE))
mbed_official	369:2e96f1b71984	796	/**
mbed_official	369:2e96f1b71984	797	* @}
mbed_official	369:2e96f1b71984	798	*/
mbed_official	369:2e96f1b71984	799	/** @defgroup TIM_Lock_level
mbed_official	369:2e96f1b71984	800	* @{
mbed_official	369:2e96f1b71984	801	*/
mbed_official	369:2e96f1b71984	802	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	803	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
mbed_official	369:2e96f1b71984	804	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
mbed_official	369:2e96f1b71984	805	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
mbed_official	369:2e96f1b71984	806
mbed_official	369:2e96f1b71984	807	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
mbed_official	369:2e96f1b71984	808	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
mbed_official	369:2e96f1b71984	809	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
mbed_official	369:2e96f1b71984	810	((LEVEL) == TIM_LOCKLEVEL_3))
mbed_official	369:2e96f1b71984	811	/**
mbed_official	369:2e96f1b71984	812	* @}
mbed_official	369:2e96f1b71984	813	*/
mbed_official	369:2e96f1b71984	814	/** @defgroup TIM_Break_Input_enable_disable
mbed_official	369:2e96f1b71984	815	* @{
mbed_official	369:2e96f1b71984	816	*/
mbed_official	369:2e96f1b71984	817	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
mbed_official	369:2e96f1b71984	818	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	819
mbed_official	369:2e96f1b71984	820	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
mbed_official	369:2e96f1b71984	821	((STATE) == TIM_BREAK_DISABLE))
mbed_official	369:2e96f1b71984	822	/**
mbed_official	369:2e96f1b71984	823	* @}
mbed_official	369:2e96f1b71984	824	*/
mbed_official	369:2e96f1b71984	825	/** @defgroup TIM_Break_Polarity
mbed_official	369:2e96f1b71984	826	* @{
mbed_official	369:2e96f1b71984	827	*/
mbed_official	369:2e96f1b71984	828	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	829	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
mbed_official	369:2e96f1b71984	830
mbed_official	369:2e96f1b71984	831	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
mbed_official	369:2e96f1b71984	832	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
mbed_official	369:2e96f1b71984	833	/**
mbed_official	369:2e96f1b71984	834	* @}
mbed_official	369:2e96f1b71984	835	*/
mbed_official	369:2e96f1b71984	836	/** @defgroup TIM_AOE_Bit_Set_Reset
mbed_official	369:2e96f1b71984	837	* @{
mbed_official	369:2e96f1b71984	838	*/
mbed_official	369:2e96f1b71984	839	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
mbed_official	369:2e96f1b71984	840	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	841
mbed_official	369:2e96f1b71984	842	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
mbed_official	369:2e96f1b71984	843	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
mbed_official	369:2e96f1b71984	844	/**
mbed_official	369:2e96f1b71984	845	* @}
mbed_official	369:2e96f1b71984	846	*/
mbed_official	369:2e96f1b71984	847
mbed_official	369:2e96f1b71984	848	/** @defgroup TIM_Master_Mode_Selection
mbed_official	369:2e96f1b71984	849	* @{
mbed_official	369:2e96f1b71984	850	*/
mbed_official	369:2e96f1b71984	851	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	852	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	369:2e96f1b71984	853	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	369:2e96f1b71984	854	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	369:2e96f1b71984	855	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	369:2e96f1b71984	856	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	369:2e96f1b71984	857	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	369:2e96f1b71984	858	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	369:2e96f1b71984	859
mbed_official	369:2e96f1b71984	860	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	369:2e96f1b71984	861	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	369:2e96f1b71984	862	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	369:2e96f1b71984	863	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	369:2e96f1b71984	864	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	369:2e96f1b71984	865	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	369:2e96f1b71984	866	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	369:2e96f1b71984	867	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	369:2e96f1b71984	868
mbed_official	369:2e96f1b71984	869
mbed_official	369:2e96f1b71984	870	/**
mbed_official	369:2e96f1b71984	871	* @}
mbed_official	369:2e96f1b71984	872	*/
mbed_official	87:085cde657901	873	/** @defgroup TIM_Slave_Mode
mbed_official	87:085cde657901	874	* @{
mbed_official	87:085cde657901	875	*/
mbed_official	87:085cde657901	876	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	877	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	87:085cde657901	878	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	87:085cde657901	879	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	87:085cde657901	880	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	87:085cde657901	881
mbed_official	87:085cde657901	882	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	87:085cde657901	883	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	87:085cde657901	884	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	87:085cde657901	885	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	87:085cde657901	886	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	87:085cde657901	887	/**
mbed_official	87:085cde657901	888	* @}
mbed_official	87:085cde657901	889	*/
mbed_official	87:085cde657901	890
mbed_official	369:2e96f1b71984	891	/** @defgroup TIM_Master_Slave_Mode
mbed_official	369:2e96f1b71984	892	* @{
mbed_official	369:2e96f1b71984	893	*/
mbed_official	369:2e96f1b71984	894
mbed_official	369:2e96f1b71984	895	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	369:2e96f1b71984	896	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	369:2e96f1b71984	897	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	369:2e96f1b71984	898	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	369:2e96f1b71984	899	/**
mbed_official	369:2e96f1b71984	900	* @}
mbed_official	369:2e96f1b71984	901	*/
mbed_official	87:085cde657901	902	/** @defgroup TIM_Trigger_Selection
mbed_official	87:085cde657901	903	* @{
mbed_official	87:085cde657901	904	*/
mbed_official	87:085cde657901	905	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	87:085cde657901	906	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	87:085cde657901	907	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	87:085cde657901	908	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	87:085cde657901	909	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	87:085cde657901	910	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	87:085cde657901	911	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	87:085cde657901	912	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	87:085cde657901	913	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	87:085cde657901	914	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	87:085cde657901	915	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	87:085cde657901	916	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	87:085cde657901	917	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	87:085cde657901	918	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	87:085cde657901	919	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	87:085cde657901	920	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	87:085cde657901	921	((SELECTION) == TIM_TS_ETRF))
mbed_official	87:085cde657901	922	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	87:085cde657901	923	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	87:085cde657901	924	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	87:085cde657901	925	((SELECTION) == TIM_TS_ITR3))
mbed_official	87:085cde657901	926	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	87:085cde657901	927	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	87:085cde657901	928	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	87:085cde657901	929	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	87:085cde657901	930	((SELECTION) == TIM_TS_NONE))
mbed_official	87:085cde657901	931	/**
mbed_official	87:085cde657901	932	* @}
mbed_official	87:085cde657901	933	*/
mbed_official	87:085cde657901	934
mbed_official	87:085cde657901	935	/** @defgroup TIM_Trigger_Polarity
mbed_official	87:085cde657901	936	* @{
mbed_official	87:085cde657901	937	*/
mbed_official	87:085cde657901	938	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	87:085cde657901	939	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	87:085cde657901	940	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	87:085cde657901	941	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	87:085cde657901	942	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	87:085cde657901	943
mbed_official	87:085cde657901	944	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	87:085cde657901	945	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	87:085cde657901	946	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	87:085cde657901	947	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	87:085cde657901	948	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	87:085cde657901	949	/**
mbed_official	87:085cde657901	950	* @}
mbed_official	87:085cde657901	951	*/
mbed_official	87:085cde657901	952
mbed_official	87:085cde657901	953	/** @defgroup TIM_Trigger_Prescaler
mbed_official	87:085cde657901	954	* @{
mbed_official	226:b062af740e40	955	*/
mbed_official	87:085cde657901	956	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	87:085cde657901	957	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	87:085cde657901	958	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	87:085cde657901	959	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	87:085cde657901	960
mbed_official	87:085cde657901	961	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	87:085cde657901	962	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	87:085cde657901	963	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	87:085cde657901	964	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	87:085cde657901	965	/**
mbed_official	87:085cde657901	966	* @}
mbed_official	87:085cde657901	967	*/
mbed_official	87:085cde657901	968
mbed_official	87:085cde657901	969	/** @defgroup TIM_Trigger_Filter
mbed_official	87:085cde657901	970	* @{
mbed_official	87:085cde657901	971	*/
mbed_official	87:085cde657901	972	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	87:085cde657901	973	/**
mbed_official	87:085cde657901	974	* @}
mbed_official	226:b062af740e40	975	*/
mbed_official	87:085cde657901	976
mbed_official	87:085cde657901	977	/** @defgroup TIM_TI1_Selection
mbed_official	87:085cde657901	978	* @{
mbed_official	87:085cde657901	979	*/
mbed_official	87:085cde657901	980	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	87:085cde657901	981	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	87:085cde657901	982
mbed_official	87:085cde657901	983	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	87:085cde657901	984	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	87:085cde657901	985	/**
mbed_official	87:085cde657901	986	* @}
mbed_official	87:085cde657901	987	*/
mbed_official	226:b062af740e40	988
mbed_official	87:085cde657901	989	/** @defgroup TIM_DMA_Base_address
mbed_official	87:085cde657901	990	* @{
mbed_official	87:085cde657901	991	*/
mbed_official	87:085cde657901	992	#define TIM_DMABase_CR1 (0x00000000)
mbed_official	87:085cde657901	993	#define TIM_DMABase_CR2 (0x00000001)
mbed_official	87:085cde657901	994	#define TIM_DMABase_SMCR (0x00000002)
mbed_official	87:085cde657901	995	#define TIM_DMABase_DIER (0x00000003)
mbed_official	87:085cde657901	996	#define TIM_DMABase_SR (0x00000004)
mbed_official	87:085cde657901	997	#define TIM_DMABase_EGR (0x00000005)
mbed_official	87:085cde657901	998	#define TIM_DMABase_CCMR1 (0x00000006)
mbed_official	87:085cde657901	999	#define TIM_DMABase_CCMR2 (0x00000007)
mbed_official	87:085cde657901	1000	#define TIM_DMABase_CCER (0x00000008)
mbed_official	87:085cde657901	1001	#define TIM_DMABase_CNT (0x00000009)
mbed_official	87:085cde657901	1002	#define TIM_DMABase_PSC (0x0000000A)
mbed_official	87:085cde657901	1003	#define TIM_DMABase_ARR (0x0000000B)
mbed_official	87:085cde657901	1004	#define TIM_DMABase_RCR (0x0000000C)
mbed_official	87:085cde657901	1005	#define TIM_DMABase_CCR1 (0x0000000D)
mbed_official	87:085cde657901	1006	#define TIM_DMABase_CCR2 (0x0000000E)
mbed_official	87:085cde657901	1007	#define TIM_DMABase_CCR3 (0x0000000F)
mbed_official	87:085cde657901	1008	#define TIM_DMABase_CCR4 (0x00000010)
mbed_official	87:085cde657901	1009	#define TIM_DMABase_BDTR (0x00000011)
mbed_official	87:085cde657901	1010	#define TIM_DMABase_DCR (0x00000012)
mbed_official	87:085cde657901	1011	#define TIM_DMABase_OR (0x00000013)
mbed_official	87:085cde657901	1012	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
mbed_official	87:085cde657901	1013	((BASE) == TIM_DMABase_CR2) \|\| \
mbed_official	87:085cde657901	1014	((BASE) == TIM_DMABase_SMCR) \|\| \
mbed_official	87:085cde657901	1015	((BASE) == TIM_DMABase_DIER) \|\| \
mbed_official	87:085cde657901	1016	((BASE) == TIM_DMABase_SR) \|\| \
mbed_official	87:085cde657901	1017	((BASE) == TIM_DMABase_EGR) \|\| \
mbed_official	87:085cde657901	1018	((BASE) == TIM_DMABase_CCMR1) \|\| \
mbed_official	87:085cde657901	1019	((BASE) == TIM_DMABase_CCMR2) \|\| \
mbed_official	87:085cde657901	1020	((BASE) == TIM_DMABase_CCER) \|\| \
mbed_official	87:085cde657901	1021	((BASE) == TIM_DMABase_CNT) \|\| \
mbed_official	87:085cde657901	1022	((BASE) == TIM_DMABase_PSC) \|\| \
mbed_official	87:085cde657901	1023	((BASE) == TIM_DMABase_ARR) \|\| \
mbed_official	87:085cde657901	1024	((BASE) == TIM_DMABase_RCR) \|\| \
mbed_official	87:085cde657901	1025	((BASE) == TIM_DMABase_CCR1) \|\| \
mbed_official	87:085cde657901	1026	((BASE) == TIM_DMABase_CCR2) \|\| \
mbed_official	87:085cde657901	1027	((BASE) == TIM_DMABase_CCR3) \|\| \
mbed_official	87:085cde657901	1028	((BASE) == TIM_DMABase_CCR4) \|\| \
mbed_official	87:085cde657901	1029	((BASE) == TIM_DMABase_BDTR) \|\| \
mbed_official	87:085cde657901	1030	((BASE) == TIM_DMABase_DCR) \|\| \
mbed_official	226:b062af740e40	1031	((BASE) == TIM_DMABase_OR))
mbed_official	87:085cde657901	1032	/**
mbed_official	87:085cde657901	1033	* @}
mbed_official	87:085cde657901	1034	*/
mbed_official	87:085cde657901	1035
mbed_official	87:085cde657901	1036	/** @defgroup TIM_DMA_Burst_Length
mbed_official	87:085cde657901	1037	* @{
mbed_official	87:085cde657901	1038	*/
mbed_official	87:085cde657901	1039	#define TIM_DMABurstLength_1Transfer (0x00000000)
mbed_official	87:085cde657901	1040	#define TIM_DMABurstLength_2Transfers (0x00000100)
mbed_official	87:085cde657901	1041	#define TIM_DMABurstLength_3Transfers (0x00000200)
mbed_official	87:085cde657901	1042	#define TIM_DMABurstLength_4Transfers (0x00000300)
mbed_official	87:085cde657901	1043	#define TIM_DMABurstLength_5Transfers (0x00000400)
mbed_official	87:085cde657901	1044	#define TIM_DMABurstLength_6Transfers (0x00000500)
mbed_official	87:085cde657901	1045	#define TIM_DMABurstLength_7Transfers (0x00000600)
mbed_official	87:085cde657901	1046	#define TIM_DMABurstLength_8Transfers (0x00000700)
mbed_official	87:085cde657901	1047	#define TIM_DMABurstLength_9Transfers (0x00000800)
mbed_official	87:085cde657901	1048	#define TIM_DMABurstLength_10Transfers (0x00000900)
mbed_official	87:085cde657901	1049	#define TIM_DMABurstLength_11Transfers (0x00000A00)
mbed_official	87:085cde657901	1050	#define TIM_DMABurstLength_12Transfers (0x00000B00)
mbed_official	87:085cde657901	1051	#define TIM_DMABurstLength_13Transfers (0x00000C00)
mbed_official	87:085cde657901	1052	#define TIM_DMABurstLength_14Transfers (0x00000D00)
mbed_official	87:085cde657901	1053	#define TIM_DMABurstLength_15Transfers (0x00000E00)
mbed_official	87:085cde657901	1054	#define TIM_DMABurstLength_16Transfers (0x00000F00)
mbed_official	87:085cde657901	1055	#define TIM_DMABurstLength_17Transfers (0x00001000)
mbed_official	87:085cde657901	1056	#define TIM_DMABurstLength_18Transfers (0x00001100)
mbed_official	87:085cde657901	1057	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
mbed_official	87:085cde657901	1058	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
mbed_official	87:085cde657901	1059	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
mbed_official	87:085cde657901	1060	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
mbed_official	87:085cde657901	1061	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
mbed_official	87:085cde657901	1062	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
mbed_official	87:085cde657901	1063	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
mbed_official	87:085cde657901	1064	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
mbed_official	87:085cde657901	1065	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
mbed_official	87:085cde657901	1066	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
mbed_official	87:085cde657901	1067	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
mbed_official	87:085cde657901	1068	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
mbed_official	87:085cde657901	1069	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
mbed_official	87:085cde657901	1070	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
mbed_official	87:085cde657901	1071	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
mbed_official	87:085cde657901	1072	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
mbed_official	87:085cde657901	1073	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
mbed_official	87:085cde657901	1074	((LENGTH) == TIM_DMABurstLength_18Transfers))
mbed_official	87:085cde657901	1075	/**
mbed_official	87:085cde657901	1076	* @}
mbed_official	226:b062af740e40	1077	*/
mbed_official	226:b062af740e40	1078
mbed_official	87:085cde657901	1079	/** @defgroup TIM_Input_Capture_Filer_Value
mbed_official	87:085cde657901	1080	* @{
mbed_official	87:085cde657901	1081	*/
mbed_official	87:085cde657901	1082	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	87:085cde657901	1083	/**
mbed_official	87:085cde657901	1084	* @}
mbed_official	87:085cde657901	1085	*/
mbed_official	87:085cde657901	1086
mbed_official	87:085cde657901	1087	/** @defgroup DMA_Handle_index
mbed_official	87:085cde657901	1088	* @{
mbed_official	87:085cde657901	1089	*/
mbed_official	87:085cde657901	1090	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	87:085cde657901	1091	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	87:085cde657901	1092	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	87:085cde657901	1093	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	87:085cde657901	1094	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	87:085cde657901	1095	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
mbed_official	87:085cde657901	1096	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	87:085cde657901	1097	/**
mbed_official	87:085cde657901	1098	* @}
mbed_official	87:085cde657901	1099	*/
mbed_official	87:085cde657901	1100
mbed_official	87:085cde657901	1101	/** @defgroup Channel_CC_State
mbed_official	87:085cde657901	1102	* @{
mbed_official	87:085cde657901	1103	*/
mbed_official	87:085cde657901	1104	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	87:085cde657901	1105	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	1106	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
mbed_official	87:085cde657901	1107	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
mbed_official	87:085cde657901	1108	/**
mbed_official	87:085cde657901	1109	* @}
mbed_official	87:085cde657901	1110	*/
mbed_official	87:085cde657901	1111
mbed_official	87:085cde657901	1112	/**
mbed_official	87:085cde657901	1113	* @}
mbed_official	87:085cde657901	1114	*/
mbed_official	87:085cde657901	1115
mbed_official	87:085cde657901	1116	/* Exported macro ------------------------------------------------------------*/
mbed_official	87:085cde657901	1117
mbed_official	226:b062af740e40	1118	/** @brief Reset TIM handle state
mbed_official	226:b062af740e40	1119	* @param __HANDLE__: TIM handle
mbed_official	226:b062af740e40	1120	* @retval None
mbed_official	226:b062af740e40	1121	*/
mbed_official	226:b062af740e40	1122	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	226:b062af740e40	1123
mbed_official	87:085cde657901	1124	/**
mbed_official	87:085cde657901	1125	* @brief Enable the TIM peripheral.
mbed_official	87:085cde657901	1126	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	1127	* @retval None
mbed_official	87:085cde657901	1128	*/
mbed_official	87:085cde657901	1129	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	87:085cde657901	1130
mbed_official	87:085cde657901	1131	/**
mbed_official	87:085cde657901	1132	* @brief Enable the TIM main Output.
mbed_official	87:085cde657901	1133	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	1134	* @retval None
mbed_official	87:085cde657901	1135	*/
mbed_official	87:085cde657901	1136	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
mbed_official	87:085cde657901	1137
mbed_official	87:085cde657901	1138
mbed_official	87:085cde657901	1139	/* The counter of a timer instance is disabled only if all the CCx and CCxN
mbed_official	87:085cde657901	1140	channels have been disabled */
mbed_official	87:085cde657901	1141	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	87:085cde657901	1142	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
mbed_official	87:085cde657901	1143
mbed_official	87:085cde657901	1144	/**
mbed_official	87:085cde657901	1145	* @brief Disable the TIM peripheral.
mbed_official	87:085cde657901	1146	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	1147	* @retval None
mbed_official	87:085cde657901	1148	*/
mbed_official	87:085cde657901	1149	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	87:085cde657901	1150	do { \
mbed_official	87:085cde657901	1151	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	87:085cde657901	1152	{ \
mbed_official	87:085cde657901	1153	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	87:085cde657901	1154	{ \
mbed_official	87:085cde657901	1155	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	87:085cde657901	1156	} \
mbed_official	87:085cde657901	1157	} \
mbed_official	87:085cde657901	1158	} while(0)
mbed_official	87:085cde657901	1159
mbed_official	226:b062af740e40	1160	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
mbed_official	226:b062af740e40	1161	channels have been disabled */
mbed_official	87:085cde657901	1162	/**
mbed_official	87:085cde657901	1163	* @brief Disable the TIM main Output.
mbed_official	87:085cde657901	1164	* @param __HANDLE__: TIM handle
mbed_official	87:085cde657901	1165	* @retval None
mbed_official	87:085cde657901	1166	*/
mbed_official	87:085cde657901	1167	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
mbed_official	87:085cde657901	1168	do { \
mbed_official	87:085cde657901	1169	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	87:085cde657901	1170	{ \
mbed_official	87:085cde657901	1171	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	87:085cde657901	1172	{ \
mbed_official	87:085cde657901	1173	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
mbed_official	87:085cde657901	1174	} \
mbed_official	87:085cde657901	1175	} \
mbed_official	226:b062af740e40	1176	} while(0)
mbed_official	87:085cde657901	1177
mbed_official	87:085cde657901	1178	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	87:085cde657901	1179	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	87:085cde657901	1180	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	87:085cde657901	1181	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	87:085cde657901	1182	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	369:2e96f1b71984	1183	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
mbed_official	87:085cde657901	1184
mbed_official	87:085cde657901	1185	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	369:2e96f1b71984	1186	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
mbed_official	87:085cde657901	1187
mbed_official	87:085cde657901	1188	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	369:2e96f1b71984	1189	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
mbed_official	87:085cde657901	1190
mbed_official	87:085cde657901	1191	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	87:085cde657901	1192	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	87:085cde657901	1193	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	87:085cde657901	1194	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	87:085cde657901	1195	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	87:085cde657901	1196
mbed_official	87:085cde657901	1197	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
mbed_official	87:085cde657901	1198	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
mbed_official	87:085cde657901	1199	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
mbed_official	87:085cde657901	1200	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
mbed_official	87:085cde657901	1201	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
mbed_official	226:b062af740e40	1202
mbed_official	87:085cde657901	1203	/**
mbed_official	87:085cde657901	1204	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	87:085cde657901	1205	* calling another time ConfigChannel function.
mbed_official	87:085cde657901	1206	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	1207	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	87:085cde657901	1208	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1209	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1210	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1211	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1212	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1213	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	87:085cde657901	1214	* @retval None
mbed_official	87:085cde657901	1215	*/
mbed_official	87:085cde657901	1216	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	87:085cde657901	1217	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	87:085cde657901	1218
mbed_official	87:085cde657901	1219	/**
mbed_official	226:b062af740e40	1220	* @brief Gets the TIM Capture Compare Register value on runtime
mbed_official	226:b062af740e40	1221	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1222	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official	226:b062af740e40	1223	* This parameter can be one of the following values:
mbed_official	226:b062af740e40	1224	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official	226:b062af740e40	1225	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official	226:b062af740e40	1226	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official	226:b062af740e40	1227	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official	226:b062af740e40	1228	* @retval None
mbed_official	226:b062af740e40	1229	*/
mbed_official	226:b062af740e40	1230	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
mbed_official	226:b062af740e40	1231	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official	226:b062af740e40	1232
mbed_official	226:b062af740e40	1233	/**
mbed_official	87:085cde657901	1234	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	87:085cde657901	1235	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	1236	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	87:085cde657901	1237	* @retval None
mbed_official	87:085cde657901	1238	*/
mbed_official	226:b062af740e40	1239	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	226:b062af740e40	1240
mbed_official	226:b062af740e40	1241	/**
mbed_official	226:b062af740e40	1242	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	226:b062af740e40	1243	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1244	* @retval None
mbed_official	226:b062af740e40	1245	*/
mbed_official	226:b062af740e40	1246	#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
mbed_official	87:085cde657901	1247
mbed_official	87:085cde657901	1248	/**
mbed_official	87:085cde657901	1249	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	87:085cde657901	1250	* another time any Init function.
mbed_official	87:085cde657901	1251	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	1252	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	87:085cde657901	1253	* @retval None
mbed_official	87:085cde657901	1254	*/
mbed_official	226:b062af740e40	1255	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
mbed_official	226:b062af740e40	1256	do{ \
mbed_official	226:b062af740e40	1257	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	226:b062af740e40	1258	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	87:085cde657901	1259	} while(0)
mbed_official	226:b062af740e40	1260	/**
mbed_official	226:b062af740e40	1261	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	226:b062af740e40	1262	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1263	* @retval None
mbed_official	226:b062af740e40	1264	*/
mbed_official	226:b062af740e40	1265	#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
mbed_official	87:085cde657901	1266
mbed_official	87:085cde657901	1267	/**
mbed_official	87:085cde657901	1268	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	87:085cde657901	1269	* another time any Init function.
mbed_official	87:085cde657901	1270	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	1271	* @param __CKD__: specifies the clock division value.
mbed_official	87:085cde657901	1272	* This parameter can be one of the following value:
mbed_official	87:085cde657901	1273	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	87:085cde657901	1274	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	226:b062af740e40	1275	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	87:085cde657901	1276	* @retval None
mbed_official	87:085cde657901	1277	*/
mbed_official	87:085cde657901	1278	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
mbed_official	226:b062af740e40	1279	do{ \
mbed_official	87:085cde657901	1280	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
mbed_official	226:b062af740e40	1281	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	87:085cde657901	1282	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	87:085cde657901	1283	} while(0)
mbed_official	226:b062af740e40	1284	/**
mbed_official	226:b062af740e40	1285	* @brief Gets the TIM Clock Division value on runtime
mbed_official	226:b062af740e40	1286	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1287	* @retval None
mbed_official	226:b062af740e40	1288	*/
mbed_official	226:b062af740e40	1289	#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	226:b062af740e40	1290
mbed_official	87:085cde657901	1291	/**
mbed_official	87:085cde657901	1292	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	87:085cde657901	1293	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	87:085cde657901	1294	* @param __HANDLE__: TIM handle.
mbed_official	87:085cde657901	1295	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	87:085cde657901	1296	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1297	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1298	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1299	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1300	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1301	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	87:085cde657901	1302	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1303	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	87:085cde657901	1304	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	87:085cde657901	1305	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	87:085cde657901	1306	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	87:085cde657901	1307	* @retval None
mbed_official	87:085cde657901	1308	*/
mbed_official	87:085cde657901	1309	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	87:085cde657901	1310	do{ \
mbed_official	87:085cde657901	1311	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
mbed_official	87:085cde657901	1312	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	226:b062af740e40	1313	} while(0)
mbed_official	87:085cde657901	1314
mbed_official	87:085cde657901	1315	/**
mbed_official	226:b062af740e40	1316	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	226:b062af740e40	1317	* @param __HANDLE__: TIM handle.
mbed_official	226:b062af740e40	1318	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	226:b062af740e40	1319	* This parameter can be one of the following values:
mbed_official	226:b062af740e40	1320	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	226:b062af740e40	1321	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	226:b062af740e40	1322	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	226:b062af740e40	1323	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	226:b062af740e40	1324	* @retval None
mbed_official	226:b062af740e40	1325	*/
mbed_official	226:b062af740e40	1326	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
mbed_official	226:b062af740e40	1327	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	226:b062af740e40	1328	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	226:b062af740e40	1329	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	226:b062af740e40	1330	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	226:b062af740e40	1331	/**
mbed_official	87:085cde657901	1332	* @}
mbed_official	87:085cde657901	1333	*/
mbed_official	87:085cde657901	1334
mbed_official	87:085cde657901	1335	/* Include TIM HAL Extension module */
mbed_official	87:085cde657901	1336	#include "stm32f4xx_hal_tim_ex.h"
mbed_official	87:085cde657901	1337
mbed_official	87:085cde657901	1338	/* Exported functions --------------------------------------------------------*/
mbed_official	87:085cde657901	1339
mbed_official	87:085cde657901	1340	/* Time Base functions ********************************************************/
mbed_official	87:085cde657901	1341	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1342	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1343	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1344	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1345	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1346	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1347	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1348	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1349	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1350	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1351	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1352	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1353	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1354
mbed_official	87:085cde657901	1355	/* Timer Output Compare functions **********************************************/
mbed_official	87:085cde657901	1356	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1357	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1358	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1359	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1360	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1361	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1362	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1363	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1364	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1365	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1366	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1367	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1368	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1369
mbed_official	87:085cde657901	1370	/* Timer PWM functions *********************************************************/
mbed_official	87:085cde657901	1371	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1372	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1373	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1374	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1375	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1376	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1377	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1378	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1379	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1380	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1381	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1382	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1383	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1384
mbed_official	87:085cde657901	1385	/* Timer Input Capture functions ***********************************************/
mbed_official	87:085cde657901	1386	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1387	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1388	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1389	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1390	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1391	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1392	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1393	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1394	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1395	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1396	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1397	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	87:085cde657901	1398	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1399
mbed_official	87:085cde657901	1400	/* Timer One Pulse functions ***************************************************/
mbed_official	87:085cde657901	1401	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	87:085cde657901	1402	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1403	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1404	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1405	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1406	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1407	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1408
mbed_official	87:085cde657901	1409	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1410	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1411	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	87:085cde657901	1412
mbed_official	87:085cde657901	1413	/* Timer Encoder functions *****************************************************/
mbed_official	87:085cde657901	1414	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	87:085cde657901	1415	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1416	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1417	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1418	/* Blocking mode: Polling */
mbed_official	87:085cde657901	1419	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1420	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1421	/* Non-Blocking mode: Interrupt */
mbed_official	87:085cde657901	1422	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1423	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1424	/* Non-Blocking mode: DMA */
mbed_official	87:085cde657901	1425	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	87:085cde657901	1426	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1427
mbed_official	87:085cde657901	1428	/* Interrupt Handler functions **********************************************/
mbed_official	87:085cde657901	1429	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1430
mbed_official	87:085cde657901	1431	/* Control functions *********************************************************/
mbed_official	87:085cde657901	1432	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	87:085cde657901	1433	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	87:085cde657901	1434	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	87:085cde657901	1435	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	87:085cde657901	1436	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	87:085cde657901	1437	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	87:085cde657901	1438	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	87:085cde657901	1439	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	87:085cde657901	1440	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	87:085cde657901	1441	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	87:085cde657901	1442	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	87:085cde657901	1443	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	87:085cde657901	1444	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	87:085cde657901	1445	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	87:085cde657901	1446	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	87:085cde657901	1447	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	87:085cde657901	1448
mbed_official	87:085cde657901	1449	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	106:ced8cbb51063	1450	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1451	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1452	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1453	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1454	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	106:ced8cbb51063	1455	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1456
mbed_official	87:085cde657901	1457	/* Peripheral State functions **************************************************/
mbed_official	87:085cde657901	1458	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1459	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1460	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1461	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1462	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1463	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	87:085cde657901	1464
mbed_official	87:085cde657901	1465	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
mbed_official	87:085cde657901	1466	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	1467	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	87:085cde657901	1468	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	1469	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	1470	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	1471	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official	87:085cde657901	1472
mbed_official	87:085cde657901	1473	/**
mbed_official	87:085cde657901	1474	* @}
mbed_official	87:085cde657901	1475	*/
mbed_official	87:085cde657901	1476
mbed_official	87:085cde657901	1477	/**
mbed_official	87:085cde657901	1478	* @}
mbed_official	87:085cde657901	1479	*/
mbed_official	87:085cde657901	1480
mbed_official	87:085cde657901	1481	#ifdef __cplusplus
mbed_official	87:085cde657901	1482	}
mbed_official	87:085cde657901	1483	#endif
mbed_official	87:085cde657901	1484
mbed_official	87:085cde657901	1485	#endif /* __STM32F4xx_HAL_TIM_H */
mbed_official	87:085cde657901	1486
mbed_official	87:085cde657901	1487	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	27 Oct 2015
Imports:	0
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Commits:	637
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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.h@380:510f0c3515e3, 2014-11-03 (annotated)

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