Marek Trojan
/
mbed-dev
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mbed-dev
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mbed official
Revision 106:c405d2eb506d, committed 2016-04-04
- Comitter:
- mbed_official
- Date:
- Mon Apr 04 22:15:11 2016 +0100
- Parent:
- 105:364b35371a11
- Child:
- 107:414e9c822e99
- Commit message:
- Synchronized with git revision e2cb35e9ad726713da701b8a95393473471560b4
Full URL: https://github.com/mbedmicro/mbed/commit/e2cb35e9ad726713da701b8a95393473471560b4/
The erasing of back up register is only needed when using LSI in RTC API
Changed in this revision
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_conf.h Mon Apr 04 11:15:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_conf.h Mon Apr 04 22:15:11 2016 +0100
@@ -121,7 +121,7 @@
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for LSE start up, in ms */
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h Mon Apr 04 11:15:10 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device.h Mon Apr 04 22:15:11 2016 +0100 @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 0 #define DEVICE_PWMOUT 1
--- a/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h Mon Apr 04 11:15:10 2016 +0100 +++ b/targets/hal/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device.h Mon Apr 04 22:15:11 2016 +0100 @@ -48,6 +48,7 @@ #define DEVICE_SPISLAVE 1 #define DEVICE_RTC 1 +#define DEVICE_RTC_LSI 0 #define DEVICE_PWMOUT 1
--- a/targets/hal/TARGET_STM/TARGET_STM32F1/rtc_api.c Mon Apr 04 11:15:10 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F1/rtc_api.c Mon Apr 04 22:15:11 2016 +0100
@@ -46,6 +46,19 @@
RtcHandle.Instance = RTC;
+#if !DEVICE_RTC_LSI
+ // Enable LSE Oscillator
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+ RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { // Check if LSE has started correctly
+ // Connect LSE to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+ } else {
+ error("Cannot initialize RTC with LSE\n");
+ }
+#else
// Enable Power clock
__HAL_RCC_PWR_CLK_ENABLE();
@@ -55,27 +68,20 @@
// Reset Backup domain
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
-
- // Enable LSE Oscillator
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
- RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
- // Connect LSE to RTC
- __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
- } else {
- // Enable LSI clock
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
- RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
- RCC_OscInitStruct.LSIState = RCC_LSI_ON;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- error("RTC error: LSI clock initialization failed.");
- }
- // Connect LSI to RTC
- __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
- }
-
+
+ // Enable LSI clock
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+ RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ error("Cannot initialize RTC with LSI\n");
+ }
+ // Connect LSI to RTC
+ __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+ // This value is LSI typical value. To be measured precisely using a timer input capture for example.
+#endif
+
// Enable RTC
__HAL_RCC_RTC_ENABLE();
@@ -88,6 +94,7 @@
void rtc_free(void)
{
+#if DEVICE_RTC_LSI
// Enable Power clock
__PWR_CLK_ENABLE();
@@ -100,6 +107,7 @@
// Disable access to Backup domain
HAL_PWR_DisableBkUpAccess();
+#endif
// Disable LSI and LSE clocks
RCC_OscInitTypeDef RCC_OscInitStruct;
--- a/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c Mon Apr 04 11:15:10 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32F7/rtc_api.c Mon Apr 04 22:15:11 2016 +0100
@@ -46,16 +46,6 @@
RtcHandle.Instance = RTC;
- // Enable Power clock
- __PWR_CLK_ENABLE();
-
- // Enable access to Backup domain
- HAL_PWR_EnableBkUpAccess();
-
- // Reset Backup domain
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
-
#if !DEVICE_RTC_LSI
// Enable LSE Oscillator
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
@@ -71,6 +61,16 @@
error("Cannot initialize RTC with LSE\n");
}
#else
+ // Enable Power clock
+ __PWR_CLK_ENABLE();
+
+ // Enable access to Backup domain
+ HAL_PWR_EnableBkUpAccess();
+
+ // Reset Backup domain
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
// Enable LSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
@@ -103,6 +103,7 @@
void rtc_free(void)
{
+#if DEVICE_RTC_LSI
// Enable Power clock
__PWR_CLK_ENABLE();
@@ -115,6 +116,7 @@
// Disable access to Backup domain
HAL_PWR_DisableBkUpAccess();
+#endif
// Disable LSI and LSE clocks
RCC_OscInitTypeDef RCC_OscInitStruct;