Marco Zecchini / Mbed OS Example_RTOS

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

mbed-os/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_GCC_ARM/startup_efm32pg12b.S@0:9fca2b23d0ba, 2019-02-23 (annotated)

Committer:
marcozecchini
Date:
Sat Feb 23 12:13:36 2019 +0000
Revision:
0:9fca2b23d0ba
final commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
marcozecchini 0:9fca2b23d0ba 1 /* @file startup_efm32pg12b.S
marcozecchini 0:9fca2b23d0ba 2 * @brief startup file for Silicon Labs EFM32PG12B devices.
marcozecchini 0:9fca2b23d0ba 3 * For use with GCC for ARM Embedded Processors
marcozecchini 0:9fca2b23d0ba 4 * @version 5.1.2
marcozecchini 0:9fca2b23d0ba 5 * Date: 12 June 2014
marcozecchini 0:9fca2b23d0ba 6 *
marcozecchini 0:9fca2b23d0ba 7 */
marcozecchini 0:9fca2b23d0ba 8 /* Copyright (c) 2011 - 2014 ARM LIMITED
marcozecchini 0:9fca2b23d0ba 9
marcozecchini 0:9fca2b23d0ba 10 All rights reserved.
marcozecchini 0:9fca2b23d0ba 11 Redistribution and use in source and binary forms, with or without
marcozecchini 0:9fca2b23d0ba 12 modification, are permitted provided that the following conditions are met:
marcozecchini 0:9fca2b23d0ba 13 - Redistributions of source code must retain the above copyright
marcozecchini 0:9fca2b23d0ba 14 notice, this list of conditions and the following disclaimer.
marcozecchini 0:9fca2b23d0ba 15 - Redistributions in binary form must reproduce the above copyright
marcozecchini 0:9fca2b23d0ba 16 notice, this list of conditions and the following disclaimer in the
marcozecchini 0:9fca2b23d0ba 17 documentation and/or other materials provided with the distribution.
marcozecchini 0:9fca2b23d0ba 18 - Neither the name of ARM nor the names of its contributors may be used
marcozecchini 0:9fca2b23d0ba 19 to endorse or promote products derived from this software without
marcozecchini 0:9fca2b23d0ba 20 specific prior written permission.
marcozecchini 0:9fca2b23d0ba 21 *
marcozecchini 0:9fca2b23d0ba 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
marcozecchini 0:9fca2b23d0ba 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
marcozecchini 0:9fca2b23d0ba 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
marcozecchini 0:9fca2b23d0ba 25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
marcozecchini 0:9fca2b23d0ba 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
marcozecchini 0:9fca2b23d0ba 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
marcozecchini 0:9fca2b23d0ba 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
marcozecchini 0:9fca2b23d0ba 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
marcozecchini 0:9fca2b23d0ba 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
marcozecchini 0:9fca2b23d0ba 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
marcozecchini 0:9fca2b23d0ba 32 POSSIBILITY OF SUCH DAMAGE.
marcozecchini 0:9fca2b23d0ba 33 ---------------------------------------------------------------------------*/
marcozecchini 0:9fca2b23d0ba 34
marcozecchini 0:9fca2b23d0ba 35 .syntax unified
marcozecchini 0:9fca2b23d0ba 36 .arch armv7-m
marcozecchini 0:9fca2b23d0ba 37 .section .stack
marcozecchini 0:9fca2b23d0ba 38 .align 3
marcozecchini 0:9fca2b23d0ba 39 #ifdef __STACK_SIZE
marcozecchini 0:9fca2b23d0ba 40 .equ Stack_Size, __STACK_SIZE
marcozecchini 0:9fca2b23d0ba 41 #else
marcozecchini 0:9fca2b23d0ba 42 .equ Stack_Size, 0x00001000
marcozecchini 0:9fca2b23d0ba 43 #endif
marcozecchini 0:9fca2b23d0ba 44 .globl __StackTop
marcozecchini 0:9fca2b23d0ba 45 .globl __StackLimit
marcozecchini 0:9fca2b23d0ba 46 __StackLimit:
marcozecchini 0:9fca2b23d0ba 47 .space Stack_Size
marcozecchini 0:9fca2b23d0ba 48 .size __StackLimit, . - __StackLimit
marcozecchini 0:9fca2b23d0ba 49 __StackTop:
marcozecchini 0:9fca2b23d0ba 50 .size __StackTop, . - __StackTop
marcozecchini 0:9fca2b23d0ba 51
marcozecchini 0:9fca2b23d0ba 52 .section .heap
marcozecchini 0:9fca2b23d0ba 53 .align 3
marcozecchini 0:9fca2b23d0ba 54 #ifdef __HEAP_SIZE
marcozecchini 0:9fca2b23d0ba 55 .equ Heap_Size, __HEAP_SIZE
marcozecchini 0:9fca2b23d0ba 56 #else
marcozecchini 0:9fca2b23d0ba 57 .equ Heap_Size, 0x00004000
marcozecchini 0:9fca2b23d0ba 58 #endif
marcozecchini 0:9fca2b23d0ba 59 .globl __HeapBase
marcozecchini 0:9fca2b23d0ba 60 .globl __HeapLimit
marcozecchini 0:9fca2b23d0ba 61 __HeapBase:
marcozecchini 0:9fca2b23d0ba 62 .if Heap_Size
marcozecchini 0:9fca2b23d0ba 63 .space Heap_Size
marcozecchini 0:9fca2b23d0ba 64 .endif
marcozecchini 0:9fca2b23d0ba 65 .size __HeapBase, . - __HeapBase
marcozecchini 0:9fca2b23d0ba 66 __HeapLimit:
marcozecchini 0:9fca2b23d0ba 67 .size __HeapLimit, . - __HeapLimit
marcozecchini 0:9fca2b23d0ba 68
marcozecchini 0:9fca2b23d0ba 69 .section .vectors
marcozecchini 0:9fca2b23d0ba 70 .align 2
marcozecchini 0:9fca2b23d0ba 71 .globl __Vectors
marcozecchini 0:9fca2b23d0ba 72 __Vectors:
marcozecchini 0:9fca2b23d0ba 73 .long __StackTop /* Top of Stack */
marcozecchini 0:9fca2b23d0ba 74 .long Reset_Handler /* Reset Handler */
marcozecchini 0:9fca2b23d0ba 75 .long NMI_Handler /* NMI Handler */
marcozecchini 0:9fca2b23d0ba 76 .long HardFault_Handler /* Hard Fault Handler */
marcozecchini 0:9fca2b23d0ba 77 .long MemManage_Handler /* MPU Fault Handler */
marcozecchini 0:9fca2b23d0ba 78 .long BusFault_Handler /* Bus Fault Handler */
marcozecchini 0:9fca2b23d0ba 79 .long UsageFault_Handler /* Usage Fault Handler */
marcozecchini 0:9fca2b23d0ba 80 .long Default_Handler /* Reserved */
marcozecchini 0:9fca2b23d0ba 81 .long Default_Handler /* Reserved */
marcozecchini 0:9fca2b23d0ba 82 .long Default_Handler /* Reserved */
marcozecchini 0:9fca2b23d0ba 83 .long Default_Handler /* Reserved */
marcozecchini 0:9fca2b23d0ba 84 .long SVC_Handler /* SVCall Handler */
marcozecchini 0:9fca2b23d0ba 85 .long DebugMon_Handler /* Debug Monitor Handler */
marcozecchini 0:9fca2b23d0ba 86 .long Default_Handler /* Reserved */
marcozecchini 0:9fca2b23d0ba 87 .long PendSV_Handler /* PendSV Handler */
marcozecchini 0:9fca2b23d0ba 88 .long SysTick_Handler /* SysTick Handler */
marcozecchini 0:9fca2b23d0ba 89
marcozecchini 0:9fca2b23d0ba 90 /* External interrupts */
marcozecchini 0:9fca2b23d0ba 91 .long EMU_IRQHandler /* 0 - EMU */
marcozecchini 0:9fca2b23d0ba 92 .long Default_Handler /* 1 - Reserved */
marcozecchini 0:9fca2b23d0ba 93 .long WDOG0_IRQHandler /* 2 - WDOG0 */
marcozecchini 0:9fca2b23d0ba 94 .long WDOG1_IRQHandler /* 3 - WDOG1 */
marcozecchini 0:9fca2b23d0ba 95 .long Default_Handler /* 4 - Reserved */
marcozecchini 0:9fca2b23d0ba 96 .long Default_Handler /* 5 - Reserved */
marcozecchini 0:9fca2b23d0ba 97 .long Default_Handler /* 6 - Reserved */
marcozecchini 0:9fca2b23d0ba 98 .long Default_Handler /* 7 - Reserved */
marcozecchini 0:9fca2b23d0ba 99 .long Default_Handler /* 8 - Reserved */
marcozecchini 0:9fca2b23d0ba 100 .long LDMA_IRQHandler /* 9 - LDMA */
marcozecchini 0:9fca2b23d0ba 101 .long GPIO_EVEN_IRQHandler /* 10 - GPIO_EVEN */
marcozecchini 0:9fca2b23d0ba 102 .long TIMER0_IRQHandler /* 11 - TIMER0 */
marcozecchini 0:9fca2b23d0ba 103 .long USART0_RX_IRQHandler /* 12 - USART0_RX */
marcozecchini 0:9fca2b23d0ba 104 .long USART0_TX_IRQHandler /* 13 - USART0_TX */
marcozecchini 0:9fca2b23d0ba 105 .long ACMP0_IRQHandler /* 14 - ACMP0 */
marcozecchini 0:9fca2b23d0ba 106 .long ADC0_IRQHandler /* 15 - ADC0 */
marcozecchini 0:9fca2b23d0ba 107 .long IDAC0_IRQHandler /* 16 - IDAC0 */
marcozecchini 0:9fca2b23d0ba 108 .long I2C0_IRQHandler /* 17 - I2C0 */
marcozecchini 0:9fca2b23d0ba 109 .long GPIO_ODD_IRQHandler /* 18 - GPIO_ODD */
marcozecchini 0:9fca2b23d0ba 110 .long TIMER1_IRQHandler /* 19 - TIMER1 */
marcozecchini 0:9fca2b23d0ba 111 .long USART1_RX_IRQHandler /* 20 - USART1_RX */
marcozecchini 0:9fca2b23d0ba 112 .long USART1_TX_IRQHandler /* 21 - USART1_TX */
marcozecchini 0:9fca2b23d0ba 113 .long LEUART0_IRQHandler /* 22 - LEUART0 */
marcozecchini 0:9fca2b23d0ba 114 .long PCNT0_IRQHandler /* 23 - PCNT0 */
marcozecchini 0:9fca2b23d0ba 115 .long CMU_IRQHandler /* 24 - CMU */
marcozecchini 0:9fca2b23d0ba 116 .long MSC_IRQHandler /* 25 - MSC */
marcozecchini 0:9fca2b23d0ba 117 .long CRYPTO0_IRQHandler /* 26 - CRYPTO0 */
marcozecchini 0:9fca2b23d0ba 118 .long LETIMER0_IRQHandler /* 27 - LETIMER0 */
marcozecchini 0:9fca2b23d0ba 119 .long Default_Handler /* 28 - Reserved */
marcozecchini 0:9fca2b23d0ba 120 .long Default_Handler /* 29 - Reserved */
marcozecchini 0:9fca2b23d0ba 121 .long RTCC_IRQHandler /* 30 - RTCC */
marcozecchini 0:9fca2b23d0ba 122 .long Default_Handler /* 31 - Reserved */
marcozecchini 0:9fca2b23d0ba 123 .long CRYOTIMER_IRQHandler /* 32 - CRYOTIMER */
marcozecchini 0:9fca2b23d0ba 124 .long Default_Handler /* 33 - Reserved */
marcozecchini 0:9fca2b23d0ba 125 .long FPUEH_IRQHandler /* 34 - FPUEH */
marcozecchini 0:9fca2b23d0ba 126 .long SMU_IRQHandler /* 35 - SMU */
marcozecchini 0:9fca2b23d0ba 127 .long WTIMER0_IRQHandler /* 36 - WTIMER0 */
marcozecchini 0:9fca2b23d0ba 128 .long WTIMER1_IRQHandler /* 37 - WTIMER1 */
marcozecchini 0:9fca2b23d0ba 129 .long PCNT1_IRQHandler /* 38 - PCNT1 */
marcozecchini 0:9fca2b23d0ba 130 .long PCNT2_IRQHandler /* 39 - PCNT2 */
marcozecchini 0:9fca2b23d0ba 131 .long USART2_RX_IRQHandler /* 40 - USART2_RX */
marcozecchini 0:9fca2b23d0ba 132 .long USART2_TX_IRQHandler /* 41 - USART2_TX */
marcozecchini 0:9fca2b23d0ba 133 .long I2C1_IRQHandler /* 42 - I2C1 */
marcozecchini 0:9fca2b23d0ba 134 .long USART3_RX_IRQHandler /* 43 - USART3_RX */
marcozecchini 0:9fca2b23d0ba 135 .long USART3_TX_IRQHandler /* 44 - USART3_TX */
marcozecchini 0:9fca2b23d0ba 136 .long VDAC0_IRQHandler /* 45 - VDAC0 */
marcozecchini 0:9fca2b23d0ba 137 .long CSEN_IRQHandler /* 46 - CSEN */
marcozecchini 0:9fca2b23d0ba 138 .long LESENSE_IRQHandler /* 47 - LESENSE */
marcozecchini 0:9fca2b23d0ba 139 .long CRYPTO1_IRQHandler /* 48 - CRYPTO1 */
marcozecchini 0:9fca2b23d0ba 140 .long TRNG0_IRQHandler /* 49 - TRNG0 */
marcozecchini 0:9fca2b23d0ba 141 .long Default_Handler /* 50 - Reserved */
marcozecchini 0:9fca2b23d0ba 142
marcozecchini 0:9fca2b23d0ba 143
marcozecchini 0:9fca2b23d0ba 144 .size __Vectors, . - __Vectors
marcozecchini 0:9fca2b23d0ba 145
marcozecchini 0:9fca2b23d0ba 146 .text
marcozecchini 0:9fca2b23d0ba 147 .thumb
marcozecchini 0:9fca2b23d0ba 148 .thumb_func
marcozecchini 0:9fca2b23d0ba 149 .align 2
marcozecchini 0:9fca2b23d0ba 150 .globl Reset_Handler
marcozecchini 0:9fca2b23d0ba 151 .type Reset_Handler, %function
marcozecchini 0:9fca2b23d0ba 152 Reset_Handler:
marcozecchini 0:9fca2b23d0ba 153 #ifndef __NO_SYSTEM_INIT
marcozecchini 0:9fca2b23d0ba 154 ldr r0, =SystemInit
marcozecchini 0:9fca2b23d0ba 155 blx r0
marcozecchini 0:9fca2b23d0ba 156 #endif
marcozecchini 0:9fca2b23d0ba 157
marcozecchini 0:9fca2b23d0ba 158 /* Firstly it copies data from read only memory to RAM. There are two schemes
marcozecchini 0:9fca2b23d0ba 159 * to copy. One can copy more than one sections. Another can only copy
marcozecchini 0:9fca2b23d0ba 160 * one section. The former scheme needs more instructions and read-only
marcozecchini 0:9fca2b23d0ba 161 * data to implement than the latter.
marcozecchini 0:9fca2b23d0ba 162 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
marcozecchini 0:9fca2b23d0ba 163
marcozecchini 0:9fca2b23d0ba 164 #ifdef __STARTUP_COPY_MULTIPLE
marcozecchini 0:9fca2b23d0ba 165 /* Multiple sections scheme.
marcozecchini 0:9fca2b23d0ba 166 *
marcozecchini 0:9fca2b23d0ba 167 * Between symbol address __copy_table_start__ and __copy_table_end__,
marcozecchini 0:9fca2b23d0ba 168 * there are array of triplets, each of which specify:
marcozecchini 0:9fca2b23d0ba 169 * offset 0: LMA of start of a section to copy from
marcozecchini 0:9fca2b23d0ba 170 * offset 4: VMA of start of a section to copy to
marcozecchini 0:9fca2b23d0ba 171 * offset 8: size of the section to copy. Must be multiply of 4
marcozecchini 0:9fca2b23d0ba 172 *
marcozecchini 0:9fca2b23d0ba 173 * All addresses must be aligned to 4 bytes boundary.
marcozecchini 0:9fca2b23d0ba 174 */
marcozecchini 0:9fca2b23d0ba 175 ldr r4, =__copy_table_start__
marcozecchini 0:9fca2b23d0ba 176 ldr r5, =__copy_table_end__
marcozecchini 0:9fca2b23d0ba 177
marcozecchini 0:9fca2b23d0ba 178 .L_loop0:
marcozecchini 0:9fca2b23d0ba 179 cmp r4, r5
marcozecchini 0:9fca2b23d0ba 180 bge .L_loop0_done
marcozecchini 0:9fca2b23d0ba 181 ldr r1, [r4]
marcozecchini 0:9fca2b23d0ba 182 ldr r2, [r4, #4]
marcozecchini 0:9fca2b23d0ba 183 ldr r3, [r4, #8]
marcozecchini 0:9fca2b23d0ba 184
marcozecchini 0:9fca2b23d0ba 185 .L_loop0_0:
marcozecchini 0:9fca2b23d0ba 186 subs r3, #4
marcozecchini 0:9fca2b23d0ba 187 ittt ge
marcozecchini 0:9fca2b23d0ba 188 ldrge r0, [r1, r3]
marcozecchini 0:9fca2b23d0ba 189 strge r0, [r2, r3]
marcozecchini 0:9fca2b23d0ba 190 bge .L_loop0_0
marcozecchini 0:9fca2b23d0ba 191
marcozecchini 0:9fca2b23d0ba 192 adds r4, #12
marcozecchini 0:9fca2b23d0ba 193 b .L_loop0
marcozecchini 0:9fca2b23d0ba 194
marcozecchini 0:9fca2b23d0ba 195 .L_loop0_done:
marcozecchini 0:9fca2b23d0ba 196 #else
marcozecchini 0:9fca2b23d0ba 197 /* Single section scheme.
marcozecchini 0:9fca2b23d0ba 198 *
marcozecchini 0:9fca2b23d0ba 199 * The ranges of copy from/to are specified by following symbols
marcozecchini 0:9fca2b23d0ba 200 * __etext: LMA of start of the section to copy from. Usually end of text
marcozecchini 0:9fca2b23d0ba 201 * __data_start__: VMA of start of the section to copy to
marcozecchini 0:9fca2b23d0ba 202 * __data_end__: VMA of end of the section to copy to
marcozecchini 0:9fca2b23d0ba 203 *
marcozecchini 0:9fca2b23d0ba 204 * All addresses must be aligned to 4 bytes boundary.
marcozecchini 0:9fca2b23d0ba 205 */
marcozecchini 0:9fca2b23d0ba 206 ldr r1, =__etext
marcozecchini 0:9fca2b23d0ba 207 ldr r2, =__data_start__
marcozecchini 0:9fca2b23d0ba 208 ldr r3, =__data_end__
marcozecchini 0:9fca2b23d0ba 209
marcozecchini 0:9fca2b23d0ba 210 .L_loop1:
marcozecchini 0:9fca2b23d0ba 211 cmp r2, r3
marcozecchini 0:9fca2b23d0ba 212 ittt lt
marcozecchini 0:9fca2b23d0ba 213 ldrlt r0, [r1], #4
marcozecchini 0:9fca2b23d0ba 214 strlt r0, [r2], #4
marcozecchini 0:9fca2b23d0ba 215 blt .L_loop1
marcozecchini 0:9fca2b23d0ba 216 #endif /*__STARTUP_COPY_MULTIPLE */
marcozecchini 0:9fca2b23d0ba 217
marcozecchini 0:9fca2b23d0ba 218 /* This part of work usually is done in C library startup code. Otherwise,
marcozecchini 0:9fca2b23d0ba 219 * define this macro to enable it in this startup.
marcozecchini 0:9fca2b23d0ba 220 *
marcozecchini 0:9fca2b23d0ba 221 * There are two schemes too. One can clear multiple BSS sections. Another
marcozecchini 0:9fca2b23d0ba 222 * can only clear one section. The former is more size expensive than the
marcozecchini 0:9fca2b23d0ba 223 * latter.
marcozecchini 0:9fca2b23d0ba 224 *
marcozecchini 0:9fca2b23d0ba 225 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
marcozecchini 0:9fca2b23d0ba 226 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
marcozecchini 0:9fca2b23d0ba 227 */
marcozecchini 0:9fca2b23d0ba 228 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
marcozecchini 0:9fca2b23d0ba 229 /* Multiple sections scheme.
marcozecchini 0:9fca2b23d0ba 230 *
marcozecchini 0:9fca2b23d0ba 231 * Between symbol address __zero_table_start__ and __zero_table_end__,
marcozecchini 0:9fca2b23d0ba 232 * there are array of tuples specifying:
marcozecchini 0:9fca2b23d0ba 233 * offset 0: Start of a BSS section
marcozecchini 0:9fca2b23d0ba 234 * offset 4: Size of this BSS section. Must be multiply of 4
marcozecchini 0:9fca2b23d0ba 235 */
marcozecchini 0:9fca2b23d0ba 236 ldr r3, =__zero_table_start__
marcozecchini 0:9fca2b23d0ba 237 ldr r4, =__zero_table_end__
marcozecchini 0:9fca2b23d0ba 238
marcozecchini 0:9fca2b23d0ba 239 .L_loop2:
marcozecchini 0:9fca2b23d0ba 240 cmp r3, r4
marcozecchini 0:9fca2b23d0ba 241 bge .L_loop2_done
marcozecchini 0:9fca2b23d0ba 242 ldr r1, [r3]
marcozecchini 0:9fca2b23d0ba 243 ldr r2, [r3, #4]
marcozecchini 0:9fca2b23d0ba 244 movs r0, 0
marcozecchini 0:9fca2b23d0ba 245
marcozecchini 0:9fca2b23d0ba 246 .L_loop2_0:
marcozecchini 0:9fca2b23d0ba 247 subs r2, #4
marcozecchini 0:9fca2b23d0ba 248 itt ge
marcozecchini 0:9fca2b23d0ba 249 strge r0, [r1, r2]
marcozecchini 0:9fca2b23d0ba 250 bge .L_loop2_0
marcozecchini 0:9fca2b23d0ba 251 adds r3, #8
marcozecchini 0:9fca2b23d0ba 252 b .L_loop2
marcozecchini 0:9fca2b23d0ba 253 .L_loop2_done:
marcozecchini 0:9fca2b23d0ba 254 #elif defined (__STARTUP_CLEAR_BSS)
marcozecchini 0:9fca2b23d0ba 255 /* Single BSS section scheme.
marcozecchini 0:9fca2b23d0ba 256 *
marcozecchini 0:9fca2b23d0ba 257 * The BSS section is specified by following symbols
marcozecchini 0:9fca2b23d0ba 258 * __bss_start__: start of the BSS section.
marcozecchini 0:9fca2b23d0ba 259 * __bss_end__: end of the BSS section.
marcozecchini 0:9fca2b23d0ba 260 *
marcozecchini 0:9fca2b23d0ba 261 * Both addresses must be aligned to 4 bytes boundary.
marcozecchini 0:9fca2b23d0ba 262 */
marcozecchini 0:9fca2b23d0ba 263 ldr r1, =__bss_start__
marcozecchini 0:9fca2b23d0ba 264 ldr r2, =__bss_end__
marcozecchini 0:9fca2b23d0ba 265
marcozecchini 0:9fca2b23d0ba 266 movs r0, 0
marcozecchini 0:9fca2b23d0ba 267 .L_loop3:
marcozecchini 0:9fca2b23d0ba 268 cmp r1, r2
marcozecchini 0:9fca2b23d0ba 269 itt lt
marcozecchini 0:9fca2b23d0ba 270 strlt r0, [r1], #4
marcozecchini 0:9fca2b23d0ba 271 blt .L_loop3
marcozecchini 0:9fca2b23d0ba 272 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
marcozecchini 0:9fca2b23d0ba 273
marcozecchini 0:9fca2b23d0ba 274 #ifndef __START
marcozecchini 0:9fca2b23d0ba 275 #define __START _start
marcozecchini 0:9fca2b23d0ba 276 #endif
marcozecchini 0:9fca2b23d0ba 277 bl __START
marcozecchini 0:9fca2b23d0ba 278
marcozecchini 0:9fca2b23d0ba 279 .pool
marcozecchini 0:9fca2b23d0ba 280 .size Reset_Handler, . - Reset_Handler
marcozecchini 0:9fca2b23d0ba 281
marcozecchini 0:9fca2b23d0ba 282 .align 1
marcozecchini 0:9fca2b23d0ba 283 .thumb_func
marcozecchini 0:9fca2b23d0ba 284 .weak Default_Handler
marcozecchini 0:9fca2b23d0ba 285 .type Default_Handler, %function
marcozecchini 0:9fca2b23d0ba 286 Default_Handler:
marcozecchini 0:9fca2b23d0ba 287 b .
marcozecchini 0:9fca2b23d0ba 288 .size Default_Handler, . - Default_Handler
marcozecchini 0:9fca2b23d0ba 289
marcozecchini 0:9fca2b23d0ba 290 /* Macro to define default handlers. Default handler
marcozecchini 0:9fca2b23d0ba 291 * will be weak symbol and just dead loops. They can be
marcozecchini 0:9fca2b23d0ba 292 * overwritten by other handlers */
marcozecchini 0:9fca2b23d0ba 293 .macro def_irq_handler handler_name
marcozecchini 0:9fca2b23d0ba 294 .weak \handler_name
marcozecchini 0:9fca2b23d0ba 295 .set \handler_name, Default_Handler
marcozecchini 0:9fca2b23d0ba 296 .endm
marcozecchini 0:9fca2b23d0ba 297
marcozecchini 0:9fca2b23d0ba 298 def_irq_handler NMI_Handler
marcozecchini 0:9fca2b23d0ba 299 def_irq_handler HardFault_Handler
marcozecchini 0:9fca2b23d0ba 300 def_irq_handler MemManage_Handler
marcozecchini 0:9fca2b23d0ba 301 def_irq_handler BusFault_Handler
marcozecchini 0:9fca2b23d0ba 302 def_irq_handler UsageFault_Handler
marcozecchini 0:9fca2b23d0ba 303 def_irq_handler SVC_Handler
marcozecchini 0:9fca2b23d0ba 304 def_irq_handler DebugMon_Handler
marcozecchini 0:9fca2b23d0ba 305 def_irq_handler PendSV_Handler
marcozecchini 0:9fca2b23d0ba 306 def_irq_handler SysTick_Handler
marcozecchini 0:9fca2b23d0ba 307
marcozecchini 0:9fca2b23d0ba 308
marcozecchini 0:9fca2b23d0ba 309 def_irq_handler EMU_IRQHandler
marcozecchini 0:9fca2b23d0ba 310 def_irq_handler WDOG0_IRQHandler
marcozecchini 0:9fca2b23d0ba 311 def_irq_handler WDOG1_IRQHandler
marcozecchini 0:9fca2b23d0ba 312 def_irq_handler LDMA_IRQHandler
marcozecchini 0:9fca2b23d0ba 313 def_irq_handler GPIO_EVEN_IRQHandler
marcozecchini 0:9fca2b23d0ba 314 def_irq_handler TIMER0_IRQHandler
marcozecchini 0:9fca2b23d0ba 315 def_irq_handler USART0_RX_IRQHandler
marcozecchini 0:9fca2b23d0ba 316 def_irq_handler USART0_TX_IRQHandler
marcozecchini 0:9fca2b23d0ba 317 def_irq_handler ACMP0_IRQHandler
marcozecchini 0:9fca2b23d0ba 318 def_irq_handler ADC0_IRQHandler
marcozecchini 0:9fca2b23d0ba 319 def_irq_handler IDAC0_IRQHandler
marcozecchini 0:9fca2b23d0ba 320 def_irq_handler I2C0_IRQHandler
marcozecchini 0:9fca2b23d0ba 321 def_irq_handler GPIO_ODD_IRQHandler
marcozecchini 0:9fca2b23d0ba 322 def_irq_handler TIMER1_IRQHandler
marcozecchini 0:9fca2b23d0ba 323 def_irq_handler USART1_RX_IRQHandler
marcozecchini 0:9fca2b23d0ba 324 def_irq_handler USART1_TX_IRQHandler
marcozecchini 0:9fca2b23d0ba 325 def_irq_handler LEUART0_IRQHandler
marcozecchini 0:9fca2b23d0ba 326 def_irq_handler PCNT0_IRQHandler
marcozecchini 0:9fca2b23d0ba 327 def_irq_handler CMU_IRQHandler
marcozecchini 0:9fca2b23d0ba 328 def_irq_handler MSC_IRQHandler
marcozecchini 0:9fca2b23d0ba 329 def_irq_handler CRYPTO0_IRQHandler
marcozecchini 0:9fca2b23d0ba 330 def_irq_handler LETIMER0_IRQHandler
marcozecchini 0:9fca2b23d0ba 331 def_irq_handler RTCC_IRQHandler
marcozecchini 0:9fca2b23d0ba 332 def_irq_handler CRYOTIMER_IRQHandler
marcozecchini 0:9fca2b23d0ba 333 def_irq_handler FPUEH_IRQHandler
marcozecchini 0:9fca2b23d0ba 334 def_irq_handler SMU_IRQHandler
marcozecchini 0:9fca2b23d0ba 335 def_irq_handler WTIMER0_IRQHandler
marcozecchini 0:9fca2b23d0ba 336 def_irq_handler WTIMER1_IRQHandler
marcozecchini 0:9fca2b23d0ba 337 def_irq_handler PCNT1_IRQHandler
marcozecchini 0:9fca2b23d0ba 338 def_irq_handler PCNT2_IRQHandler
marcozecchini 0:9fca2b23d0ba 339 def_irq_handler USART2_RX_IRQHandler
marcozecchini 0:9fca2b23d0ba 340 def_irq_handler USART2_TX_IRQHandler
marcozecchini 0:9fca2b23d0ba 341 def_irq_handler I2C1_IRQHandler
marcozecchini 0:9fca2b23d0ba 342 def_irq_handler USART3_RX_IRQHandler
marcozecchini 0:9fca2b23d0ba 343 def_irq_handler USART3_TX_IRQHandler
marcozecchini 0:9fca2b23d0ba 344 def_irq_handler VDAC0_IRQHandler
marcozecchini 0:9fca2b23d0ba 345 def_irq_handler CSEN_IRQHandler
marcozecchini 0:9fca2b23d0ba 346 def_irq_handler LESENSE_IRQHandler
marcozecchini 0:9fca2b23d0ba 347 def_irq_handler CRYPTO1_IRQHandler
marcozecchini 0:9fca2b23d0ba 348 def_irq_handler TRNG0_IRQHandler
marcozecchini 0:9fca2b23d0ba 349
marcozecchini 0:9fca2b23d0ba 350 .end