Marco Zecchini
/
Example_RTOS
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mbed-os/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_cortex.h@0:9fca2b23d0ba, 2019-02-23 (annotated)
- Committer:
- marcozecchini
- Date:
- Sat Feb 23 12:13:36 2019 +0000
- Revision:
- 0:9fca2b23d0ba
final commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| marcozecchini | 0:9fca2b23d0ba | 1 | /** |
| marcozecchini | 0:9fca2b23d0ba | 2 | ****************************************************************************** |
| marcozecchini | 0:9fca2b23d0ba | 3 | * @file stm32f3xx_ll_cortex.h |
| marcozecchini | 0:9fca2b23d0ba | 4 | * @author MCD Application Team |
| marcozecchini | 0:9fca2b23d0ba | 5 | * @version V1.4.0 |
| marcozecchini | 0:9fca2b23d0ba | 6 | * @date 16-December-2016 |
| marcozecchini | 0:9fca2b23d0ba | 7 | * @brief Header file of CORTEX LL module. |
| marcozecchini | 0:9fca2b23d0ba | 8 | @verbatim |
| marcozecchini | 0:9fca2b23d0ba | 9 | ============================================================================== |
| marcozecchini | 0:9fca2b23d0ba | 10 | ##### How to use this driver ##### |
| marcozecchini | 0:9fca2b23d0ba | 11 | ============================================================================== |
| marcozecchini | 0:9fca2b23d0ba | 12 | [..] |
| marcozecchini | 0:9fca2b23d0ba | 13 | The LL CORTEX driver contains a set of generic APIs that can be |
| marcozecchini | 0:9fca2b23d0ba | 14 | used by user: |
| marcozecchini | 0:9fca2b23d0ba | 15 | (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick |
| marcozecchini | 0:9fca2b23d0ba | 16 | functions |
| marcozecchini | 0:9fca2b23d0ba | 17 | (+) Low power mode configuration (SCB register of Cortex-MCU) |
| marcozecchini | 0:9fca2b23d0ba | 18 | (+) MPU API to configure and enable regions |
| marcozecchini | 0:9fca2b23d0ba | 19 | (MPU services provided only on some devices) |
| marcozecchini | 0:9fca2b23d0ba | 20 | (+) API to access to MCU info (CPUID register) |
| marcozecchini | 0:9fca2b23d0ba | 21 | (+) API to enable fault handler (SHCSR accesses) |
| marcozecchini | 0:9fca2b23d0ba | 22 | |
| marcozecchini | 0:9fca2b23d0ba | 23 | @endverbatim |
| marcozecchini | 0:9fca2b23d0ba | 24 | ****************************************************************************** |
| marcozecchini | 0:9fca2b23d0ba | 25 | * @attention |
| marcozecchini | 0:9fca2b23d0ba | 26 | * |
| marcozecchini | 0:9fca2b23d0ba | 27 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| marcozecchini | 0:9fca2b23d0ba | 28 | * |
| marcozecchini | 0:9fca2b23d0ba | 29 | * Redistribution and use in source and binary forms, with or without modification, |
| marcozecchini | 0:9fca2b23d0ba | 30 | * are permitted provided that the following conditions are met: |
| marcozecchini | 0:9fca2b23d0ba | 31 | * 1. Redistributions of source code must retain the above copyright notice, |
| marcozecchini | 0:9fca2b23d0ba | 32 | * this list of conditions and the following disclaimer. |
| marcozecchini | 0:9fca2b23d0ba | 33 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| marcozecchini | 0:9fca2b23d0ba | 34 | * this list of conditions and the following disclaimer in the documentation |
| marcozecchini | 0:9fca2b23d0ba | 35 | * and/or other materials provided with the distribution. |
| marcozecchini | 0:9fca2b23d0ba | 36 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| marcozecchini | 0:9fca2b23d0ba | 37 | * may be used to endorse or promote products derived from this software |
| marcozecchini | 0:9fca2b23d0ba | 38 | * without specific prior written permission. |
| marcozecchini | 0:9fca2b23d0ba | 39 | * |
| marcozecchini | 0:9fca2b23d0ba | 40 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| marcozecchini | 0:9fca2b23d0ba | 41 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| marcozecchini | 0:9fca2b23d0ba | 42 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| marcozecchini | 0:9fca2b23d0ba | 43 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| marcozecchini | 0:9fca2b23d0ba | 44 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| marcozecchini | 0:9fca2b23d0ba | 45 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| marcozecchini | 0:9fca2b23d0ba | 46 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| marcozecchini | 0:9fca2b23d0ba | 47 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| marcozecchini | 0:9fca2b23d0ba | 48 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| marcozecchini | 0:9fca2b23d0ba | 49 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| marcozecchini | 0:9fca2b23d0ba | 50 | * |
| marcozecchini | 0:9fca2b23d0ba | 51 | ****************************************************************************** |
| marcozecchini | 0:9fca2b23d0ba | 52 | */ |
| marcozecchini | 0:9fca2b23d0ba | 53 | |
| marcozecchini | 0:9fca2b23d0ba | 54 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 55 | #ifndef __STM32F3xx_LL_CORTEX_H |
| marcozecchini | 0:9fca2b23d0ba | 56 | #define __STM32F3xx_LL_CORTEX_H |
| marcozecchini | 0:9fca2b23d0ba | 57 | |
| marcozecchini | 0:9fca2b23d0ba | 58 | #ifdef __cplusplus |
| marcozecchini | 0:9fca2b23d0ba | 59 | extern "C" { |
| marcozecchini | 0:9fca2b23d0ba | 60 | #endif |
| marcozecchini | 0:9fca2b23d0ba | 61 | |
| marcozecchini | 0:9fca2b23d0ba | 62 | /* Includes ------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 63 | #include "stm32f3xx.h" |
| marcozecchini | 0:9fca2b23d0ba | 64 | |
| marcozecchini | 0:9fca2b23d0ba | 65 | /** @addtogroup STM32F3xx_LL_Driver |
| marcozecchini | 0:9fca2b23d0ba | 66 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 67 | */ |
| marcozecchini | 0:9fca2b23d0ba | 68 | |
| marcozecchini | 0:9fca2b23d0ba | 69 | /** @defgroup CORTEX_LL CORTEX |
| marcozecchini | 0:9fca2b23d0ba | 70 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 71 | */ |
| marcozecchini | 0:9fca2b23d0ba | 72 | |
| marcozecchini | 0:9fca2b23d0ba | 73 | /* Private types -------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 74 | /* Private variables ---------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 75 | |
| marcozecchini | 0:9fca2b23d0ba | 76 | /* Private constants ---------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 77 | |
| marcozecchini | 0:9fca2b23d0ba | 78 | /* Private macros ------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 79 | |
| marcozecchini | 0:9fca2b23d0ba | 80 | /* Exported types ------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 81 | /* Exported constants --------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 82 | /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants |
| marcozecchini | 0:9fca2b23d0ba | 83 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 84 | */ |
| marcozecchini | 0:9fca2b23d0ba | 85 | |
| marcozecchini | 0:9fca2b23d0ba | 86 | /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source |
| marcozecchini | 0:9fca2b23d0ba | 87 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 88 | */ |
| marcozecchini | 0:9fca2b23d0ba | 89 | #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/ |
| marcozecchini | 0:9fca2b23d0ba | 90 | #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */ |
| marcozecchini | 0:9fca2b23d0ba | 91 | /** |
| marcozecchini | 0:9fca2b23d0ba | 92 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 93 | */ |
| marcozecchini | 0:9fca2b23d0ba | 94 | |
| marcozecchini | 0:9fca2b23d0ba | 95 | /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type |
| marcozecchini | 0:9fca2b23d0ba | 96 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 97 | */ |
| marcozecchini | 0:9fca2b23d0ba | 98 | #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ |
| marcozecchini | 0:9fca2b23d0ba | 99 | #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ |
| marcozecchini | 0:9fca2b23d0ba | 100 | #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ |
| marcozecchini | 0:9fca2b23d0ba | 101 | /** |
| marcozecchini | 0:9fca2b23d0ba | 102 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 103 | */ |
| marcozecchini | 0:9fca2b23d0ba | 104 | |
| marcozecchini | 0:9fca2b23d0ba | 105 | #if __MPU_PRESENT |
| marcozecchini | 0:9fca2b23d0ba | 106 | |
| marcozecchini | 0:9fca2b23d0ba | 107 | /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control |
| marcozecchini | 0:9fca2b23d0ba | 108 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 109 | */ |
| marcozecchini | 0:9fca2b23d0ba | 110 | #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */ |
| marcozecchini | 0:9fca2b23d0ba | 111 | #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ |
| marcozecchini | 0:9fca2b23d0ba | 112 | #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ |
| marcozecchini | 0:9fca2b23d0ba | 113 | #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ |
| marcozecchini | 0:9fca2b23d0ba | 114 | /** |
| marcozecchini | 0:9fca2b23d0ba | 115 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 116 | */ |
| marcozecchini | 0:9fca2b23d0ba | 117 | |
| marcozecchini | 0:9fca2b23d0ba | 118 | /** @defgroup CORTEX_LL_EC_REGION MPU Region Number |
| marcozecchini | 0:9fca2b23d0ba | 119 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 120 | */ |
| marcozecchini | 0:9fca2b23d0ba | 121 | #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */ |
| marcozecchini | 0:9fca2b23d0ba | 122 | #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */ |
| marcozecchini | 0:9fca2b23d0ba | 123 | #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */ |
| marcozecchini | 0:9fca2b23d0ba | 124 | #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */ |
| marcozecchini | 0:9fca2b23d0ba | 125 | #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */ |
| marcozecchini | 0:9fca2b23d0ba | 126 | #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */ |
| marcozecchini | 0:9fca2b23d0ba | 127 | #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */ |
| marcozecchini | 0:9fca2b23d0ba | 128 | #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */ |
| marcozecchini | 0:9fca2b23d0ba | 129 | /** |
| marcozecchini | 0:9fca2b23d0ba | 130 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 131 | */ |
| marcozecchini | 0:9fca2b23d0ba | 132 | |
| marcozecchini | 0:9fca2b23d0ba | 133 | /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size |
| marcozecchini | 0:9fca2b23d0ba | 134 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 135 | */ |
| marcozecchini | 0:9fca2b23d0ba | 136 | #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 137 | #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 138 | #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 139 | #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 140 | #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 141 | #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 142 | #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 143 | #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 144 | #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 145 | #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 146 | #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 147 | #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 148 | #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 149 | #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 150 | #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 151 | #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 152 | #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 153 | #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 154 | #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 155 | #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 156 | #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 157 | #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 158 | #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 159 | #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 160 | #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 161 | #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 162 | #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 163 | #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */ |
| marcozecchini | 0:9fca2b23d0ba | 164 | /** |
| marcozecchini | 0:9fca2b23d0ba | 165 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 166 | */ |
| marcozecchini | 0:9fca2b23d0ba | 167 | |
| marcozecchini | 0:9fca2b23d0ba | 168 | /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges |
| marcozecchini | 0:9fca2b23d0ba | 169 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 170 | */ |
| marcozecchini | 0:9fca2b23d0ba | 171 | #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/ |
| marcozecchini | 0:9fca2b23d0ba | 172 | #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/ |
| marcozecchini | 0:9fca2b23d0ba | 173 | #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */ |
| marcozecchini | 0:9fca2b23d0ba | 174 | #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */ |
| marcozecchini | 0:9fca2b23d0ba | 175 | #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/ |
| marcozecchini | 0:9fca2b23d0ba | 176 | #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */ |
| marcozecchini | 0:9fca2b23d0ba | 177 | /** |
| marcozecchini | 0:9fca2b23d0ba | 178 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 179 | */ |
| marcozecchini | 0:9fca2b23d0ba | 180 | |
| marcozecchini | 0:9fca2b23d0ba | 181 | /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level |
| marcozecchini | 0:9fca2b23d0ba | 182 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 183 | */ |
| marcozecchini | 0:9fca2b23d0ba | 184 | #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */ |
| marcozecchini | 0:9fca2b23d0ba | 185 | #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */ |
| marcozecchini | 0:9fca2b23d0ba | 186 | #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */ |
| marcozecchini | 0:9fca2b23d0ba | 187 | #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */ |
| marcozecchini | 0:9fca2b23d0ba | 188 | /** |
| marcozecchini | 0:9fca2b23d0ba | 189 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 190 | */ |
| marcozecchini | 0:9fca2b23d0ba | 191 | |
| marcozecchini | 0:9fca2b23d0ba | 192 | /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access |
| marcozecchini | 0:9fca2b23d0ba | 193 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 194 | */ |
| marcozecchini | 0:9fca2b23d0ba | 195 | #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */ |
| marcozecchini | 0:9fca2b23d0ba | 196 | #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ |
| marcozecchini | 0:9fca2b23d0ba | 197 | /** |
| marcozecchini | 0:9fca2b23d0ba | 198 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 199 | */ |
| marcozecchini | 0:9fca2b23d0ba | 200 | |
| marcozecchini | 0:9fca2b23d0ba | 201 | /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access |
| marcozecchini | 0:9fca2b23d0ba | 202 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 203 | */ |
| marcozecchini | 0:9fca2b23d0ba | 204 | #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ |
| marcozecchini | 0:9fca2b23d0ba | 205 | #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */ |
| marcozecchini | 0:9fca2b23d0ba | 206 | /** |
| marcozecchini | 0:9fca2b23d0ba | 207 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 208 | */ |
| marcozecchini | 0:9fca2b23d0ba | 209 | |
| marcozecchini | 0:9fca2b23d0ba | 210 | /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access |
| marcozecchini | 0:9fca2b23d0ba | 211 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 212 | */ |
| marcozecchini | 0:9fca2b23d0ba | 213 | #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ |
| marcozecchini | 0:9fca2b23d0ba | 214 | #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */ |
| marcozecchini | 0:9fca2b23d0ba | 215 | /** |
| marcozecchini | 0:9fca2b23d0ba | 216 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 217 | */ |
| marcozecchini | 0:9fca2b23d0ba | 218 | |
| marcozecchini | 0:9fca2b23d0ba | 219 | /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access |
| marcozecchini | 0:9fca2b23d0ba | 220 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 221 | */ |
| marcozecchini | 0:9fca2b23d0ba | 222 | #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ |
| marcozecchini | 0:9fca2b23d0ba | 223 | #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */ |
| marcozecchini | 0:9fca2b23d0ba | 224 | /** |
| marcozecchini | 0:9fca2b23d0ba | 225 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 226 | */ |
| marcozecchini | 0:9fca2b23d0ba | 227 | #endif /* __MPU_PRESENT */ |
| marcozecchini | 0:9fca2b23d0ba | 228 | /** |
| marcozecchini | 0:9fca2b23d0ba | 229 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 230 | */ |
| marcozecchini | 0:9fca2b23d0ba | 231 | |
| marcozecchini | 0:9fca2b23d0ba | 232 | /* Exported macro ------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 233 | |
| marcozecchini | 0:9fca2b23d0ba | 234 | /* Exported functions --------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 235 | /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions |
| marcozecchini | 0:9fca2b23d0ba | 236 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 237 | */ |
| marcozecchini | 0:9fca2b23d0ba | 238 | |
| marcozecchini | 0:9fca2b23d0ba | 239 | /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK |
| marcozecchini | 0:9fca2b23d0ba | 240 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 241 | */ |
| marcozecchini | 0:9fca2b23d0ba | 242 | |
| marcozecchini | 0:9fca2b23d0ba | 243 | /** |
| marcozecchini | 0:9fca2b23d0ba | 244 | * @brief This function checks if the Systick counter flag is active or not. |
| marcozecchini | 0:9fca2b23d0ba | 245 | * @note It can be used in timeout function on application side. |
| marcozecchini | 0:9fca2b23d0ba | 246 | * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag |
| marcozecchini | 0:9fca2b23d0ba | 247 | * @retval State of bit (1 or 0). |
| marcozecchini | 0:9fca2b23d0ba | 248 | */ |
| marcozecchini | 0:9fca2b23d0ba | 249 | __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) |
| marcozecchini | 0:9fca2b23d0ba | 250 | { |
| marcozecchini | 0:9fca2b23d0ba | 251 | return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 252 | } |
| marcozecchini | 0:9fca2b23d0ba | 253 | |
| marcozecchini | 0:9fca2b23d0ba | 254 | /** |
| marcozecchini | 0:9fca2b23d0ba | 255 | * @brief Configures the SysTick clock source |
| marcozecchini | 0:9fca2b23d0ba | 256 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource |
| marcozecchini | 0:9fca2b23d0ba | 257 | * @param Source This parameter can be one of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 258 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
| marcozecchini | 0:9fca2b23d0ba | 259 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
| marcozecchini | 0:9fca2b23d0ba | 260 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 261 | */ |
| marcozecchini | 0:9fca2b23d0ba | 262 | __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) |
| marcozecchini | 0:9fca2b23d0ba | 263 | { |
| marcozecchini | 0:9fca2b23d0ba | 264 | if (Source == LL_SYSTICK_CLKSOURCE_HCLK) |
| marcozecchini | 0:9fca2b23d0ba | 265 | { |
| marcozecchini | 0:9fca2b23d0ba | 266 | SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
| marcozecchini | 0:9fca2b23d0ba | 267 | } |
| marcozecchini | 0:9fca2b23d0ba | 268 | else |
| marcozecchini | 0:9fca2b23d0ba | 269 | { |
| marcozecchini | 0:9fca2b23d0ba | 270 | CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
| marcozecchini | 0:9fca2b23d0ba | 271 | } |
| marcozecchini | 0:9fca2b23d0ba | 272 | } |
| marcozecchini | 0:9fca2b23d0ba | 273 | |
| marcozecchini | 0:9fca2b23d0ba | 274 | /** |
| marcozecchini | 0:9fca2b23d0ba | 275 | * @brief Get the SysTick clock source |
| marcozecchini | 0:9fca2b23d0ba | 276 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource |
| marcozecchini | 0:9fca2b23d0ba | 277 | * @retval Returned value can be one of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 278 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
| marcozecchini | 0:9fca2b23d0ba | 279 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
| marcozecchini | 0:9fca2b23d0ba | 280 | */ |
| marcozecchini | 0:9fca2b23d0ba | 281 | __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) |
| marcozecchini | 0:9fca2b23d0ba | 282 | { |
| marcozecchini | 0:9fca2b23d0ba | 283 | return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
| marcozecchini | 0:9fca2b23d0ba | 284 | } |
| marcozecchini | 0:9fca2b23d0ba | 285 | |
| marcozecchini | 0:9fca2b23d0ba | 286 | /** |
| marcozecchini | 0:9fca2b23d0ba | 287 | * @brief Enable SysTick exception request |
| marcozecchini | 0:9fca2b23d0ba | 288 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT |
| marcozecchini | 0:9fca2b23d0ba | 289 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 290 | */ |
| marcozecchini | 0:9fca2b23d0ba | 291 | __STATIC_INLINE void LL_SYSTICK_EnableIT(void) |
| marcozecchini | 0:9fca2b23d0ba | 292 | { |
| marcozecchini | 0:9fca2b23d0ba | 293 | SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
| marcozecchini | 0:9fca2b23d0ba | 294 | } |
| marcozecchini | 0:9fca2b23d0ba | 295 | |
| marcozecchini | 0:9fca2b23d0ba | 296 | /** |
| marcozecchini | 0:9fca2b23d0ba | 297 | * @brief Disable SysTick exception request |
| marcozecchini | 0:9fca2b23d0ba | 298 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT |
| marcozecchini | 0:9fca2b23d0ba | 299 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 300 | */ |
| marcozecchini | 0:9fca2b23d0ba | 301 | __STATIC_INLINE void LL_SYSTICK_DisableIT(void) |
| marcozecchini | 0:9fca2b23d0ba | 302 | { |
| marcozecchini | 0:9fca2b23d0ba | 303 | CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
| marcozecchini | 0:9fca2b23d0ba | 304 | } |
| marcozecchini | 0:9fca2b23d0ba | 305 | |
| marcozecchini | 0:9fca2b23d0ba | 306 | /** |
| marcozecchini | 0:9fca2b23d0ba | 307 | * @brief Checks if the SYSTICK interrupt is enabled or disabled. |
| marcozecchini | 0:9fca2b23d0ba | 308 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT |
| marcozecchini | 0:9fca2b23d0ba | 309 | * @retval State of bit (1 or 0). |
| marcozecchini | 0:9fca2b23d0ba | 310 | */ |
| marcozecchini | 0:9fca2b23d0ba | 311 | __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) |
| marcozecchini | 0:9fca2b23d0ba | 312 | { |
| marcozecchini | 0:9fca2b23d0ba | 313 | return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 314 | } |
| marcozecchini | 0:9fca2b23d0ba | 315 | |
| marcozecchini | 0:9fca2b23d0ba | 316 | /** |
| marcozecchini | 0:9fca2b23d0ba | 317 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 318 | */ |
| marcozecchini | 0:9fca2b23d0ba | 319 | |
| marcozecchini | 0:9fca2b23d0ba | 320 | /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE |
| marcozecchini | 0:9fca2b23d0ba | 321 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 322 | */ |
| marcozecchini | 0:9fca2b23d0ba | 323 | |
| marcozecchini | 0:9fca2b23d0ba | 324 | /** |
| marcozecchini | 0:9fca2b23d0ba | 325 | * @brief Processor uses sleep as its low power mode |
| marcozecchini | 0:9fca2b23d0ba | 326 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep |
| marcozecchini | 0:9fca2b23d0ba | 327 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 328 | */ |
| marcozecchini | 0:9fca2b23d0ba | 329 | __STATIC_INLINE void LL_LPM_EnableSleep(void) |
| marcozecchini | 0:9fca2b23d0ba | 330 | { |
| marcozecchini | 0:9fca2b23d0ba | 331 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
| marcozecchini | 0:9fca2b23d0ba | 332 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 333 | } |
| marcozecchini | 0:9fca2b23d0ba | 334 | |
| marcozecchini | 0:9fca2b23d0ba | 335 | /** |
| marcozecchini | 0:9fca2b23d0ba | 336 | * @brief Processor uses deep sleep as its low power mode |
| marcozecchini | 0:9fca2b23d0ba | 337 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep |
| marcozecchini | 0:9fca2b23d0ba | 338 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 339 | */ |
| marcozecchini | 0:9fca2b23d0ba | 340 | __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) |
| marcozecchini | 0:9fca2b23d0ba | 341 | { |
| marcozecchini | 0:9fca2b23d0ba | 342 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| marcozecchini | 0:9fca2b23d0ba | 343 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 344 | } |
| marcozecchini | 0:9fca2b23d0ba | 345 | |
| marcozecchini | 0:9fca2b23d0ba | 346 | /** |
| marcozecchini | 0:9fca2b23d0ba | 347 | * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. |
| marcozecchini | 0:9fca2b23d0ba | 348 | * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an |
| marcozecchini | 0:9fca2b23d0ba | 349 | * empty main application. |
| marcozecchini | 0:9fca2b23d0ba | 350 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit |
| marcozecchini | 0:9fca2b23d0ba | 351 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 352 | */ |
| marcozecchini | 0:9fca2b23d0ba | 353 | __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) |
| marcozecchini | 0:9fca2b23d0ba | 354 | { |
| marcozecchini | 0:9fca2b23d0ba | 355 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
| marcozecchini | 0:9fca2b23d0ba | 356 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 357 | } |
| marcozecchini | 0:9fca2b23d0ba | 358 | |
| marcozecchini | 0:9fca2b23d0ba | 359 | /** |
| marcozecchini | 0:9fca2b23d0ba | 360 | * @brief Do not sleep when returning to Thread mode. |
| marcozecchini | 0:9fca2b23d0ba | 361 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit |
| marcozecchini | 0:9fca2b23d0ba | 362 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 363 | */ |
| marcozecchini | 0:9fca2b23d0ba | 364 | __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) |
| marcozecchini | 0:9fca2b23d0ba | 365 | { |
| marcozecchini | 0:9fca2b23d0ba | 366 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
| marcozecchini | 0:9fca2b23d0ba | 367 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 368 | } |
| marcozecchini | 0:9fca2b23d0ba | 369 | |
| marcozecchini | 0:9fca2b23d0ba | 370 | /** |
| marcozecchini | 0:9fca2b23d0ba | 371 | * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the |
| marcozecchini | 0:9fca2b23d0ba | 372 | * processor. |
| marcozecchini | 0:9fca2b23d0ba | 373 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend |
| marcozecchini | 0:9fca2b23d0ba | 374 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 375 | */ |
| marcozecchini | 0:9fca2b23d0ba | 376 | __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) |
| marcozecchini | 0:9fca2b23d0ba | 377 | { |
| marcozecchini | 0:9fca2b23d0ba | 378 | /* Set SEVEONPEND bit of Cortex System Control Register */ |
| marcozecchini | 0:9fca2b23d0ba | 379 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 380 | } |
| marcozecchini | 0:9fca2b23d0ba | 381 | |
| marcozecchini | 0:9fca2b23d0ba | 382 | /** |
| marcozecchini | 0:9fca2b23d0ba | 383 | * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are |
| marcozecchini | 0:9fca2b23d0ba | 384 | * excluded |
| marcozecchini | 0:9fca2b23d0ba | 385 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend |
| marcozecchini | 0:9fca2b23d0ba | 386 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 387 | */ |
| marcozecchini | 0:9fca2b23d0ba | 388 | __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) |
| marcozecchini | 0:9fca2b23d0ba | 389 | { |
| marcozecchini | 0:9fca2b23d0ba | 390 | /* Clear SEVEONPEND bit of Cortex System Control Register */ |
| marcozecchini | 0:9fca2b23d0ba | 391 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 392 | } |
| marcozecchini | 0:9fca2b23d0ba | 393 | |
| marcozecchini | 0:9fca2b23d0ba | 394 | /** |
| marcozecchini | 0:9fca2b23d0ba | 395 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 396 | */ |
| marcozecchini | 0:9fca2b23d0ba | 397 | |
| marcozecchini | 0:9fca2b23d0ba | 398 | /** @defgroup CORTEX_LL_EF_HANDLER HANDLER |
| marcozecchini | 0:9fca2b23d0ba | 399 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 400 | */ |
| marcozecchini | 0:9fca2b23d0ba | 401 | |
| marcozecchini | 0:9fca2b23d0ba | 402 | /** |
| marcozecchini | 0:9fca2b23d0ba | 403 | * @brief Enable a fault in System handler control register (SHCSR) |
| marcozecchini | 0:9fca2b23d0ba | 404 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault |
| marcozecchini | 0:9fca2b23d0ba | 405 | * @param Fault This parameter can be a combination of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 406 | * @arg @ref LL_HANDLER_FAULT_USG |
| marcozecchini | 0:9fca2b23d0ba | 407 | * @arg @ref LL_HANDLER_FAULT_BUS |
| marcozecchini | 0:9fca2b23d0ba | 408 | * @arg @ref LL_HANDLER_FAULT_MEM |
| marcozecchini | 0:9fca2b23d0ba | 409 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 410 | */ |
| marcozecchini | 0:9fca2b23d0ba | 411 | __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) |
| marcozecchini | 0:9fca2b23d0ba | 412 | { |
| marcozecchini | 0:9fca2b23d0ba | 413 | /* Enable the system handler fault */ |
| marcozecchini | 0:9fca2b23d0ba | 414 | SET_BIT(SCB->SHCSR, Fault); |
| marcozecchini | 0:9fca2b23d0ba | 415 | } |
| marcozecchini | 0:9fca2b23d0ba | 416 | |
| marcozecchini | 0:9fca2b23d0ba | 417 | /** |
| marcozecchini | 0:9fca2b23d0ba | 418 | * @brief Disable a fault in System handler control register (SHCSR) |
| marcozecchini | 0:9fca2b23d0ba | 419 | * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault |
| marcozecchini | 0:9fca2b23d0ba | 420 | * @param Fault This parameter can be a combination of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 421 | * @arg @ref LL_HANDLER_FAULT_USG |
| marcozecchini | 0:9fca2b23d0ba | 422 | * @arg @ref LL_HANDLER_FAULT_BUS |
| marcozecchini | 0:9fca2b23d0ba | 423 | * @arg @ref LL_HANDLER_FAULT_MEM |
| marcozecchini | 0:9fca2b23d0ba | 424 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 425 | */ |
| marcozecchini | 0:9fca2b23d0ba | 426 | __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) |
| marcozecchini | 0:9fca2b23d0ba | 427 | { |
| marcozecchini | 0:9fca2b23d0ba | 428 | /* Disable the system handler fault */ |
| marcozecchini | 0:9fca2b23d0ba | 429 | CLEAR_BIT(SCB->SHCSR, Fault); |
| marcozecchini | 0:9fca2b23d0ba | 430 | } |
| marcozecchini | 0:9fca2b23d0ba | 431 | |
| marcozecchini | 0:9fca2b23d0ba | 432 | /** |
| marcozecchini | 0:9fca2b23d0ba | 433 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 434 | */ |
| marcozecchini | 0:9fca2b23d0ba | 435 | |
| marcozecchini | 0:9fca2b23d0ba | 436 | /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO |
| marcozecchini | 0:9fca2b23d0ba | 437 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 438 | */ |
| marcozecchini | 0:9fca2b23d0ba | 439 | |
| marcozecchini | 0:9fca2b23d0ba | 440 | /** |
| marcozecchini | 0:9fca2b23d0ba | 441 | * @brief Get Implementer code |
| marcozecchini | 0:9fca2b23d0ba | 442 | * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer |
| marcozecchini | 0:9fca2b23d0ba | 443 | * @retval Value should be equal to 0x41 for ARM |
| marcozecchini | 0:9fca2b23d0ba | 444 | */ |
| marcozecchini | 0:9fca2b23d0ba | 445 | __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) |
| marcozecchini | 0:9fca2b23d0ba | 446 | { |
| marcozecchini | 0:9fca2b23d0ba | 447 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); |
| marcozecchini | 0:9fca2b23d0ba | 448 | } |
| marcozecchini | 0:9fca2b23d0ba | 449 | |
| marcozecchini | 0:9fca2b23d0ba | 450 | /** |
| marcozecchini | 0:9fca2b23d0ba | 451 | * @brief Get Variant number (The r value in the rnpn product revision identifier) |
| marcozecchini | 0:9fca2b23d0ba | 452 | * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant |
| marcozecchini | 0:9fca2b23d0ba | 453 | * @retval Value between 0 and 255 (0x0: revision 0) |
| marcozecchini | 0:9fca2b23d0ba | 454 | */ |
| marcozecchini | 0:9fca2b23d0ba | 455 | __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) |
| marcozecchini | 0:9fca2b23d0ba | 456 | { |
| marcozecchini | 0:9fca2b23d0ba | 457 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); |
| marcozecchini | 0:9fca2b23d0ba | 458 | } |
| marcozecchini | 0:9fca2b23d0ba | 459 | |
| marcozecchini | 0:9fca2b23d0ba | 460 | /** |
| marcozecchini | 0:9fca2b23d0ba | 461 | * @brief Get Constant number |
| marcozecchini | 0:9fca2b23d0ba | 462 | * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant |
| marcozecchini | 0:9fca2b23d0ba | 463 | * @retval Value should be equal to 0xF for Cortex-M4 devices |
| marcozecchini | 0:9fca2b23d0ba | 464 | */ |
| marcozecchini | 0:9fca2b23d0ba | 465 | __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) |
| marcozecchini | 0:9fca2b23d0ba | 466 | { |
| marcozecchini | 0:9fca2b23d0ba | 467 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); |
| marcozecchini | 0:9fca2b23d0ba | 468 | } |
| marcozecchini | 0:9fca2b23d0ba | 469 | |
| marcozecchini | 0:9fca2b23d0ba | 470 | /** |
| marcozecchini | 0:9fca2b23d0ba | 471 | * @brief Get Part number |
| marcozecchini | 0:9fca2b23d0ba | 472 | * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo |
| marcozecchini | 0:9fca2b23d0ba | 473 | * @retval Value should be equal to 0xC24 for Cortex-M4 |
| marcozecchini | 0:9fca2b23d0ba | 474 | */ |
| marcozecchini | 0:9fca2b23d0ba | 475 | __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) |
| marcozecchini | 0:9fca2b23d0ba | 476 | { |
| marcozecchini | 0:9fca2b23d0ba | 477 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); |
| marcozecchini | 0:9fca2b23d0ba | 478 | } |
| marcozecchini | 0:9fca2b23d0ba | 479 | |
| marcozecchini | 0:9fca2b23d0ba | 480 | /** |
| marcozecchini | 0:9fca2b23d0ba | 481 | * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) |
| marcozecchini | 0:9fca2b23d0ba | 482 | * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision |
| marcozecchini | 0:9fca2b23d0ba | 483 | * @retval Value between 0 and 255 (0x1: patch 1) |
| marcozecchini | 0:9fca2b23d0ba | 484 | */ |
| marcozecchini | 0:9fca2b23d0ba | 485 | __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) |
| marcozecchini | 0:9fca2b23d0ba | 486 | { |
| marcozecchini | 0:9fca2b23d0ba | 487 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); |
| marcozecchini | 0:9fca2b23d0ba | 488 | } |
| marcozecchini | 0:9fca2b23d0ba | 489 | |
| marcozecchini | 0:9fca2b23d0ba | 490 | /** |
| marcozecchini | 0:9fca2b23d0ba | 491 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 492 | */ |
| marcozecchini | 0:9fca2b23d0ba | 493 | |
| marcozecchini | 0:9fca2b23d0ba | 494 | #if __MPU_PRESENT |
| marcozecchini | 0:9fca2b23d0ba | 495 | /** @defgroup CORTEX_LL_EF_MPU MPU |
| marcozecchini | 0:9fca2b23d0ba | 496 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 497 | */ |
| marcozecchini | 0:9fca2b23d0ba | 498 | |
| marcozecchini | 0:9fca2b23d0ba | 499 | /** |
| marcozecchini | 0:9fca2b23d0ba | 500 | * @brief Enable MPU with input options |
| marcozecchini | 0:9fca2b23d0ba | 501 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable |
| marcozecchini | 0:9fca2b23d0ba | 502 | * @param Options This parameter can be one of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 503 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE |
| marcozecchini | 0:9fca2b23d0ba | 504 | * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI |
| marcozecchini | 0:9fca2b23d0ba | 505 | * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT |
| marcozecchini | 0:9fca2b23d0ba | 506 | * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF |
| marcozecchini | 0:9fca2b23d0ba | 507 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 508 | */ |
| marcozecchini | 0:9fca2b23d0ba | 509 | __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) |
| marcozecchini | 0:9fca2b23d0ba | 510 | { |
| marcozecchini | 0:9fca2b23d0ba | 511 | /* Enable the MPU*/ |
| marcozecchini | 0:9fca2b23d0ba | 512 | WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); |
| marcozecchini | 0:9fca2b23d0ba | 513 | /* Ensure MPU settings take effects */ |
| marcozecchini | 0:9fca2b23d0ba | 514 | __DSB(); |
| marcozecchini | 0:9fca2b23d0ba | 515 | /* Sequence instruction fetches using update settings */ |
| marcozecchini | 0:9fca2b23d0ba | 516 | __ISB(); |
| marcozecchini | 0:9fca2b23d0ba | 517 | } |
| marcozecchini | 0:9fca2b23d0ba | 518 | |
| marcozecchini | 0:9fca2b23d0ba | 519 | /** |
| marcozecchini | 0:9fca2b23d0ba | 520 | * @brief Disable MPU |
| marcozecchini | 0:9fca2b23d0ba | 521 | * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable |
| marcozecchini | 0:9fca2b23d0ba | 522 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 523 | */ |
| marcozecchini | 0:9fca2b23d0ba | 524 | __STATIC_INLINE void LL_MPU_Disable(void) |
| marcozecchini | 0:9fca2b23d0ba | 525 | { |
| marcozecchini | 0:9fca2b23d0ba | 526 | /* Make sure outstanding transfers are done */ |
| marcozecchini | 0:9fca2b23d0ba | 527 | __DMB(); |
| marcozecchini | 0:9fca2b23d0ba | 528 | /* Disable MPU*/ |
| marcozecchini | 0:9fca2b23d0ba | 529 | WRITE_REG(MPU->CTRL, 0U); |
| marcozecchini | 0:9fca2b23d0ba | 530 | } |
| marcozecchini | 0:9fca2b23d0ba | 531 | |
| marcozecchini | 0:9fca2b23d0ba | 532 | /** |
| marcozecchini | 0:9fca2b23d0ba | 533 | * @brief Check if MPU is enabled or not |
| marcozecchini | 0:9fca2b23d0ba | 534 | * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled |
| marcozecchini | 0:9fca2b23d0ba | 535 | * @retval State of bit (1 or 0). |
| marcozecchini | 0:9fca2b23d0ba | 536 | */ |
| marcozecchini | 0:9fca2b23d0ba | 537 | __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) |
| marcozecchini | 0:9fca2b23d0ba | 538 | { |
| marcozecchini | 0:9fca2b23d0ba | 539 | return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); |
| marcozecchini | 0:9fca2b23d0ba | 540 | } |
| marcozecchini | 0:9fca2b23d0ba | 541 | |
| marcozecchini | 0:9fca2b23d0ba | 542 | /** |
| marcozecchini | 0:9fca2b23d0ba | 543 | * @brief Enable a MPU region |
| marcozecchini | 0:9fca2b23d0ba | 544 | * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion |
| marcozecchini | 0:9fca2b23d0ba | 545 | * @param Region This parameter can be one of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 546 | * @arg @ref LL_MPU_REGION_NUMBER0 |
| marcozecchini | 0:9fca2b23d0ba | 547 | * @arg @ref LL_MPU_REGION_NUMBER1 |
| marcozecchini | 0:9fca2b23d0ba | 548 | * @arg @ref LL_MPU_REGION_NUMBER2 |
| marcozecchini | 0:9fca2b23d0ba | 549 | * @arg @ref LL_MPU_REGION_NUMBER3 |
| marcozecchini | 0:9fca2b23d0ba | 550 | * @arg @ref LL_MPU_REGION_NUMBER4 |
| marcozecchini | 0:9fca2b23d0ba | 551 | * @arg @ref LL_MPU_REGION_NUMBER5 |
| marcozecchini | 0:9fca2b23d0ba | 552 | * @arg @ref LL_MPU_REGION_NUMBER6 |
| marcozecchini | 0:9fca2b23d0ba | 553 | * @arg @ref LL_MPU_REGION_NUMBER7 |
| marcozecchini | 0:9fca2b23d0ba | 554 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 555 | */ |
| marcozecchini | 0:9fca2b23d0ba | 556 | __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) |
| marcozecchini | 0:9fca2b23d0ba | 557 | { |
| marcozecchini | 0:9fca2b23d0ba | 558 | /* Set Region number */ |
| marcozecchini | 0:9fca2b23d0ba | 559 | WRITE_REG(MPU->RNR, Region); |
| marcozecchini | 0:9fca2b23d0ba | 560 | /* Enable the MPU region */ |
| marcozecchini | 0:9fca2b23d0ba | 561 | SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
| marcozecchini | 0:9fca2b23d0ba | 562 | } |
| marcozecchini | 0:9fca2b23d0ba | 563 | |
| marcozecchini | 0:9fca2b23d0ba | 564 | /** |
| marcozecchini | 0:9fca2b23d0ba | 565 | * @brief Configure and enable a region |
| marcozecchini | 0:9fca2b23d0ba | 566 | * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 567 | * MPU_RBAR REGION LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 568 | * MPU_RBAR ADDR LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 569 | * MPU_RASR XN LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 570 | * MPU_RASR AP LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 571 | * MPU_RASR S LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 572 | * MPU_RASR C LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 573 | * MPU_RASR B LL_MPU_ConfigRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 574 | * MPU_RASR SIZE LL_MPU_ConfigRegion |
| marcozecchini | 0:9fca2b23d0ba | 575 | * @param Region This parameter can be one of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 576 | * @arg @ref LL_MPU_REGION_NUMBER0 |
| marcozecchini | 0:9fca2b23d0ba | 577 | * @arg @ref LL_MPU_REGION_NUMBER1 |
| marcozecchini | 0:9fca2b23d0ba | 578 | * @arg @ref LL_MPU_REGION_NUMBER2 |
| marcozecchini | 0:9fca2b23d0ba | 579 | * @arg @ref LL_MPU_REGION_NUMBER3 |
| marcozecchini | 0:9fca2b23d0ba | 580 | * @arg @ref LL_MPU_REGION_NUMBER4 |
| marcozecchini | 0:9fca2b23d0ba | 581 | * @arg @ref LL_MPU_REGION_NUMBER5 |
| marcozecchini | 0:9fca2b23d0ba | 582 | * @arg @ref LL_MPU_REGION_NUMBER6 |
| marcozecchini | 0:9fca2b23d0ba | 583 | * @arg @ref LL_MPU_REGION_NUMBER7 |
| marcozecchini | 0:9fca2b23d0ba | 584 | * @param Address Value of region base address |
| marcozecchini | 0:9fca2b23d0ba | 585 | * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF |
| marcozecchini | 0:9fca2b23d0ba | 586 | * @param Attributes This parameter can be a combination of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 587 | * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B |
| marcozecchini | 0:9fca2b23d0ba | 588 | * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB |
| marcozecchini | 0:9fca2b23d0ba | 589 | * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB |
| marcozecchini | 0:9fca2b23d0ba | 590 | * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB |
| marcozecchini | 0:9fca2b23d0ba | 591 | * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB |
| marcozecchini | 0:9fca2b23d0ba | 592 | * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB |
| marcozecchini | 0:9fca2b23d0ba | 593 | * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS |
| marcozecchini | 0:9fca2b23d0ba | 594 | * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO |
| marcozecchini | 0:9fca2b23d0ba | 595 | * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 |
| marcozecchini | 0:9fca2b23d0ba | 596 | * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE |
| marcozecchini | 0:9fca2b23d0ba | 597 | * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE |
| marcozecchini | 0:9fca2b23d0ba | 598 | * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE |
| marcozecchini | 0:9fca2b23d0ba | 599 | * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE |
| marcozecchini | 0:9fca2b23d0ba | 600 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 601 | */ |
| marcozecchini | 0:9fca2b23d0ba | 602 | __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) |
| marcozecchini | 0:9fca2b23d0ba | 603 | { |
| marcozecchini | 0:9fca2b23d0ba | 604 | /* Set Region number */ |
| marcozecchini | 0:9fca2b23d0ba | 605 | WRITE_REG(MPU->RNR, Region); |
| marcozecchini | 0:9fca2b23d0ba | 606 | /* Set base address */ |
| marcozecchini | 0:9fca2b23d0ba | 607 | WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); |
| marcozecchini | 0:9fca2b23d0ba | 608 | /* Configure MPU */ |
| marcozecchini | 0:9fca2b23d0ba | 609 | WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); |
| marcozecchini | 0:9fca2b23d0ba | 610 | } |
| marcozecchini | 0:9fca2b23d0ba | 611 | |
| marcozecchini | 0:9fca2b23d0ba | 612 | /** |
| marcozecchini | 0:9fca2b23d0ba | 613 | * @brief Disable a region |
| marcozecchini | 0:9fca2b23d0ba | 614 | * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n |
| marcozecchini | 0:9fca2b23d0ba | 615 | * MPU_RASR ENABLE LL_MPU_DisableRegion |
| marcozecchini | 0:9fca2b23d0ba | 616 | * @param Region This parameter can be one of the following values: |
| marcozecchini | 0:9fca2b23d0ba | 617 | * @arg @ref LL_MPU_REGION_NUMBER0 |
| marcozecchini | 0:9fca2b23d0ba | 618 | * @arg @ref LL_MPU_REGION_NUMBER1 |
| marcozecchini | 0:9fca2b23d0ba | 619 | * @arg @ref LL_MPU_REGION_NUMBER2 |
| marcozecchini | 0:9fca2b23d0ba | 620 | * @arg @ref LL_MPU_REGION_NUMBER3 |
| marcozecchini | 0:9fca2b23d0ba | 621 | * @arg @ref LL_MPU_REGION_NUMBER4 |
| marcozecchini | 0:9fca2b23d0ba | 622 | * @arg @ref LL_MPU_REGION_NUMBER5 |
| marcozecchini | 0:9fca2b23d0ba | 623 | * @arg @ref LL_MPU_REGION_NUMBER6 |
| marcozecchini | 0:9fca2b23d0ba | 624 | * @arg @ref LL_MPU_REGION_NUMBER7 |
| marcozecchini | 0:9fca2b23d0ba | 625 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 626 | */ |
| marcozecchini | 0:9fca2b23d0ba | 627 | __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) |
| marcozecchini | 0:9fca2b23d0ba | 628 | { |
| marcozecchini | 0:9fca2b23d0ba | 629 | /* Set Region number */ |
| marcozecchini | 0:9fca2b23d0ba | 630 | WRITE_REG(MPU->RNR, Region); |
| marcozecchini | 0:9fca2b23d0ba | 631 | /* Disable the MPU region */ |
| marcozecchini | 0:9fca2b23d0ba | 632 | CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
| marcozecchini | 0:9fca2b23d0ba | 633 | } |
| marcozecchini | 0:9fca2b23d0ba | 634 | |
| marcozecchini | 0:9fca2b23d0ba | 635 | /** |
| marcozecchini | 0:9fca2b23d0ba | 636 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 637 | */ |
| marcozecchini | 0:9fca2b23d0ba | 638 | |
| marcozecchini | 0:9fca2b23d0ba | 639 | #endif /* __MPU_PRESENT */ |
| marcozecchini | 0:9fca2b23d0ba | 640 | /** |
| marcozecchini | 0:9fca2b23d0ba | 641 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 642 | */ |
| marcozecchini | 0:9fca2b23d0ba | 643 | |
| marcozecchini | 0:9fca2b23d0ba | 644 | /** |
| marcozecchini | 0:9fca2b23d0ba | 645 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 646 | */ |
| marcozecchini | 0:9fca2b23d0ba | 647 | |
| marcozecchini | 0:9fca2b23d0ba | 648 | /** |
| marcozecchini | 0:9fca2b23d0ba | 649 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 650 | */ |
| marcozecchini | 0:9fca2b23d0ba | 651 | |
| marcozecchini | 0:9fca2b23d0ba | 652 | #ifdef __cplusplus |
| marcozecchini | 0:9fca2b23d0ba | 653 | } |
| marcozecchini | 0:9fca2b23d0ba | 654 | #endif |
| marcozecchini | 0:9fca2b23d0ba | 655 | |
| marcozecchini | 0:9fca2b23d0ba | 656 | #endif /* __STM32F3xx_LL_CORTEX_H */ |
| marcozecchini | 0:9fca2b23d0ba | 657 | |
| marcozecchini | 0:9fca2b23d0ba | 658 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |