Marco Zecchini / Mbed OS Example_RTOS

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mbed-os/targets/TARGET_NUVOTON/TARGET_NANO100/device/StdDriver/nano100_adc.c@0:9fca2b23d0ba, 2019-02-23 (annotated)

Committer:
marcozecchini
Date:
Sat Feb 23 12:13:36 2019 +0000
Revision:
0:9fca2b23d0ba
final commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
marcozecchini 0:9fca2b23d0ba 1 /**************************************************************************//**
marcozecchini 0:9fca2b23d0ba 2 * @file adc.c
marcozecchini 0:9fca2b23d0ba 3 * @version V1.00
marcozecchini 0:9fca2b23d0ba 4 * $Revision: 7 $
marcozecchini 0:9fca2b23d0ba 5 * $Date: 14/10/06 6:00p $
marcozecchini 0:9fca2b23d0ba 6 * @brief NANO100 series ADC driver source file
marcozecchini 0:9fca2b23d0ba 7 *
marcozecchini 0:9fca2b23d0ba 8 * @note
marcozecchini 0:9fca2b23d0ba 9 * Copyright (C) 2013-2014 Nuvoton Technology Corp. All rights reserved.
marcozecchini 0:9fca2b23d0ba 10 *****************************************************************************/
marcozecchini 0:9fca2b23d0ba 11 #include "Nano100Series.h"
marcozecchini 0:9fca2b23d0ba 12
marcozecchini 0:9fca2b23d0ba 13 /** @addtogroup NANO100_Device_Driver NANO100 Device Driver
marcozecchini 0:9fca2b23d0ba 14 @{
marcozecchini 0:9fca2b23d0ba 15 */
marcozecchini 0:9fca2b23d0ba 16
marcozecchini 0:9fca2b23d0ba 17 /** @addtogroup NANO100_ADC_Driver ADC Driver
marcozecchini 0:9fca2b23d0ba 18 @{
marcozecchini 0:9fca2b23d0ba 19 */
marcozecchini 0:9fca2b23d0ba 20
marcozecchini 0:9fca2b23d0ba 21
marcozecchini 0:9fca2b23d0ba 22 /** @addtogroup NANO100_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
marcozecchini 0:9fca2b23d0ba 23 @{
marcozecchini 0:9fca2b23d0ba 24 */
marcozecchini 0:9fca2b23d0ba 25
marcozecchini 0:9fca2b23d0ba 26 /**
marcozecchini 0:9fca2b23d0ba 27 * @brief This API configures ADC module to be ready for convert the input from selected channel
marcozecchini 0:9fca2b23d0ba 28 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 29 * @param[in] u32InputMode Input mode (single-end/differential). Valid values are:
marcozecchini 0:9fca2b23d0ba 30 * - \ref ADC_INPUT_MODE_SINGLE_END
marcozecchini 0:9fca2b23d0ba 31 * - \ref ADC_INPUT_MODE_DIFFERENTIAL
marcozecchini 0:9fca2b23d0ba 32 * @param[in] u32OpMode Operation mode (single/single cycle/continuous). Valid values are:
marcozecchini 0:9fca2b23d0ba 33 * - \ref ADC_OPERATION_MODE_SINGLE
marcozecchini 0:9fca2b23d0ba 34 * - \ref ADC_OPERATION_MODE_SINGLE_CYCLE
marcozecchini 0:9fca2b23d0ba 35 * - \ref ADC_OPERATION_MODE_CONTINUOUS
marcozecchini 0:9fca2b23d0ba 36 * @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
marcozecchini 0:9fca2b23d0ba 37 * @return None
marcozecchini 0:9fca2b23d0ba 38 * @note This API does not turn on ADC power nor does trigger ADC conversion
marcozecchini 0:9fca2b23d0ba 39 */
marcozecchini 0:9fca2b23d0ba 40 void ADC_Open(ADC_T *adc,
marcozecchini 0:9fca2b23d0ba 41 uint32_t u32InputMode,
marcozecchini 0:9fca2b23d0ba 42 uint32_t u32OpMode,
marcozecchini 0:9fca2b23d0ba 43 uint32_t u32ChMask)
marcozecchini 0:9fca2b23d0ba 44 {
marcozecchini 0:9fca2b23d0ba 45
marcozecchini 0:9fca2b23d0ba 46 ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32InputMode;
marcozecchini 0:9fca2b23d0ba 47 ADC->CR = (ADC->CR & ~ADC_CR_ADMD_Msk) | u32OpMode;
marcozecchini 0:9fca2b23d0ba 48 ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk);
marcozecchini 0:9fca2b23d0ba 49 ADC->CHEN = u32ChMask;
marcozecchini 0:9fca2b23d0ba 50 return;
marcozecchini 0:9fca2b23d0ba 51 }
marcozecchini 0:9fca2b23d0ba 52
marcozecchini 0:9fca2b23d0ba 53 /**
marcozecchini 0:9fca2b23d0ba 54 * @brief Disable ADC module
marcozecchini 0:9fca2b23d0ba 55 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 56 * @return None
marcozecchini 0:9fca2b23d0ba 57 */
marcozecchini 0:9fca2b23d0ba 58 void ADC_Close(ADC_T *adc)
marcozecchini 0:9fca2b23d0ba 59 {
marcozecchini 0:9fca2b23d0ba 60 SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_ADC_RST_Msk;
marcozecchini 0:9fca2b23d0ba 61 SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_ADC_RST_Msk;
marcozecchini 0:9fca2b23d0ba 62 return;
marcozecchini 0:9fca2b23d0ba 63
marcozecchini 0:9fca2b23d0ba 64 }
marcozecchini 0:9fca2b23d0ba 65
marcozecchini 0:9fca2b23d0ba 66 /**
marcozecchini 0:9fca2b23d0ba 67 * @brief Configure the hardware trigger condition and enable hardware trigger
marcozecchini 0:9fca2b23d0ba 68 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 69 * @param[in] u32Source Decides the hardware trigger source. Valid values are:
marcozecchini 0:9fca2b23d0ba 70 * - \ref ADC_TRIGGER_BY_EXT_PIN
marcozecchini 0:9fca2b23d0ba 71 * @param[in] u32Param While ADC trigger by external pin, this parameter
marcozecchini 0:9fca2b23d0ba 72 * is used to set trigger condition. Valid values are:
marcozecchini 0:9fca2b23d0ba 73 * - \ref ADC_LOW_LEVEL_TRIGGER
marcozecchini 0:9fca2b23d0ba 74 * - \ref ADC_HIGH_LEVEL_TRIGGER
marcozecchini 0:9fca2b23d0ba 75 * - \ref ADC_FALLING_EDGE_TRIGGER
marcozecchini 0:9fca2b23d0ba 76 * - \ref ADC_RISING_EDGE_TRIGGER
marcozecchini 0:9fca2b23d0ba 77 * @return None
marcozecchini 0:9fca2b23d0ba 78 */
marcozecchini 0:9fca2b23d0ba 79 void ADC_EnableHWTrigger(ADC_T *adc,
marcozecchini 0:9fca2b23d0ba 80 uint32_t u32Source,
marcozecchini 0:9fca2b23d0ba 81 uint32_t u32Param)
marcozecchini 0:9fca2b23d0ba 82 {
marcozecchini 0:9fca2b23d0ba 83 ADC->CR &= ~(ADC_CR_TRGE_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGS_Msk);
marcozecchini 0:9fca2b23d0ba 84 ADC->CR |= u32Source | u32Param | ADC_CR_TRGE_Msk;
marcozecchini 0:9fca2b23d0ba 85 return;
marcozecchini 0:9fca2b23d0ba 86 }
marcozecchini 0:9fca2b23d0ba 87
marcozecchini 0:9fca2b23d0ba 88 /**
marcozecchini 0:9fca2b23d0ba 89 * @brief Disable hardware trigger ADC function.
marcozecchini 0:9fca2b23d0ba 90 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 91 * @return None
marcozecchini 0:9fca2b23d0ba 92 */
marcozecchini 0:9fca2b23d0ba 93 void ADC_DisableHWTrigger(ADC_T *adc)
marcozecchini 0:9fca2b23d0ba 94 {
marcozecchini 0:9fca2b23d0ba 95 ADC->CR &= ~(ADC_CR_TRGS_Msk | ADC_CR_TRGCOND_Msk | ADC_CR_TRGE_Msk);
marcozecchini 0:9fca2b23d0ba 96 return;
marcozecchini 0:9fca2b23d0ba 97 }
marcozecchini 0:9fca2b23d0ba 98
marcozecchini 0:9fca2b23d0ba 99 /**
marcozecchini 0:9fca2b23d0ba 100 * @brief Config and enable timer trigger
marcozecchini 0:9fca2b23d0ba 101 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 102 * @param[in] u32Source Decides which timer trigger ADC. Valid values are: 0 ~ 3
marcozecchini 0:9fca2b23d0ba 103 * @param[in] u32PDMACnt When timer event occurred, PDMA will transfer u32PDMACnt+1 ADC result
marcozecchini 0:9fca2b23d0ba 104 * @return None
marcozecchini 0:9fca2b23d0ba 105 */
marcozecchini 0:9fca2b23d0ba 106 void ADC_EnableTimerTrigger(ADC_T *adc,
marcozecchini 0:9fca2b23d0ba 107 uint32_t u32Source,
marcozecchini 0:9fca2b23d0ba 108 uint32_t u32PDMACnt)
marcozecchini 0:9fca2b23d0ba 109 {
marcozecchini 0:9fca2b23d0ba 110 ADC->CR &= ~(ADC_CR_TMPDMACNT_Msk | ADC_CR_TMSEL_Msk);
marcozecchini 0:9fca2b23d0ba 111 ADC->CR |= (u32PDMACnt << ADC_CR_TMPDMACNT_Pos) | (u32Source << ADC_CR_TMSEL_Pos) | ADC_CR_TMTRGMOD_Msk;
marcozecchini 0:9fca2b23d0ba 112
marcozecchini 0:9fca2b23d0ba 113 return;
marcozecchini 0:9fca2b23d0ba 114 }
marcozecchini 0:9fca2b23d0ba 115
marcozecchini 0:9fca2b23d0ba 116 /**
marcozecchini 0:9fca2b23d0ba 117 * @brief Disable timer trigger ADC function.
marcozecchini 0:9fca2b23d0ba 118 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 119 * @return None
marcozecchini 0:9fca2b23d0ba 120 */
marcozecchini 0:9fca2b23d0ba 121 void ADC_DisableTimerTrigger(ADC_T *adc)
marcozecchini 0:9fca2b23d0ba 122 {
marcozecchini 0:9fca2b23d0ba 123 ADC->CR &= ~ADC_CR_TMTRGMOD_Msk;
marcozecchini 0:9fca2b23d0ba 124
marcozecchini 0:9fca2b23d0ba 125 return;
marcozecchini 0:9fca2b23d0ba 126 }
marcozecchini 0:9fca2b23d0ba 127
marcozecchini 0:9fca2b23d0ba 128 /**
marcozecchini 0:9fca2b23d0ba 129 * @brief Configure the extended sampling time
marcozecchini 0:9fca2b23d0ba 130 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 131 * @param[in] u32ChNum The channel number
marcozecchini 0:9fca2b23d0ba 132 * @param[in] u32SampleTime Decides the extend sampling counter. Valid values are 0 ~ 15
marcozecchini 0:9fca2b23d0ba 133 * @return None
marcozecchini 0:9fca2b23d0ba 134 */
marcozecchini 0:9fca2b23d0ba 135 void ADC_SetExtraSampleTime(ADC_T *adc,
marcozecchini 0:9fca2b23d0ba 136 uint32_t u32ChNum,
marcozecchini 0:9fca2b23d0ba 137 uint32_t u32SampleTime)
marcozecchini 0:9fca2b23d0ba 138 {
marcozecchini 0:9fca2b23d0ba 139
marcozecchini 0:9fca2b23d0ba 140 if (u32ChNum < 8)
marcozecchini 0:9fca2b23d0ba 141 ADC->SMPLCNT0 = (ADC->SMPLCNT0 & ~(ADC_SMPLCNT0_CH0SAMPCNT_Msk << (u32ChNum * 4))) | (u32SampleTime << (u32ChNum * 4));
marcozecchini 0:9fca2b23d0ba 142 else if (u32ChNum < 12)
marcozecchini 0:9fca2b23d0ba 143 ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~(ADC_SMPLCNT1_CH8SAMPCNT_Msk << ((u32ChNum - 8) * 4))) | (u32SampleTime << ((u32ChNum - 8 ) * 4));
marcozecchini 0:9fca2b23d0ba 144 else
marcozecchini 0:9fca2b23d0ba 145 ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~ADC_SMPLCNT1_INTCHSAMPCNT_Msk) | (u32SampleTime << ADC_SMPLCNT1_INTCHSAMPCNT_Pos);
marcozecchini 0:9fca2b23d0ba 146 }
marcozecchini 0:9fca2b23d0ba 147
marcozecchini 0:9fca2b23d0ba 148 /**
marcozecchini 0:9fca2b23d0ba 149 * @brief Enable the interrupt(s) selected by u32Mask parameter.
marcozecchini 0:9fca2b23d0ba 150 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 151 * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
marcozecchini 0:9fca2b23d0ba 152 * corresponds to a interrupt status. This parameter decides which
marcozecchini 0:9fca2b23d0ba 153 * interrupts will be enabled.
marcozecchini 0:9fca2b23d0ba 154 * - \ref ADC_ADF_INT
marcozecchini 0:9fca2b23d0ba 155 * - \ref ADC_CMP0_INT
marcozecchini 0:9fca2b23d0ba 156 * - \ref ADC_CMP1_INT
marcozecchini 0:9fca2b23d0ba 157 * @return None
marcozecchini 0:9fca2b23d0ba 158 */
marcozecchini 0:9fca2b23d0ba 159 void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
marcozecchini 0:9fca2b23d0ba 160 {
marcozecchini 0:9fca2b23d0ba 161 if(u32Mask & ADC_ADF_INT)
marcozecchini 0:9fca2b23d0ba 162 ADC->CR |= ADC_CR_ADIE_Msk;
marcozecchini 0:9fca2b23d0ba 163 if(u32Mask & ADC_CMP0_INT)
marcozecchini 0:9fca2b23d0ba 164 ADC->CMPR0 |= ADC_CMPR_CMPIE_Msk;
marcozecchini 0:9fca2b23d0ba 165 if(u32Mask & ADC_CMP1_INT)
marcozecchini 0:9fca2b23d0ba 166 ADC->CMPR1 |= ADC_CMPR_CMPIE_Msk;
marcozecchini 0:9fca2b23d0ba 167
marcozecchini 0:9fca2b23d0ba 168 return;
marcozecchini 0:9fca2b23d0ba 169 }
marcozecchini 0:9fca2b23d0ba 170
marcozecchini 0:9fca2b23d0ba 171 /**
marcozecchini 0:9fca2b23d0ba 172 * @brief Disable the interrupt(s) selected by u32Mask parameter.
marcozecchini 0:9fca2b23d0ba 173 * @param[in] adc Base address of ADC module
marcozecchini 0:9fca2b23d0ba 174 * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
marcozecchini 0:9fca2b23d0ba 175 * corresponds to a interrupt status. This parameter decides which
marcozecchini 0:9fca2b23d0ba 176 * interrupts will be disabled.
marcozecchini 0:9fca2b23d0ba 177 * - \ref ADC_ADF_INT
marcozecchini 0:9fca2b23d0ba 178 * - \ref ADC_CMP0_INT
marcozecchini 0:9fca2b23d0ba 179 * - \ref ADC_CMP1_INT
marcozecchini 0:9fca2b23d0ba 180 * @return None
marcozecchini 0:9fca2b23d0ba 181 */
marcozecchini 0:9fca2b23d0ba 182 void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
marcozecchini 0:9fca2b23d0ba 183 {
marcozecchini 0:9fca2b23d0ba 184 if(u32Mask & ADC_ADF_INT)
marcozecchini 0:9fca2b23d0ba 185 ADC->CR &= ~ADC_CR_ADIE_Msk;
marcozecchini 0:9fca2b23d0ba 186 if(u32Mask & ADC_CMP0_INT)
marcozecchini 0:9fca2b23d0ba 187 ADC->CMPR0 &= ~ADC_CMPR_CMPIE_Msk;
marcozecchini 0:9fca2b23d0ba 188 if(u32Mask & ADC_CMP1_INT)
marcozecchini 0:9fca2b23d0ba 189 ADC->CMPR1 &= ~ADC_CMPR_CMPIE_Msk;
marcozecchini 0:9fca2b23d0ba 190
marcozecchini 0:9fca2b23d0ba 191 return;
marcozecchini 0:9fca2b23d0ba 192 }
marcozecchini 0:9fca2b23d0ba 193
marcozecchini 0:9fca2b23d0ba 194
marcozecchini 0:9fca2b23d0ba 195
marcozecchini 0:9fca2b23d0ba 196 /*@}*/ /* end of group NANO100_ADC_EXPORTED_FUNCTIONS */
marcozecchini 0:9fca2b23d0ba 197
marcozecchini 0:9fca2b23d0ba 198 /*@}*/ /* end of group NANO100_ADC_Driver */
marcozecchini 0:9fca2b23d0ba 199
marcozecchini 0:9fca2b23d0ba 200 /*@}*/ /* end of group NANO100_Device_Driver */
marcozecchini 0:9fca2b23d0ba 201
marcozecchini 0:9fca2b23d0ba 202 /*** (C) COPYRIGHT 2013-2014 Nuvoton Technology Corp. ***/