Marco Zecchini
/
Example_RTOS
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mbed-os/targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spim.h@0:9fca2b23d0ba, 2019-02-23 (annotated)
- Committer:
- marcozecchini
- Date:
- Sat Feb 23 12:13:36 2019 +0000
- Revision:
- 0:9fca2b23d0ba
final commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| marcozecchini | 0:9fca2b23d0ba | 1 | /**************************************************************************//** |
| marcozecchini | 0:9fca2b23d0ba | 2 | * @file spim.h |
| marcozecchini | 0:9fca2b23d0ba | 3 | * @version V1.00 |
| marcozecchini | 0:9fca2b23d0ba | 4 | * @brief M480 series SPIM driver header file |
| marcozecchini | 0:9fca2b23d0ba | 5 | * |
| marcozecchini | 0:9fca2b23d0ba | 6 | * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. |
| marcozecchini | 0:9fca2b23d0ba | 7 | *****************************************************************************/ |
| marcozecchini | 0:9fca2b23d0ba | 8 | #ifndef __SPIM_H__ |
| marcozecchini | 0:9fca2b23d0ba | 9 | #define __SPIM_H__ |
| marcozecchini | 0:9fca2b23d0ba | 10 | |
| marcozecchini | 0:9fca2b23d0ba | 11 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 12 | /* Include related headers */ |
| marcozecchini | 0:9fca2b23d0ba | 13 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 14 | |
| marcozecchini | 0:9fca2b23d0ba | 15 | #ifdef __cplusplus |
| marcozecchini | 0:9fca2b23d0ba | 16 | extern "C" |
| marcozecchini | 0:9fca2b23d0ba | 17 | { |
| marcozecchini | 0:9fca2b23d0ba | 18 | #endif |
| marcozecchini | 0:9fca2b23d0ba | 19 | |
| marcozecchini | 0:9fca2b23d0ba | 20 | |
| marcozecchini | 0:9fca2b23d0ba | 21 | /** @addtogroup M480_Device_Driver M480 Device Driver |
| marcozecchini | 0:9fca2b23d0ba | 22 | @{ |
| marcozecchini | 0:9fca2b23d0ba | 23 | */ |
| marcozecchini | 0:9fca2b23d0ba | 24 | |
| marcozecchini | 0:9fca2b23d0ba | 25 | /** @addtogroup M480_SPIM_Driver SPIM Driver |
| marcozecchini | 0:9fca2b23d0ba | 26 | @{ |
| marcozecchini | 0:9fca2b23d0ba | 27 | */ |
| marcozecchini | 0:9fca2b23d0ba | 28 | |
| marcozecchini | 0:9fca2b23d0ba | 29 | |
| marcozecchini | 0:9fca2b23d0ba | 30 | /** @addtogroup M480_SPIM_EXPORTED_CONSTANTS SPIM Exported Constants |
| marcozecchini | 0:9fca2b23d0ba | 31 | @{ |
| marcozecchini | 0:9fca2b23d0ba | 32 | */ |
| marcozecchini | 0:9fca2b23d0ba | 33 | |
| marcozecchini | 0:9fca2b23d0ba | 34 | #define SPIM_DMM_MAP_ADDR 0x8000000UL /*!< DMM mode memory map base address \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 35 | #define SPIM_DMM_SIZE 0x2000000UL /*!< DMM mode memory mapping size \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 36 | #define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 37 | #define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 38 | |
| marcozecchini | 0:9fca2b23d0ba | 39 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 40 | /* SPIM_CTL0 constant definitions */ |
| marcozecchini | 0:9fca2b23d0ba | 41 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 42 | #define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 43 | #define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 44 | #define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 45 | #define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 46 | #define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 47 | #define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 48 | #define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 49 | #define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 50 | |
| marcozecchini | 0:9fca2b23d0ba | 51 | #define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 52 | #define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 53 | #define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 54 | #define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 55 | #define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 56 | |
| marcozecchini | 0:9fca2b23d0ba | 57 | #define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 58 | #define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 59 | #define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 60 | #define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 61 | #define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 62 | #define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 63 | #define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 64 | #define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ |
| marcozecchini | 0:9fca2b23d0ba | 65 | |
| marcozecchini | 0:9fca2b23d0ba | 66 | /** @cond HIDDEN_SYMBOLS */ |
| marcozecchini | 0:9fca2b23d0ba | 67 | |
| marcozecchini | 0:9fca2b23d0ba | 68 | typedef enum { |
| marcozecchini | 0:9fca2b23d0ba | 69 | MFGID_UNKNOW = 0x00U, |
| marcozecchini | 0:9fca2b23d0ba | 70 | MFGID_SPANSION = 0x01U, |
| marcozecchini | 0:9fca2b23d0ba | 71 | MFGID_EON = 0x1CU, |
| marcozecchini | 0:9fca2b23d0ba | 72 | MFGID_ISSI = 0x7FU, |
| marcozecchini | 0:9fca2b23d0ba | 73 | MFGID_MXIC = 0xC2U, |
| marcozecchini | 0:9fca2b23d0ba | 74 | MFGID_WINBOND = 0xEFU |
| marcozecchini | 0:9fca2b23d0ba | 75 | } |
| marcozecchini | 0:9fca2b23d0ba | 76 | E_MFGID; |
| marcozecchini | 0:9fca2b23d0ba | 77 | |
| marcozecchini | 0:9fca2b23d0ba | 78 | /* Flash opcodes. */ |
| marcozecchini | 0:9fca2b23d0ba | 79 | #define OPCODE_WREN 0x06U /* Write enable */ |
| marcozecchini | 0:9fca2b23d0ba | 80 | #define OPCODE_RDSR 0x05U /* Read status register #1*/ |
| marcozecchini | 0:9fca2b23d0ba | 81 | #define OPCODE_WRSR 0x01U /* Write status register #1 */ |
| marcozecchini | 0:9fca2b23d0ba | 82 | #define OPCODE_RDSR2 0x35U /* Read status register #2*/ |
| marcozecchini | 0:9fca2b23d0ba | 83 | #define OPCODE_WRSR2 0x31U /* Write status register #2 */ |
| marcozecchini | 0:9fca2b23d0ba | 84 | #define OPCODE_RDSR3 0x15U /* Read status register #3*/ |
| marcozecchini | 0:9fca2b23d0ba | 85 | #define OPCODE_WRSR3 0x11U /* Write status register #3 */ |
| marcozecchini | 0:9fca2b23d0ba | 86 | #define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */ |
| marcozecchini | 0:9fca2b23d0ba | 87 | #define OPCODE_SE_4K 0x20U /* Erase 4KB sector */ |
| marcozecchini | 0:9fca2b23d0ba | 88 | #define OPCODE_BE_32K 0x52U /* Erase 32KB block */ |
| marcozecchini | 0:9fca2b23d0ba | 89 | #define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */ |
| marcozecchini | 0:9fca2b23d0ba | 90 | #define OPCODE_BE_64K 0xd8U /* Erase 64KB block */ |
| marcozecchini | 0:9fca2b23d0ba | 91 | #define OPCODE_READ_ID 0x90U /* Read ID */ |
| marcozecchini | 0:9fca2b23d0ba | 92 | #define OPCODE_RDID 0x9fU /* Read JEDEC ID */ |
| marcozecchini | 0:9fca2b23d0ba | 93 | #define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */ |
| marcozecchini | 0:9fca2b23d0ba | 94 | #define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */ |
| marcozecchini | 0:9fca2b23d0ba | 95 | #define OPCODE_NORM_READ 0x03U /* Read data bytes */ |
| marcozecchini | 0:9fca2b23d0ba | 96 | #define OPCODE_FAST_READ 0x0bU /* Read data bytes */ |
| marcozecchini | 0:9fca2b23d0ba | 97 | #define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */ |
| marcozecchini | 0:9fca2b23d0ba | 98 | #define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */ |
| marcozecchini | 0:9fca2b23d0ba | 99 | |
| marcozecchini | 0:9fca2b23d0ba | 100 | /* Used for SST flashes only. */ |
| marcozecchini | 0:9fca2b23d0ba | 101 | #define OPCODE_BP 0x02U /* Byte program */ |
| marcozecchini | 0:9fca2b23d0ba | 102 | #define OPCODE_WRDI 0x04U /* Write disable */ |
| marcozecchini | 0:9fca2b23d0ba | 103 | #define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */ |
| marcozecchini | 0:9fca2b23d0ba | 104 | |
| marcozecchini | 0:9fca2b23d0ba | 105 | /* Used for Macronix flashes only. */ |
| marcozecchini | 0:9fca2b23d0ba | 106 | #define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */ |
| marcozecchini | 0:9fca2b23d0ba | 107 | #define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */ |
| marcozecchini | 0:9fca2b23d0ba | 108 | |
| marcozecchini | 0:9fca2b23d0ba | 109 | #define OPCODE_RDSCUR 0x2bU |
| marcozecchini | 0:9fca2b23d0ba | 110 | #define OPCODE_WRSCUR 0x2fU |
| marcozecchini | 0:9fca2b23d0ba | 111 | |
| marcozecchini | 0:9fca2b23d0ba | 112 | #define OPCODE_RSTEN 0x66U |
| marcozecchini | 0:9fca2b23d0ba | 113 | #define OPCODE_RST 0x99U |
| marcozecchini | 0:9fca2b23d0ba | 114 | |
| marcozecchini | 0:9fca2b23d0ba | 115 | #define OPCODE_ENQPI 0x38U |
| marcozecchini | 0:9fca2b23d0ba | 116 | #define OPCODE_EXQPI 0xFFU |
| marcozecchini | 0:9fca2b23d0ba | 117 | |
| marcozecchini | 0:9fca2b23d0ba | 118 | /* Status Register bits. */ |
| marcozecchini | 0:9fca2b23d0ba | 119 | #define SR_WIP 0x1U /* Write in progress */ |
| marcozecchini | 0:9fca2b23d0ba | 120 | #define SR_WEL 0x2U /* Write enable latch */ |
| marcozecchini | 0:9fca2b23d0ba | 121 | #define SR_QE 0x40U /* Quad Enable for MXIC */ |
| marcozecchini | 0:9fca2b23d0ba | 122 | /* Status Register #2 bits. */ |
| marcozecchini | 0:9fca2b23d0ba | 123 | #define SR2_QE 0x2U /* Quad Enable for Winbond */ |
| marcozecchini | 0:9fca2b23d0ba | 124 | /* meaning of other SR_* bits may differ between vendors */ |
| marcozecchini | 0:9fca2b23d0ba | 125 | #define SR_BP0 0x4U /* Block protect 0 */ |
| marcozecchini | 0:9fca2b23d0ba | 126 | #define SR_BP1 0x8U /* Block protect 1 */ |
| marcozecchini | 0:9fca2b23d0ba | 127 | #define SR_BP2 0x10U /* Block protect 2 */ |
| marcozecchini | 0:9fca2b23d0ba | 128 | #define SR_SRWD 0x80U /* SR write protect */ |
| marcozecchini | 0:9fca2b23d0ba | 129 | #define SR3_ADR 0x01U /* 4-byte u32Address mode */ |
| marcozecchini | 0:9fca2b23d0ba | 130 | |
| marcozecchini | 0:9fca2b23d0ba | 131 | #define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */ |
| marcozecchini | 0:9fca2b23d0ba | 132 | |
| marcozecchini | 0:9fca2b23d0ba | 133 | /** @endcond HIDDEN_SYMBOLS */ |
| marcozecchini | 0:9fca2b23d0ba | 134 | |
| marcozecchini | 0:9fca2b23d0ba | 135 | /*@}*/ /* end of group M480_SPIM_EXPORTED_CONSTANTS */ |
| marcozecchini | 0:9fca2b23d0ba | 136 | |
| marcozecchini | 0:9fca2b23d0ba | 137 | |
| marcozecchini | 0:9fca2b23d0ba | 138 | /** @addtogroup M480_SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions |
| marcozecchini | 0:9fca2b23d0ba | 139 | @{ |
| marcozecchini | 0:9fca2b23d0ba | 140 | */ |
| marcozecchini | 0:9fca2b23d0ba | 141 | |
| marcozecchini | 0:9fca2b23d0ba | 142 | |
| marcozecchini | 0:9fca2b23d0ba | 143 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 144 | /* Define Macros and functions */ |
| marcozecchini | 0:9fca2b23d0ba | 145 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 146 | |
| marcozecchini | 0:9fca2b23d0ba | 147 | /** |
| marcozecchini | 0:9fca2b23d0ba | 148 | * @details Enable cipher. |
| marcozecchini | 0:9fca2b23d0ba | 149 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 150 | */ |
| marcozecchini | 0:9fca2b23d0ba | 151 | #define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 152 | |
| marcozecchini | 0:9fca2b23d0ba | 153 | /** |
| marcozecchini | 0:9fca2b23d0ba | 154 | * @details Disable cipher. |
| marcozecchini | 0:9fca2b23d0ba | 155 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 156 | */ |
| marcozecchini | 0:9fca2b23d0ba | 157 | #define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 158 | |
| marcozecchini | 0:9fca2b23d0ba | 159 | /** |
| marcozecchini | 0:9fca2b23d0ba | 160 | * @details Enable cipher balance |
| marcozecchini | 0:9fca2b23d0ba | 161 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 162 | */ |
| marcozecchini | 0:9fca2b23d0ba | 163 | #define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 164 | |
| marcozecchini | 0:9fca2b23d0ba | 165 | /** |
| marcozecchini | 0:9fca2b23d0ba | 166 | * @details Disable cipher balance |
| marcozecchini | 0:9fca2b23d0ba | 167 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 168 | */ |
| marcozecchini | 0:9fca2b23d0ba | 169 | #define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 170 | |
| marcozecchini | 0:9fca2b23d0ba | 171 | /** |
| marcozecchini | 0:9fca2b23d0ba | 172 | * @details Set 4-byte address to be enabled/disabled. |
| marcozecchini | 0:9fca2b23d0ba | 173 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 174 | */ |
| marcozecchini | 0:9fca2b23d0ba | 175 | #define SPIM_SET_4BYTE_ADDR_EN(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 176 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 177 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 178 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 179 | |
| marcozecchini | 0:9fca2b23d0ba | 180 | /** |
| marcozecchini | 0:9fca2b23d0ba | 181 | * @details Enable SPIM interrupt |
| marcozecchini | 0:9fca2b23d0ba | 182 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 183 | */ |
| marcozecchini | 0:9fca2b23d0ba | 184 | #define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 185 | |
| marcozecchini | 0:9fca2b23d0ba | 186 | /** |
| marcozecchini | 0:9fca2b23d0ba | 187 | * @details Disable SPIM interrupt |
| marcozecchini | 0:9fca2b23d0ba | 188 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 189 | */ |
| marcozecchini | 0:9fca2b23d0ba | 190 | #define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 191 | |
| marcozecchini | 0:9fca2b23d0ba | 192 | /** |
| marcozecchini | 0:9fca2b23d0ba | 193 | * @details Is interrupt flag on. |
| marcozecchini | 0:9fca2b23d0ba | 194 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 195 | */ |
| marcozecchini | 0:9fca2b23d0ba | 196 | #define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL) |
| marcozecchini | 0:9fca2b23d0ba | 197 | |
| marcozecchini | 0:9fca2b23d0ba | 198 | /** |
| marcozecchini | 0:9fca2b23d0ba | 199 | * @details Clear interrupt flag. |
| marcozecchini | 0:9fca2b23d0ba | 200 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 201 | */ |
| marcozecchini | 0:9fca2b23d0ba | 202 | #define SPIM_CLR_INT() \ |
| marcozecchini | 0:9fca2b23d0ba | 203 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 204 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 205 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 206 | |
| marcozecchini | 0:9fca2b23d0ba | 207 | /** |
| marcozecchini | 0:9fca2b23d0ba | 208 | * @details Set transmit/receive bit length |
| marcozecchini | 0:9fca2b23d0ba | 209 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 210 | */ |
| marcozecchini | 0:9fca2b23d0ba | 211 | #define SPIM_SET_DATA_WIDTH(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 212 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 213 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 214 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 215 | |
| marcozecchini | 0:9fca2b23d0ba | 216 | /** |
| marcozecchini | 0:9fca2b23d0ba | 217 | * @details Get data transmit/receive bit length setting |
| marcozecchini | 0:9fca2b23d0ba | 218 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 219 | */ |
| marcozecchini | 0:9fca2b23d0ba | 220 | #define SPIM_GET_DATA_WIDTH() \ |
| marcozecchini | 0:9fca2b23d0ba | 221 | (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U) |
| marcozecchini | 0:9fca2b23d0ba | 222 | |
| marcozecchini | 0:9fca2b23d0ba | 223 | /** |
| marcozecchini | 0:9fca2b23d0ba | 224 | * @details Set data transmit/receive burst number |
| marcozecchini | 0:9fca2b23d0ba | 225 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 226 | */ |
| marcozecchini | 0:9fca2b23d0ba | 227 | #define SPIM_SET_DATA_NUM(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 228 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 229 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 230 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 231 | |
| marcozecchini | 0:9fca2b23d0ba | 232 | /** |
| marcozecchini | 0:9fca2b23d0ba | 233 | * @details Get data transmit/receive burst number |
| marcozecchini | 0:9fca2b23d0ba | 234 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 235 | */ |
| marcozecchini | 0:9fca2b23d0ba | 236 | #define SPIM_GET_DATA_NUM() \ |
| marcozecchini | 0:9fca2b23d0ba | 237 | (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U) |
| marcozecchini | 0:9fca2b23d0ba | 238 | |
| marcozecchini | 0:9fca2b23d0ba | 239 | /** |
| marcozecchini | 0:9fca2b23d0ba | 240 | * @details Enable Single Input mode. |
| marcozecchini | 0:9fca2b23d0ba | 241 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 242 | */ |
| marcozecchini | 0:9fca2b23d0ba | 243 | #define SPIM_ENABLE_SING_INPUT_MODE() \ |
| marcozecchini | 0:9fca2b23d0ba | 244 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 245 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \ |
| marcozecchini | 0:9fca2b23d0ba | 246 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 247 | |
| marcozecchini | 0:9fca2b23d0ba | 248 | /** |
| marcozecchini | 0:9fca2b23d0ba | 249 | * @details Enable Single Output mode. |
| marcozecchini | 0:9fca2b23d0ba | 250 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 251 | */ |
| marcozecchini | 0:9fca2b23d0ba | 252 | #define SPIM_ENABLE_SING_OUTPUT_MODE() \ |
| marcozecchini | 0:9fca2b23d0ba | 253 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 254 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \ |
| marcozecchini | 0:9fca2b23d0ba | 255 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 256 | |
| marcozecchini | 0:9fca2b23d0ba | 257 | /** |
| marcozecchini | 0:9fca2b23d0ba | 258 | * @details Enable Dual Input mode. |
| marcozecchini | 0:9fca2b23d0ba | 259 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 260 | */ |
| marcozecchini | 0:9fca2b23d0ba | 261 | #define SPIM_ENABLE_DUAL_INPUT_MODE() \ |
| marcozecchini | 0:9fca2b23d0ba | 262 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 263 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \ |
| marcozecchini | 0:9fca2b23d0ba | 264 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 265 | |
| marcozecchini | 0:9fca2b23d0ba | 266 | /** |
| marcozecchini | 0:9fca2b23d0ba | 267 | * @details Enable Dual Output mode. |
| marcozecchini | 0:9fca2b23d0ba | 268 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 269 | */ |
| marcozecchini | 0:9fca2b23d0ba | 270 | #define SPIM_ENABLE_DUAL_OUTPUT_MODE() \ |
| marcozecchini | 0:9fca2b23d0ba | 271 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 272 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \ |
| marcozecchini | 0:9fca2b23d0ba | 273 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 274 | |
| marcozecchini | 0:9fca2b23d0ba | 275 | /** |
| marcozecchini | 0:9fca2b23d0ba | 276 | * @details Enable Quad Input mode. |
| marcozecchini | 0:9fca2b23d0ba | 277 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 278 | */ |
| marcozecchini | 0:9fca2b23d0ba | 279 | #define SPIM_ENABLE_QUAD_INPUT_MODE() \ |
| marcozecchini | 0:9fca2b23d0ba | 280 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 281 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \ |
| marcozecchini | 0:9fca2b23d0ba | 282 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 283 | |
| marcozecchini | 0:9fca2b23d0ba | 284 | /** |
| marcozecchini | 0:9fca2b23d0ba | 285 | * @details Enable Quad Output mode. |
| marcozecchini | 0:9fca2b23d0ba | 286 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 287 | */ |
| marcozecchini | 0:9fca2b23d0ba | 288 | #define SPIM_ENABLE_QUAD_OUTPUT_MODE() \ |
| marcozecchini | 0:9fca2b23d0ba | 289 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 290 | SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \ |
| marcozecchini | 0:9fca2b23d0ba | 291 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 292 | |
| marcozecchini | 0:9fca2b23d0ba | 293 | /** |
| marcozecchini | 0:9fca2b23d0ba | 294 | * @details Set suspend interval which ranges between 0 and 15. |
| marcozecchini | 0:9fca2b23d0ba | 295 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 296 | */ |
| marcozecchini | 0:9fca2b23d0ba | 297 | #define SPIM_SET_SUSP_INTVL(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 298 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 299 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 300 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 301 | |
| marcozecchini | 0:9fca2b23d0ba | 302 | /** |
| marcozecchini | 0:9fca2b23d0ba | 303 | * @details Get suspend interval setting |
| marcozecchini | 0:9fca2b23d0ba | 304 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 305 | */ |
| marcozecchini | 0:9fca2b23d0ba | 306 | #define SPIM_GET_SUSP_INTVL() \ |
| marcozecchini | 0:9fca2b23d0ba | 307 | ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 308 | |
| marcozecchini | 0:9fca2b23d0ba | 309 | /** |
| marcozecchini | 0:9fca2b23d0ba | 310 | * @details Set operation mode. |
| marcozecchini | 0:9fca2b23d0ba | 311 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 312 | */ |
| marcozecchini | 0:9fca2b23d0ba | 313 | #define SPIM_SET_OPMODE(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 314 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 315 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \ |
| marcozecchini | 0:9fca2b23d0ba | 316 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 317 | |
| marcozecchini | 0:9fca2b23d0ba | 318 | /** |
| marcozecchini | 0:9fca2b23d0ba | 319 | * @details Get operation mode. |
| marcozecchini | 0:9fca2b23d0ba | 320 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 321 | */ |
| marcozecchini | 0:9fca2b23d0ba | 322 | #define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 323 | |
| marcozecchini | 0:9fca2b23d0ba | 324 | /** |
| marcozecchini | 0:9fca2b23d0ba | 325 | * @details Set SPIM mode. |
| marcozecchini | 0:9fca2b23d0ba | 326 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 327 | */ |
| marcozecchini | 0:9fca2b23d0ba | 328 | #define SPIM_SET_SPIM_MODE(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 329 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 330 | SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \ |
| marcozecchini | 0:9fca2b23d0ba | 331 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 332 | |
| marcozecchini | 0:9fca2b23d0ba | 333 | /** |
| marcozecchini | 0:9fca2b23d0ba | 334 | * @details Get SPIM mode. |
| marcozecchini | 0:9fca2b23d0ba | 335 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 336 | */ |
| marcozecchini | 0:9fca2b23d0ba | 337 | #define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 338 | |
| marcozecchini | 0:9fca2b23d0ba | 339 | /** |
| marcozecchini | 0:9fca2b23d0ba | 340 | * @details Start operation. |
| marcozecchini | 0:9fca2b23d0ba | 341 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 342 | */ |
| marcozecchini | 0:9fca2b23d0ba | 343 | #define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 344 | |
| marcozecchini | 0:9fca2b23d0ba | 345 | /** |
| marcozecchini | 0:9fca2b23d0ba | 346 | * @details Is engine busy. |
| marcozecchini | 0:9fca2b23d0ba | 347 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 348 | */ |
| marcozecchini | 0:9fca2b23d0ba | 349 | #define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 350 | |
| marcozecchini | 0:9fca2b23d0ba | 351 | /** |
| marcozecchini | 0:9fca2b23d0ba | 352 | * @details Wait for free. |
| marcozecchini | 0:9fca2b23d0ba | 353 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 354 | */ |
| marcozecchini | 0:9fca2b23d0ba | 355 | #define SPIM_WAIT_FREE() \ |
| marcozecchini | 0:9fca2b23d0ba | 356 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 357 | while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \ |
| marcozecchini | 0:9fca2b23d0ba | 358 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 359 | |
| marcozecchini | 0:9fca2b23d0ba | 360 | /** |
| marcozecchini | 0:9fca2b23d0ba | 361 | * @details Enable cache. |
| marcozecchini | 0:9fca2b23d0ba | 362 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 363 | */ |
| marcozecchini | 0:9fca2b23d0ba | 364 | #define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 365 | |
| marcozecchini | 0:9fca2b23d0ba | 366 | /** |
| marcozecchini | 0:9fca2b23d0ba | 367 | * @details Disable cache. |
| marcozecchini | 0:9fca2b23d0ba | 368 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 369 | */ |
| marcozecchini | 0:9fca2b23d0ba | 370 | #define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 371 | |
| marcozecchini | 0:9fca2b23d0ba | 372 | /** |
| marcozecchini | 0:9fca2b23d0ba | 373 | * @details Is cache enabled. |
| marcozecchini | 0:9fca2b23d0ba | 374 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 375 | */ |
| marcozecchini | 0:9fca2b23d0ba | 376 | #define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1) |
| marcozecchini | 0:9fca2b23d0ba | 377 | |
| marcozecchini | 0:9fca2b23d0ba | 378 | /** |
| marcozecchini | 0:9fca2b23d0ba | 379 | * @details Enable CCM |
| marcozecchini | 0:9fca2b23d0ba | 380 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 381 | */ |
| marcozecchini | 0:9fca2b23d0ba | 382 | #define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 383 | |
| marcozecchini | 0:9fca2b23d0ba | 384 | /** |
| marcozecchini | 0:9fca2b23d0ba | 385 | * @details Disable CCM. |
| marcozecchini | 0:9fca2b23d0ba | 386 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 387 | */ |
| marcozecchini | 0:9fca2b23d0ba | 388 | #define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 389 | |
| marcozecchini | 0:9fca2b23d0ba | 390 | /** |
| marcozecchini | 0:9fca2b23d0ba | 391 | * @details Is CCM enabled. |
| marcozecchini | 0:9fca2b23d0ba | 392 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 393 | */ |
| marcozecchini | 0:9fca2b23d0ba | 394 | #define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 395 | |
| marcozecchini | 0:9fca2b23d0ba | 396 | /** |
| marcozecchini | 0:9fca2b23d0ba | 397 | * @details Invalidate cache. |
| marcozecchini | 0:9fca2b23d0ba | 398 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 399 | */ |
| marcozecchini | 0:9fca2b23d0ba | 400 | #define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 401 | |
| marcozecchini | 0:9fca2b23d0ba | 402 | /** |
| marcozecchini | 0:9fca2b23d0ba | 403 | * @details Set SS(Select Active) to active level. |
| marcozecchini | 0:9fca2b23d0ba | 404 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 405 | */ |
| marcozecchini | 0:9fca2b23d0ba | 406 | #define SPIM_SET_SS_EN(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 407 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 408 | (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \ |
| marcozecchini | 0:9fca2b23d0ba | 409 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 410 | |
| marcozecchini | 0:9fca2b23d0ba | 411 | /** |
| marcozecchini | 0:9fca2b23d0ba | 412 | * @details Is SS(Select Active) in active level. |
| marcozecchini | 0:9fca2b23d0ba | 413 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 414 | */ |
| marcozecchini | 0:9fca2b23d0ba | 415 | #define SPIM_GET_SS_EN() \ |
| marcozecchini | 0:9fca2b23d0ba | 416 | (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk)) |
| marcozecchini | 0:9fca2b23d0ba | 417 | |
| marcozecchini | 0:9fca2b23d0ba | 418 | /** |
| marcozecchini | 0:9fca2b23d0ba | 419 | * @details Set active level of slave select to be high/low. |
| marcozecchini | 0:9fca2b23d0ba | 420 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 421 | */ |
| marcozecchini | 0:9fca2b23d0ba | 422 | #define SPIM_SET_SS_ACTLVL(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 423 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 424 | (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \ |
| marcozecchini | 0:9fca2b23d0ba | 425 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 426 | |
| marcozecchini | 0:9fca2b23d0ba | 427 | /** |
| marcozecchini | 0:9fca2b23d0ba | 428 | * @details Set idle time interval |
| marcozecchini | 0:9fca2b23d0ba | 429 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 430 | */ |
| marcozecchini | 0:9fca2b23d0ba | 431 | #define SPIM_SET_IDL_INTVL(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 432 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 433 | SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 434 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 435 | |
| marcozecchini | 0:9fca2b23d0ba | 436 | /** |
| marcozecchini | 0:9fca2b23d0ba | 437 | * @details Get idle time interval setting |
| marcozecchini | 0:9fca2b23d0ba | 438 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 439 | */ |
| marcozecchini | 0:9fca2b23d0ba | 440 | #define SPIM_GET_IDL_INTVL() \ |
| marcozecchini | 0:9fca2b23d0ba | 441 | ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 442 | |
| marcozecchini | 0:9fca2b23d0ba | 443 | /** |
| marcozecchini | 0:9fca2b23d0ba | 444 | * @details Set SPIM clock divider |
| marcozecchini | 0:9fca2b23d0ba | 445 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 446 | */ |
| marcozecchini | 0:9fca2b23d0ba | 447 | #define SPIM_SET_CLOCK_DIVIDER(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 448 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 449 | SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 450 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 451 | |
| marcozecchini | 0:9fca2b23d0ba | 452 | /** |
| marcozecchini | 0:9fca2b23d0ba | 453 | * @details Get SPIM current clock divider setting |
| marcozecchini | 0:9fca2b23d0ba | 454 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 455 | */ |
| marcozecchini | 0:9fca2b23d0ba | 456 | #define SPIM_GET_CLOCK_DIVIDER() \ |
| marcozecchini | 0:9fca2b23d0ba | 457 | ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 458 | |
| marcozecchini | 0:9fca2b23d0ba | 459 | /** |
| marcozecchini | 0:9fca2b23d0ba | 460 | * @details Set SPI flash deselect time interval of DMA write mode |
| marcozecchini | 0:9fca2b23d0ba | 461 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 462 | */ |
| marcozecchini | 0:9fca2b23d0ba | 463 | #define SPIM_SET_RXCLKDLY_DWDELSEL(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 464 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 465 | (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \ |
| marcozecchini | 0:9fca2b23d0ba | 466 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 467 | |
| marcozecchini | 0:9fca2b23d0ba | 468 | /** |
| marcozecchini | 0:9fca2b23d0ba | 469 | * @details Get SPI flash deselect time interval of DMA write mode |
| marcozecchini | 0:9fca2b23d0ba | 470 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 471 | */ |
| marcozecchini | 0:9fca2b23d0ba | 472 | #define SPIM_GET_RXCLKDLY_DWDELSEL() \ |
| marcozecchini | 0:9fca2b23d0ba | 473 | ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 474 | |
| marcozecchini | 0:9fca2b23d0ba | 475 | /** |
| marcozecchini | 0:9fca2b23d0ba | 476 | * @details Set sampling clock delay selection for received data |
| marcozecchini | 0:9fca2b23d0ba | 477 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 478 | */ |
| marcozecchini | 0:9fca2b23d0ba | 479 | #define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 480 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 481 | (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \ |
| marcozecchini | 0:9fca2b23d0ba | 482 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 483 | |
| marcozecchini | 0:9fca2b23d0ba | 484 | /** |
| marcozecchini | 0:9fca2b23d0ba | 485 | * @details Get sampling clock delay selection for received data |
| marcozecchini | 0:9fca2b23d0ba | 486 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 487 | */ |
| marcozecchini | 0:9fca2b23d0ba | 488 | #define SPIM_GET_RXCLKDLY_RDDLYSEL() \ |
| marcozecchini | 0:9fca2b23d0ba | 489 | ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 490 | |
| marcozecchini | 0:9fca2b23d0ba | 491 | /** |
| marcozecchini | 0:9fca2b23d0ba | 492 | * @details Set sampling clock edge selection for received data |
| marcozecchini | 0:9fca2b23d0ba | 493 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 494 | */ |
| marcozecchini | 0:9fca2b23d0ba | 495 | #define SPIM_SET_RXCLKDLY_RDEDGE() \ |
| marcozecchini | 0:9fca2b23d0ba | 496 | (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \ |
| marcozecchini | 0:9fca2b23d0ba | 497 | |
| marcozecchini | 0:9fca2b23d0ba | 498 | /** |
| marcozecchini | 0:9fca2b23d0ba | 499 | * @details Get sampling clock edge selection for received data |
| marcozecchini | 0:9fca2b23d0ba | 500 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 501 | */ |
| marcozecchini | 0:9fca2b23d0ba | 502 | #define SPIM_CLR_RXCLKDLY_RDEDGE() \ |
| marcozecchini | 0:9fca2b23d0ba | 503 | (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 504 | |
| marcozecchini | 0:9fca2b23d0ba | 505 | /** |
| marcozecchini | 0:9fca2b23d0ba | 506 | * @details Set mode bits data for continuous read mode |
| marcozecchini | 0:9fca2b23d0ba | 507 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 508 | */ |
| marcozecchini | 0:9fca2b23d0ba | 509 | #define SPIM_SET_DMMCTL_CRMDAT(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 510 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 511 | (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \ |
| marcozecchini | 0:9fca2b23d0ba | 512 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 513 | |
| marcozecchini | 0:9fca2b23d0ba | 514 | /** |
| marcozecchini | 0:9fca2b23d0ba | 515 | * @details Get mode bits data for continuous read mode |
| marcozecchini | 0:9fca2b23d0ba | 516 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 517 | */ |
| marcozecchini | 0:9fca2b23d0ba | 518 | #define SPIM_GET_DMMCTL_CRMDAT() \ |
| marcozecchini | 0:9fca2b23d0ba | 519 | ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 520 | |
| marcozecchini | 0:9fca2b23d0ba | 521 | /** |
| marcozecchini | 0:9fca2b23d0ba | 522 | * @details Set DMM mode SPI flash deselect time |
| marcozecchini | 0:9fca2b23d0ba | 523 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 524 | */ |
| marcozecchini | 0:9fca2b23d0ba | 525 | #define SPIM_DMM_SET_DESELTIM(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 526 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 527 | SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \ |
| marcozecchini | 0:9fca2b23d0ba | 528 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 529 | |
| marcozecchini | 0:9fca2b23d0ba | 530 | /** |
| marcozecchini | 0:9fca2b23d0ba | 531 | * @details Get current DMM mode SPI flash deselect time setting |
| marcozecchini | 0:9fca2b23d0ba | 532 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 533 | */ |
| marcozecchini | 0:9fca2b23d0ba | 534 | #define SPIM_DMM_GET_DESELTIM() \ |
| marcozecchini | 0:9fca2b23d0ba | 535 | ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos) |
| marcozecchini | 0:9fca2b23d0ba | 536 | |
| marcozecchini | 0:9fca2b23d0ba | 537 | /** |
| marcozecchini | 0:9fca2b23d0ba | 538 | * @details Enable DMM mode burst wrap mode |
| marcozecchini | 0:9fca2b23d0ba | 539 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 540 | */ |
| marcozecchini | 0:9fca2b23d0ba | 541 | #define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 542 | |
| marcozecchini | 0:9fca2b23d0ba | 543 | /** |
| marcozecchini | 0:9fca2b23d0ba | 544 | * @details Disable DMM mode burst wrap mode |
| marcozecchini | 0:9fca2b23d0ba | 545 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 546 | */ |
| marcozecchini | 0:9fca2b23d0ba | 547 | #define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 548 | |
| marcozecchini | 0:9fca2b23d0ba | 549 | /** |
| marcozecchini | 0:9fca2b23d0ba | 550 | * @details Enable DMM mode continuous read mode |
| marcozecchini | 0:9fca2b23d0ba | 551 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 552 | */ |
| marcozecchini | 0:9fca2b23d0ba | 553 | #define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 554 | |
| marcozecchini | 0:9fca2b23d0ba | 555 | /** |
| marcozecchini | 0:9fca2b23d0ba | 556 | * @details Disable DMM mode continuous read mode |
| marcozecchini | 0:9fca2b23d0ba | 557 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 558 | */ |
| marcozecchini | 0:9fca2b23d0ba | 559 | #define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 560 | |
| marcozecchini | 0:9fca2b23d0ba | 561 | /** |
| marcozecchini | 0:9fca2b23d0ba | 562 | * @details Set DMM mode SPI flash active SCLK time |
| marcozecchini | 0:9fca2b23d0ba | 563 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 564 | */ |
| marcozecchini | 0:9fca2b23d0ba | 565 | #define SPIM_DMM_SET_ACTSCLKT(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 566 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 567 | SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \ |
| marcozecchini | 0:9fca2b23d0ba | 568 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 569 | |
| marcozecchini | 0:9fca2b23d0ba | 570 | /** |
| marcozecchini | 0:9fca2b23d0ba | 571 | * @details Set SPI flash active SCLK time as SPIM default |
| marcozecchini | 0:9fca2b23d0ba | 572 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 573 | */ |
| marcozecchini | 0:9fca2b23d0ba | 574 | #define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 575 | |
| marcozecchini | 0:9fca2b23d0ba | 576 | /** |
| marcozecchini | 0:9fca2b23d0ba | 577 | * @details Set dummy cycle number (Only for DMM mode and DMA mode) |
| marcozecchini | 0:9fca2b23d0ba | 578 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 579 | */ |
| marcozecchini | 0:9fca2b23d0ba | 580 | #define SPIM_SET_DCNUM(x) \ |
| marcozecchini | 0:9fca2b23d0ba | 581 | do { \ |
| marcozecchini | 0:9fca2b23d0ba | 582 | SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \ |
| marcozecchini | 0:9fca2b23d0ba | 583 | } while (0) |
| marcozecchini | 0:9fca2b23d0ba | 584 | |
| marcozecchini | 0:9fca2b23d0ba | 585 | /** |
| marcozecchini | 0:9fca2b23d0ba | 586 | * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default |
| marcozecchini | 0:9fca2b23d0ba | 587 | * \hideinitializer |
| marcozecchini | 0:9fca2b23d0ba | 588 | */ |
| marcozecchini | 0:9fca2b23d0ba | 589 | #define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk) |
| marcozecchini | 0:9fca2b23d0ba | 590 | |
| marcozecchini | 0:9fca2b23d0ba | 591 | |
| marcozecchini | 0:9fca2b23d0ba | 592 | |
| marcozecchini | 0:9fca2b23d0ba | 593 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 594 | /* Define Function Prototypes */ |
| marcozecchini | 0:9fca2b23d0ba | 595 | /*---------------------------------------------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 596 | |
| marcozecchini | 0:9fca2b23d0ba | 597 | |
| marcozecchini | 0:9fca2b23d0ba | 598 | int SPIM_InitFlash(int clrWP); |
| marcozecchini | 0:9fca2b23d0ba | 599 | uint32_t SPIM_GetSClkFreq(void); |
| marcozecchini | 0:9fca2b23d0ba | 600 | void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit); |
| marcozecchini | 0:9fca2b23d0ba | 601 | int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit); |
| marcozecchini | 0:9fca2b23d0ba | 602 | int SPIM_Is4ByteModeEnable(uint32_t u32NBit); |
| marcozecchini | 0:9fca2b23d0ba | 603 | |
| marcozecchini | 0:9fca2b23d0ba | 604 | void SPIM_ChipErase(uint32_t u32NBit, int isSync); |
| marcozecchini | 0:9fca2b23d0ba | 605 | void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync); |
| marcozecchini | 0:9fca2b23d0ba | 606 | |
| marcozecchini | 0:9fca2b23d0ba | 607 | void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat); |
| marcozecchini | 0:9fca2b23d0ba | 608 | void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy); |
| marcozecchini | 0:9fca2b23d0ba | 609 | |
| marcozecchini | 0:9fca2b23d0ba | 610 | void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd); |
| marcozecchini | 0:9fca2b23d0ba | 611 | void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync); |
| marcozecchini | 0:9fca2b23d0ba | 612 | |
| marcozecchini | 0:9fca2b23d0ba | 613 | void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl); |
| marcozecchini | 0:9fca2b23d0ba | 614 | void SPIM_ExitDirectMapMode(void); |
| marcozecchini | 0:9fca2b23d0ba | 615 | |
| marcozecchini | 0:9fca2b23d0ba | 616 | void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit); |
| marcozecchini | 0:9fca2b23d0ba | 617 | |
| marcozecchini | 0:9fca2b23d0ba | 618 | /*@}*/ /* end of group M480_SPIM_EXPORTED_FUNCTIONS */ |
| marcozecchini | 0:9fca2b23d0ba | 619 | |
| marcozecchini | 0:9fca2b23d0ba | 620 | /*@}*/ /* end of group M480_SPIM_Driver */ |
| marcozecchini | 0:9fca2b23d0ba | 621 | |
| marcozecchini | 0:9fca2b23d0ba | 622 | /*@}*/ /* end of group M480_Device_Driver */ |
| marcozecchini | 0:9fca2b23d0ba | 623 | |
| marcozecchini | 0:9fca2b23d0ba | 624 | #ifdef __cplusplus |
| marcozecchini | 0:9fca2b23d0ba | 625 | } |
| marcozecchini | 0:9fca2b23d0ba | 626 | #endif |
| marcozecchini | 0:9fca2b23d0ba | 627 | |
| marcozecchini | 0:9fca2b23d0ba | 628 | #endif /* __SPIM_H__ */ |
| marcozecchini | 0:9fca2b23d0ba | 629 | |
| marcozecchini | 0:9fca2b23d0ba | 630 | /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ |