Marco Zecchini
/
Example_RTOS
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mbed-os/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_adc.c@0:9fca2b23d0ba, 2019-02-23 (annotated)
- Committer:
- marcozecchini
- Date:
- Sat Feb 23 12:13:36 2019 +0000
- Revision:
- 0:9fca2b23d0ba
final commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| marcozecchini | 0:9fca2b23d0ba | 1 | /** |
| marcozecchini | 0:9fca2b23d0ba | 2 | ****************************************************************************** |
| marcozecchini | 0:9fca2b23d0ba | 3 | * @file stm32l4xx_ll_adc.c |
| marcozecchini | 0:9fca2b23d0ba | 4 | * @author MCD Application Team |
| marcozecchini | 0:9fca2b23d0ba | 5 | * @version V1.7.1 |
| marcozecchini | 0:9fca2b23d0ba | 6 | * @date 21-April-2017 |
| marcozecchini | 0:9fca2b23d0ba | 7 | * @brief ADC LL module driver |
| marcozecchini | 0:9fca2b23d0ba | 8 | ****************************************************************************** |
| marcozecchini | 0:9fca2b23d0ba | 9 | * @attention |
| marcozecchini | 0:9fca2b23d0ba | 10 | * |
| marcozecchini | 0:9fca2b23d0ba | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| marcozecchini | 0:9fca2b23d0ba | 12 | * |
| marcozecchini | 0:9fca2b23d0ba | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| marcozecchini | 0:9fca2b23d0ba | 14 | * are permitted provided that the following conditions are met: |
| marcozecchini | 0:9fca2b23d0ba | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| marcozecchini | 0:9fca2b23d0ba | 16 | * this list of conditions and the following disclaimer. |
| marcozecchini | 0:9fca2b23d0ba | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| marcozecchini | 0:9fca2b23d0ba | 18 | * this list of conditions and the following disclaimer in the documentation |
| marcozecchini | 0:9fca2b23d0ba | 19 | * and/or other materials provided with the distribution. |
| marcozecchini | 0:9fca2b23d0ba | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| marcozecchini | 0:9fca2b23d0ba | 21 | * may be used to endorse or promote products derived from this software |
| marcozecchini | 0:9fca2b23d0ba | 22 | * without specific prior written permission. |
| marcozecchini | 0:9fca2b23d0ba | 23 | * |
| marcozecchini | 0:9fca2b23d0ba | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| marcozecchini | 0:9fca2b23d0ba | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| marcozecchini | 0:9fca2b23d0ba | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| marcozecchini | 0:9fca2b23d0ba | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| marcozecchini | 0:9fca2b23d0ba | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| marcozecchini | 0:9fca2b23d0ba | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| marcozecchini | 0:9fca2b23d0ba | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| marcozecchini | 0:9fca2b23d0ba | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| marcozecchini | 0:9fca2b23d0ba | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| marcozecchini | 0:9fca2b23d0ba | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| marcozecchini | 0:9fca2b23d0ba | 34 | * |
| marcozecchini | 0:9fca2b23d0ba | 35 | ****************************************************************************** |
| marcozecchini | 0:9fca2b23d0ba | 36 | */ |
| marcozecchini | 0:9fca2b23d0ba | 37 | #if defined(USE_FULL_LL_DRIVER) |
| marcozecchini | 0:9fca2b23d0ba | 38 | |
| marcozecchini | 0:9fca2b23d0ba | 39 | /* Includes ------------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 40 | #include "stm32l4xx_ll_adc.h" |
| marcozecchini | 0:9fca2b23d0ba | 41 | #include "stm32l4xx_ll_bus.h" |
| marcozecchini | 0:9fca2b23d0ba | 42 | |
| marcozecchini | 0:9fca2b23d0ba | 43 | #ifdef USE_FULL_ASSERT |
| marcozecchini | 0:9fca2b23d0ba | 44 | #include "stm32_assert.h" |
| marcozecchini | 0:9fca2b23d0ba | 45 | #else |
| marcozecchini | 0:9fca2b23d0ba | 46 | #define assert_param(expr) ((void)0U) |
| marcozecchini | 0:9fca2b23d0ba | 47 | #endif |
| marcozecchini | 0:9fca2b23d0ba | 48 | |
| marcozecchini | 0:9fca2b23d0ba | 49 | /** @addtogroup STM32L4xx_LL_Driver |
| marcozecchini | 0:9fca2b23d0ba | 50 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 51 | */ |
| marcozecchini | 0:9fca2b23d0ba | 52 | |
| marcozecchini | 0:9fca2b23d0ba | 53 | #if defined (ADC1) || defined (ADC2) || defined (ADC3) |
| marcozecchini | 0:9fca2b23d0ba | 54 | |
| marcozecchini | 0:9fca2b23d0ba | 55 | /** @addtogroup ADC_LL ADC |
| marcozecchini | 0:9fca2b23d0ba | 56 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 57 | */ |
| marcozecchini | 0:9fca2b23d0ba | 58 | |
| marcozecchini | 0:9fca2b23d0ba | 59 | /* Private types -------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 60 | /* Private variables ---------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 61 | /* Private constants ---------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 62 | /** @addtogroup ADC_LL_Private_Constants |
| marcozecchini | 0:9fca2b23d0ba | 63 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 64 | */ |
| marcozecchini | 0:9fca2b23d0ba | 65 | |
| marcozecchini | 0:9fca2b23d0ba | 66 | /* Definitions of ADC hardware constraints delays */ |
| marcozecchini | 0:9fca2b23d0ba | 67 | /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ |
| marcozecchini | 0:9fca2b23d0ba | 68 | /* not timeout values: */ |
| marcozecchini | 0:9fca2b23d0ba | 69 | /* Timeout values for ADC operations are dependent to device clock */ |
| marcozecchini | 0:9fca2b23d0ba | 70 | /* configuration (system clock versus ADC clock), */ |
| marcozecchini | 0:9fca2b23d0ba | 71 | /* and therefore must be defined in user application. */ |
| marcozecchini | 0:9fca2b23d0ba | 72 | /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ |
| marcozecchini | 0:9fca2b23d0ba | 73 | /* values definition. */ |
| marcozecchini | 0:9fca2b23d0ba | 74 | /* Note: ADC timeout values are defined here in CPU cycles to be independent */ |
| marcozecchini | 0:9fca2b23d0ba | 75 | /* of device clock setting. */ |
| marcozecchini | 0:9fca2b23d0ba | 76 | /* In user application, ADC timeout values should be defined with */ |
| marcozecchini | 0:9fca2b23d0ba | 77 | /* temporal values, in function of device clock settings. */ |
| marcozecchini | 0:9fca2b23d0ba | 78 | /* Highest ratio CPU clock frequency vs ADC clock frequency: */ |
| marcozecchini | 0:9fca2b23d0ba | 79 | /* - ADC clock from synchronous clock with AHB prescaler 512, */ |
| marcozecchini | 0:9fca2b23d0ba | 80 | /* APB prescaler 16, ADC prescaler 4. */ |
| marcozecchini | 0:9fca2b23d0ba | 81 | /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */ |
| marcozecchini | 0:9fca2b23d0ba | 82 | /* with highest ratio CPU clock frequency vs HSI clock frequency: */ |
| marcozecchini | 0:9fca2b23d0ba | 83 | /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */ |
| marcozecchini | 0:9fca2b23d0ba | 84 | /* Unit: CPU cycles. */ |
| marcozecchini | 0:9fca2b23d0ba | 85 | #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) |
| marcozecchini | 0:9fca2b23d0ba | 86 | #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) |
| marcozecchini | 0:9fca2b23d0ba | 87 | #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) |
| marcozecchini | 0:9fca2b23d0ba | 88 | |
| marcozecchini | 0:9fca2b23d0ba | 89 | /** |
| marcozecchini | 0:9fca2b23d0ba | 90 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 91 | */ |
| marcozecchini | 0:9fca2b23d0ba | 92 | |
| marcozecchini | 0:9fca2b23d0ba | 93 | /* Private macros ------------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 94 | |
| marcozecchini | 0:9fca2b23d0ba | 95 | /** @addtogroup ADC_LL_Private_Macros |
| marcozecchini | 0:9fca2b23d0ba | 96 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 97 | */ |
| marcozecchini | 0:9fca2b23d0ba | 98 | |
| marcozecchini | 0:9fca2b23d0ba | 99 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 100 | /* common to several ADC instances. */ |
| marcozecchini | 0:9fca2b23d0ba | 101 | #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
| marcozecchini | 0:9fca2b23d0ba | 102 | ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ |
| marcozecchini | 0:9fca2b23d0ba | 103 | || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ |
| marcozecchini | 0:9fca2b23d0ba | 104 | || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ |
| marcozecchini | 0:9fca2b23d0ba | 105 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ |
| marcozecchini | 0:9fca2b23d0ba | 106 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ |
| marcozecchini | 0:9fca2b23d0ba | 107 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ |
| marcozecchini | 0:9fca2b23d0ba | 108 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ |
| marcozecchini | 0:9fca2b23d0ba | 109 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ |
| marcozecchini | 0:9fca2b23d0ba | 110 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ |
| marcozecchini | 0:9fca2b23d0ba | 111 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ |
| marcozecchini | 0:9fca2b23d0ba | 112 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ |
| marcozecchini | 0:9fca2b23d0ba | 113 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ |
| marcozecchini | 0:9fca2b23d0ba | 114 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ |
| marcozecchini | 0:9fca2b23d0ba | 115 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ |
| marcozecchini | 0:9fca2b23d0ba | 116 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ |
| marcozecchini | 0:9fca2b23d0ba | 117 | ) |
| marcozecchini | 0:9fca2b23d0ba | 118 | |
| marcozecchini | 0:9fca2b23d0ba | 119 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 120 | /* ADC instance. */ |
| marcozecchini | 0:9fca2b23d0ba | 121 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
| marcozecchini | 0:9fca2b23d0ba | 122 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
| marcozecchini | 0:9fca2b23d0ba | 123 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
| marcozecchini | 0:9fca2b23d0ba | 124 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
| marcozecchini | 0:9fca2b23d0ba | 125 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
| marcozecchini | 0:9fca2b23d0ba | 126 | ) |
| marcozecchini | 0:9fca2b23d0ba | 127 | |
| marcozecchini | 0:9fca2b23d0ba | 128 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
| marcozecchini | 0:9fca2b23d0ba | 129 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
| marcozecchini | 0:9fca2b23d0ba | 130 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
| marcozecchini | 0:9fca2b23d0ba | 131 | ) |
| marcozecchini | 0:9fca2b23d0ba | 132 | |
| marcozecchini | 0:9fca2b23d0ba | 133 | #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ |
| marcozecchini | 0:9fca2b23d0ba | 134 | ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ |
| marcozecchini | 0:9fca2b23d0ba | 135 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ |
| marcozecchini | 0:9fca2b23d0ba | 136 | ) |
| marcozecchini | 0:9fca2b23d0ba | 137 | |
| marcozecchini | 0:9fca2b23d0ba | 138 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 139 | /* ADC group regular */ |
| marcozecchini | 0:9fca2b23d0ba | 140 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 141 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
| marcozecchini | 0:9fca2b23d0ba | 142 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 143 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ |
| marcozecchini | 0:9fca2b23d0ba | 144 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
| marcozecchini | 0:9fca2b23d0ba | 145 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
| marcozecchini | 0:9fca2b23d0ba | 146 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
| marcozecchini | 0:9fca2b23d0ba | 147 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 148 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
| marcozecchini | 0:9fca2b23d0ba | 149 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 150 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ |
| marcozecchini | 0:9fca2b23d0ba | 151 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 152 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
| marcozecchini | 0:9fca2b23d0ba | 153 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 154 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 155 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ |
| marcozecchini | 0:9fca2b23d0ba | 156 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 157 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
| marcozecchini | 0:9fca2b23d0ba | 158 | ) |
| marcozecchini | 0:9fca2b23d0ba | 159 | |
| marcozecchini | 0:9fca2b23d0ba | 160 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 161 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
| marcozecchini | 0:9fca2b23d0ba | 162 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
| marcozecchini | 0:9fca2b23d0ba | 163 | ) |
| marcozecchini | 0:9fca2b23d0ba | 164 | |
| marcozecchini | 0:9fca2b23d0ba | 165 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
| marcozecchini | 0:9fca2b23d0ba | 166 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
| marcozecchini | 0:9fca2b23d0ba | 167 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
| marcozecchini | 0:9fca2b23d0ba | 168 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
| marcozecchini | 0:9fca2b23d0ba | 169 | ) |
| marcozecchini | 0:9fca2b23d0ba | 170 | |
| marcozecchini | 0:9fca2b23d0ba | 171 | #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ |
| marcozecchini | 0:9fca2b23d0ba | 172 | ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ |
| marcozecchini | 0:9fca2b23d0ba | 173 | || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ |
| marcozecchini | 0:9fca2b23d0ba | 174 | ) |
| marcozecchini | 0:9fca2b23d0ba | 175 | |
| marcozecchini | 0:9fca2b23d0ba | 176 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
| marcozecchini | 0:9fca2b23d0ba | 177 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
| marcozecchini | 0:9fca2b23d0ba | 178 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 179 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 180 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 181 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 182 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 183 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 184 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 185 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 186 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 187 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 188 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 189 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 190 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 191 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 192 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 193 | ) |
| marcozecchini | 0:9fca2b23d0ba | 194 | |
| marcozecchini | 0:9fca2b23d0ba | 195 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 196 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
| marcozecchini | 0:9fca2b23d0ba | 197 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
| marcozecchini | 0:9fca2b23d0ba | 198 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 199 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 200 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 201 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 202 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 203 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 204 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 205 | ) |
| marcozecchini | 0:9fca2b23d0ba | 206 | |
| marcozecchini | 0:9fca2b23d0ba | 207 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 208 | /* ADC group injected */ |
| marcozecchini | 0:9fca2b23d0ba | 209 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 210 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
| marcozecchini | 0:9fca2b23d0ba | 211 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 212 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ |
| marcozecchini | 0:9fca2b23d0ba | 213 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
| marcozecchini | 0:9fca2b23d0ba | 214 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 215 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
| marcozecchini | 0:9fca2b23d0ba | 216 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 217 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ |
| marcozecchini | 0:9fca2b23d0ba | 218 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ |
| marcozecchini | 0:9fca2b23d0ba | 219 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
| marcozecchini | 0:9fca2b23d0ba | 220 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 221 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 222 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
| marcozecchini | 0:9fca2b23d0ba | 223 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 224 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ |
| marcozecchini | 0:9fca2b23d0ba | 225 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ |
| marcozecchini | 0:9fca2b23d0ba | 226 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
| marcozecchini | 0:9fca2b23d0ba | 227 | ) |
| marcozecchini | 0:9fca2b23d0ba | 228 | |
| marcozecchini | 0:9fca2b23d0ba | 229 | #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 230 | ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
| marcozecchini | 0:9fca2b23d0ba | 231 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
| marcozecchini | 0:9fca2b23d0ba | 232 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
| marcozecchini | 0:9fca2b23d0ba | 233 | ) |
| marcozecchini | 0:9fca2b23d0ba | 234 | |
| marcozecchini | 0:9fca2b23d0ba | 235 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
| marcozecchini | 0:9fca2b23d0ba | 236 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
| marcozecchini | 0:9fca2b23d0ba | 237 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
| marcozecchini | 0:9fca2b23d0ba | 238 | ) |
| marcozecchini | 0:9fca2b23d0ba | 239 | |
| marcozecchini | 0:9fca2b23d0ba | 240 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
| marcozecchini | 0:9fca2b23d0ba | 241 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
| marcozecchini | 0:9fca2b23d0ba | 242 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 243 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 244 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
| marcozecchini | 0:9fca2b23d0ba | 245 | ) |
| marcozecchini | 0:9fca2b23d0ba | 246 | |
| marcozecchini | 0:9fca2b23d0ba | 247 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 248 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
| marcozecchini | 0:9fca2b23d0ba | 249 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
| marcozecchini | 0:9fca2b23d0ba | 250 | ) |
| marcozecchini | 0:9fca2b23d0ba | 251 | |
| marcozecchini | 0:9fca2b23d0ba | 252 | #if defined(ADC_MULTIMODE_SUPPORT) |
| marcozecchini | 0:9fca2b23d0ba | 253 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 254 | /* multimode. */ |
| marcozecchini | 0:9fca2b23d0ba | 255 | #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 256 | ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
| marcozecchini | 0:9fca2b23d0ba | 257 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
| marcozecchini | 0:9fca2b23d0ba | 258 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ |
| marcozecchini | 0:9fca2b23d0ba | 259 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
| marcozecchini | 0:9fca2b23d0ba | 260 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
| marcozecchini | 0:9fca2b23d0ba | 261 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
| marcozecchini | 0:9fca2b23d0ba | 262 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
| marcozecchini | 0:9fca2b23d0ba | 263 | || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ |
| marcozecchini | 0:9fca2b23d0ba | 264 | ) |
| marcozecchini | 0:9fca2b23d0ba | 265 | |
| marcozecchini | 0:9fca2b23d0ba | 266 | #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ |
| marcozecchini | 0:9fca2b23d0ba | 267 | ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ |
| marcozecchini | 0:9fca2b23d0ba | 268 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ |
| marcozecchini | 0:9fca2b23d0ba | 269 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ |
| marcozecchini | 0:9fca2b23d0ba | 270 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ |
| marcozecchini | 0:9fca2b23d0ba | 271 | || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \ |
| marcozecchini | 0:9fca2b23d0ba | 272 | ) |
| marcozecchini | 0:9fca2b23d0ba | 273 | |
| marcozecchini | 0:9fca2b23d0ba | 274 | #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ |
| marcozecchini | 0:9fca2b23d0ba | 275 | ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ |
| marcozecchini | 0:9fca2b23d0ba | 276 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 277 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 278 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 279 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 280 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 281 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 282 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 283 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 284 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 285 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 286 | || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ |
| marcozecchini | 0:9fca2b23d0ba | 287 | ) |
| marcozecchini | 0:9fca2b23d0ba | 288 | |
| marcozecchini | 0:9fca2b23d0ba | 289 | #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ |
| marcozecchini | 0:9fca2b23d0ba | 290 | ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ |
| marcozecchini | 0:9fca2b23d0ba | 291 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ |
| marcozecchini | 0:9fca2b23d0ba | 292 | || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ |
| marcozecchini | 0:9fca2b23d0ba | 293 | ) |
| marcozecchini | 0:9fca2b23d0ba | 294 | |
| marcozecchini | 0:9fca2b23d0ba | 295 | #endif /* ADC_MULTIMODE_SUPPORT */ |
| marcozecchini | 0:9fca2b23d0ba | 296 | /** |
| marcozecchini | 0:9fca2b23d0ba | 297 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 298 | */ |
| marcozecchini | 0:9fca2b23d0ba | 299 | |
| marcozecchini | 0:9fca2b23d0ba | 300 | |
| marcozecchini | 0:9fca2b23d0ba | 301 | /* Private function prototypes -----------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 302 | |
| marcozecchini | 0:9fca2b23d0ba | 303 | /* Exported functions --------------------------------------------------------*/ |
| marcozecchini | 0:9fca2b23d0ba | 304 | /** @addtogroup ADC_LL_Exported_Functions |
| marcozecchini | 0:9fca2b23d0ba | 305 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 306 | */ |
| marcozecchini | 0:9fca2b23d0ba | 307 | |
| marcozecchini | 0:9fca2b23d0ba | 308 | /** @addtogroup ADC_LL_EF_Init |
| marcozecchini | 0:9fca2b23d0ba | 309 | * @{ |
| marcozecchini | 0:9fca2b23d0ba | 310 | */ |
| marcozecchini | 0:9fca2b23d0ba | 311 | |
| marcozecchini | 0:9fca2b23d0ba | 312 | /** |
| marcozecchini | 0:9fca2b23d0ba | 313 | * @brief De-initialize registers of all ADC instances belonging to |
| marcozecchini | 0:9fca2b23d0ba | 314 | * the same ADC common instance to their default reset values. |
| marcozecchini | 0:9fca2b23d0ba | 315 | * @note This function is performing a hard reset, using high level |
| marcozecchini | 0:9fca2b23d0ba | 316 | * clock source RCC ADC reset. |
| marcozecchini | 0:9fca2b23d0ba | 317 | * Caution: On this STM32 serie, if several ADC instances are available |
| marcozecchini | 0:9fca2b23d0ba | 318 | * on the selected device, RCC ADC reset will reset |
| marcozecchini | 0:9fca2b23d0ba | 319 | * all ADC instances belonging to the common ADC instance. |
| marcozecchini | 0:9fca2b23d0ba | 320 | * To de-initialize only 1 ADC instance, use |
| marcozecchini | 0:9fca2b23d0ba | 321 | * function @ref LL_ADC_DeInit(). |
| marcozecchini | 0:9fca2b23d0ba | 322 | * @param ADCxy_COMMON ADC common instance |
| marcozecchini | 0:9fca2b23d0ba | 323 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| marcozecchini | 0:9fca2b23d0ba | 324 | * @retval An ErrorStatus enumeration value: |
| marcozecchini | 0:9fca2b23d0ba | 325 | * - SUCCESS: ADC common registers are de-initialized |
| marcozecchini | 0:9fca2b23d0ba | 326 | * - ERROR: not applicable |
| marcozecchini | 0:9fca2b23d0ba | 327 | */ |
| marcozecchini | 0:9fca2b23d0ba | 328 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
| marcozecchini | 0:9fca2b23d0ba | 329 | { |
| marcozecchini | 0:9fca2b23d0ba | 330 | /* Check the parameters */ |
| marcozecchini | 0:9fca2b23d0ba | 331 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| marcozecchini | 0:9fca2b23d0ba | 332 | |
| marcozecchini | 0:9fca2b23d0ba | 333 | /* Force reset of ADC clock (core clock) */ |
| marcozecchini | 0:9fca2b23d0ba | 334 | LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC); |
| marcozecchini | 0:9fca2b23d0ba | 335 | |
| marcozecchini | 0:9fca2b23d0ba | 336 | /* Release reset of ADC clock (core clock) */ |
| marcozecchini | 0:9fca2b23d0ba | 337 | LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC); |
| marcozecchini | 0:9fca2b23d0ba | 338 | |
| marcozecchini | 0:9fca2b23d0ba | 339 | return SUCCESS; |
| marcozecchini | 0:9fca2b23d0ba | 340 | } |
| marcozecchini | 0:9fca2b23d0ba | 341 | |
| marcozecchini | 0:9fca2b23d0ba | 342 | /** |
| marcozecchini | 0:9fca2b23d0ba | 343 | * @brief Initialize some features of ADC common parameters |
| marcozecchini | 0:9fca2b23d0ba | 344 | * (all ADC instances belonging to the same ADC common instance) |
| marcozecchini | 0:9fca2b23d0ba | 345 | * and multimode (for devices with several ADC instances available). |
| marcozecchini | 0:9fca2b23d0ba | 346 | * @note The setting of ADC common parameters is conditioned to |
| marcozecchini | 0:9fca2b23d0ba | 347 | * ADC instances state: |
| marcozecchini | 0:9fca2b23d0ba | 348 | * All ADC instances belonging to the same ADC common instance |
| marcozecchini | 0:9fca2b23d0ba | 349 | * must be disabled. |
| marcozecchini | 0:9fca2b23d0ba | 350 | * @param ADCxy_COMMON ADC common instance |
| marcozecchini | 0:9fca2b23d0ba | 351 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| marcozecchini | 0:9fca2b23d0ba | 352 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 353 | * @retval An ErrorStatus enumeration value: |
| marcozecchini | 0:9fca2b23d0ba | 354 | * - SUCCESS: ADC common registers are initialized |
| marcozecchini | 0:9fca2b23d0ba | 355 | * - ERROR: ADC common registers are not initialized |
| marcozecchini | 0:9fca2b23d0ba | 356 | */ |
| marcozecchini | 0:9fca2b23d0ba | 357 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 358 | { |
| marcozecchini | 0:9fca2b23d0ba | 359 | ErrorStatus status = SUCCESS; |
| marcozecchini | 0:9fca2b23d0ba | 360 | |
| marcozecchini | 0:9fca2b23d0ba | 361 | /* Check the parameters */ |
| marcozecchini | 0:9fca2b23d0ba | 362 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| marcozecchini | 0:9fca2b23d0ba | 363 | assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
| marcozecchini | 0:9fca2b23d0ba | 364 | |
| marcozecchini | 0:9fca2b23d0ba | 365 | #if defined(ADC_MULTIMODE_SUPPORT) |
| marcozecchini | 0:9fca2b23d0ba | 366 | assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); |
| marcozecchini | 0:9fca2b23d0ba | 367 | if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
| marcozecchini | 0:9fca2b23d0ba | 368 | { |
| marcozecchini | 0:9fca2b23d0ba | 369 | assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); |
| marcozecchini | 0:9fca2b23d0ba | 370 | assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); |
| marcozecchini | 0:9fca2b23d0ba | 371 | } |
| marcozecchini | 0:9fca2b23d0ba | 372 | #endif /* ADC_MULTIMODE_SUPPORT */ |
| marcozecchini | 0:9fca2b23d0ba | 373 | |
| marcozecchini | 0:9fca2b23d0ba | 374 | /* Note: Hardware constraint (refer to description of functions */ |
| marcozecchini | 0:9fca2b23d0ba | 375 | /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ |
| marcozecchini | 0:9fca2b23d0ba | 376 | /* On this STM32 serie, setting of these features is conditioned to */ |
| marcozecchini | 0:9fca2b23d0ba | 377 | /* ADC state: */ |
| marcozecchini | 0:9fca2b23d0ba | 378 | /* All ADC instances of the ADC common group must be disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 379 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 380 | { |
| marcozecchini | 0:9fca2b23d0ba | 381 | /* Configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 382 | /* - common to several ADC */ |
| marcozecchini | 0:9fca2b23d0ba | 383 | /* (all ADC instances belonging to the same ADC common instance) */ |
| marcozecchini | 0:9fca2b23d0ba | 384 | /* - Set ADC clock (conversion clock) */ |
| marcozecchini | 0:9fca2b23d0ba | 385 | /* - multimode (if several ADC instances available on the */ |
| marcozecchini | 0:9fca2b23d0ba | 386 | /* selected device) */ |
| marcozecchini | 0:9fca2b23d0ba | 387 | /* - Set ADC multimode configuration */ |
| marcozecchini | 0:9fca2b23d0ba | 388 | /* - Set ADC multimode DMA transfer */ |
| marcozecchini | 0:9fca2b23d0ba | 389 | /* - Set ADC multimode: delay between 2 sampling phases */ |
| marcozecchini | 0:9fca2b23d0ba | 390 | #if defined(ADC_MULTIMODE_SUPPORT) |
| marcozecchini | 0:9fca2b23d0ba | 391 | if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
| marcozecchini | 0:9fca2b23d0ba | 392 | { |
| marcozecchini | 0:9fca2b23d0ba | 393 | MODIFY_REG(ADCxy_COMMON->CCR, |
| marcozecchini | 0:9fca2b23d0ba | 394 | ADC_CCR_CKMODE |
| marcozecchini | 0:9fca2b23d0ba | 395 | | ADC_CCR_PRESC |
| marcozecchini | 0:9fca2b23d0ba | 396 | | ADC_CCR_DUAL |
| marcozecchini | 0:9fca2b23d0ba | 397 | | ADC_CCR_MDMA |
| marcozecchini | 0:9fca2b23d0ba | 398 | | ADC_CCR_DELAY |
| marcozecchini | 0:9fca2b23d0ba | 399 | , |
| marcozecchini | 0:9fca2b23d0ba | 400 | ADC_CommonInitStruct->CommonClock |
| marcozecchini | 0:9fca2b23d0ba | 401 | | ADC_CommonInitStruct->Multimode |
| marcozecchini | 0:9fca2b23d0ba | 402 | | ADC_CommonInitStruct->MultiDMATransfer |
| marcozecchini | 0:9fca2b23d0ba | 403 | | ADC_CommonInitStruct->MultiTwoSamplingDelay |
| marcozecchini | 0:9fca2b23d0ba | 404 | ); |
| marcozecchini | 0:9fca2b23d0ba | 405 | } |
| marcozecchini | 0:9fca2b23d0ba | 406 | else |
| marcozecchini | 0:9fca2b23d0ba | 407 | { |
| marcozecchini | 0:9fca2b23d0ba | 408 | MODIFY_REG(ADCxy_COMMON->CCR, |
| marcozecchini | 0:9fca2b23d0ba | 409 | ADC_CCR_CKMODE |
| marcozecchini | 0:9fca2b23d0ba | 410 | | ADC_CCR_PRESC |
| marcozecchini | 0:9fca2b23d0ba | 411 | | ADC_CCR_DUAL |
| marcozecchini | 0:9fca2b23d0ba | 412 | | ADC_CCR_MDMA |
| marcozecchini | 0:9fca2b23d0ba | 413 | | ADC_CCR_DELAY |
| marcozecchini | 0:9fca2b23d0ba | 414 | , |
| marcozecchini | 0:9fca2b23d0ba | 415 | ADC_CommonInitStruct->CommonClock |
| marcozecchini | 0:9fca2b23d0ba | 416 | | LL_ADC_MULTI_INDEPENDENT |
| marcozecchini | 0:9fca2b23d0ba | 417 | ); |
| marcozecchini | 0:9fca2b23d0ba | 418 | } |
| marcozecchini | 0:9fca2b23d0ba | 419 | #else |
| marcozecchini | 0:9fca2b23d0ba | 420 | LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
| marcozecchini | 0:9fca2b23d0ba | 421 | #endif |
| marcozecchini | 0:9fca2b23d0ba | 422 | } |
| marcozecchini | 0:9fca2b23d0ba | 423 | else |
| marcozecchini | 0:9fca2b23d0ba | 424 | { |
| marcozecchini | 0:9fca2b23d0ba | 425 | /* Initialization error: One or several ADC instances belonging to */ |
| marcozecchini | 0:9fca2b23d0ba | 426 | /* the same ADC common instance are not disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 427 | status = ERROR; |
| marcozecchini | 0:9fca2b23d0ba | 428 | } |
| marcozecchini | 0:9fca2b23d0ba | 429 | |
| marcozecchini | 0:9fca2b23d0ba | 430 | return status; |
| marcozecchini | 0:9fca2b23d0ba | 431 | } |
| marcozecchini | 0:9fca2b23d0ba | 432 | |
| marcozecchini | 0:9fca2b23d0ba | 433 | /** |
| marcozecchini | 0:9fca2b23d0ba | 434 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
| marcozecchini | 0:9fca2b23d0ba | 435 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 436 | * whose fields will be set to default values. |
| marcozecchini | 0:9fca2b23d0ba | 437 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 438 | */ |
| marcozecchini | 0:9fca2b23d0ba | 439 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 440 | { |
| marcozecchini | 0:9fca2b23d0ba | 441 | /* Set ADC_CommonInitStruct fields to default values */ |
| marcozecchini | 0:9fca2b23d0ba | 442 | /* Set fields of ADC common */ |
| marcozecchini | 0:9fca2b23d0ba | 443 | /* (all ADC instances belonging to the same ADC common instance) */ |
| marcozecchini | 0:9fca2b23d0ba | 444 | ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; |
| marcozecchini | 0:9fca2b23d0ba | 445 | |
| marcozecchini | 0:9fca2b23d0ba | 446 | #if defined(ADC_MULTIMODE_SUPPORT) |
| marcozecchini | 0:9fca2b23d0ba | 447 | /* Set fields of ADC multimode */ |
| marcozecchini | 0:9fca2b23d0ba | 448 | ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; |
| marcozecchini | 0:9fca2b23d0ba | 449 | ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; |
| marcozecchini | 0:9fca2b23d0ba | 450 | ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; |
| marcozecchini | 0:9fca2b23d0ba | 451 | #endif /* ADC_MULTIMODE_SUPPORT */ |
| marcozecchini | 0:9fca2b23d0ba | 452 | } |
| marcozecchini | 0:9fca2b23d0ba | 453 | |
| marcozecchini | 0:9fca2b23d0ba | 454 | /** |
| marcozecchini | 0:9fca2b23d0ba | 455 | * @brief De-initialize registers of the selected ADC instance |
| marcozecchini | 0:9fca2b23d0ba | 456 | * to their default reset values. |
| marcozecchini | 0:9fca2b23d0ba | 457 | * @note To reset all ADC instances quickly (perform a hard reset), |
| marcozecchini | 0:9fca2b23d0ba | 458 | * use function @ref LL_ADC_CommonDeInit(). |
| marcozecchini | 0:9fca2b23d0ba | 459 | * @note If this functions returns error status, it means that ADC instance |
| marcozecchini | 0:9fca2b23d0ba | 460 | * is in an unknown state. |
| marcozecchini | 0:9fca2b23d0ba | 461 | * In this case, perform a hard reset using high level |
| marcozecchini | 0:9fca2b23d0ba | 462 | * clock source RCC ADC reset. |
| marcozecchini | 0:9fca2b23d0ba | 463 | * Caution: On this STM32 serie, if several ADC instances are available |
| marcozecchini | 0:9fca2b23d0ba | 464 | * on the selected device, RCC ADC reset will reset |
| marcozecchini | 0:9fca2b23d0ba | 465 | * all ADC instances belonging to the common ADC instance. |
| marcozecchini | 0:9fca2b23d0ba | 466 | * Refer to function @ref LL_ADC_CommonDeInit(). |
| marcozecchini | 0:9fca2b23d0ba | 467 | * @param ADCx ADC instance |
| marcozecchini | 0:9fca2b23d0ba | 468 | * @retval An ErrorStatus enumeration value: |
| marcozecchini | 0:9fca2b23d0ba | 469 | * - SUCCESS: ADC registers are de-initialized |
| marcozecchini | 0:9fca2b23d0ba | 470 | * - ERROR: ADC registers are not de-initialized |
| marcozecchini | 0:9fca2b23d0ba | 471 | */ |
| marcozecchini | 0:9fca2b23d0ba | 472 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
| marcozecchini | 0:9fca2b23d0ba | 473 | { |
| marcozecchini | 0:9fca2b23d0ba | 474 | ErrorStatus status = SUCCESS; |
| marcozecchini | 0:9fca2b23d0ba | 475 | |
| marcozecchini | 0:9fca2b23d0ba | 476 | __IO uint32_t timeout_cpu_cycles = 0U; |
| marcozecchini | 0:9fca2b23d0ba | 477 | |
| marcozecchini | 0:9fca2b23d0ba | 478 | /* Check the parameters */ |
| marcozecchini | 0:9fca2b23d0ba | 479 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| marcozecchini | 0:9fca2b23d0ba | 480 | |
| marcozecchini | 0:9fca2b23d0ba | 481 | /* Disable ADC instance if not already disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 482 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
| marcozecchini | 0:9fca2b23d0ba | 483 | { |
| marcozecchini | 0:9fca2b23d0ba | 484 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
| marcozecchini | 0:9fca2b23d0ba | 485 | /* have an external trigger event occurring during the conversion stop */ |
| marcozecchini | 0:9fca2b23d0ba | 486 | /* ADC disable process. */ |
| marcozecchini | 0:9fca2b23d0ba | 487 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
| marcozecchini | 0:9fca2b23d0ba | 488 | |
| marcozecchini | 0:9fca2b23d0ba | 489 | /* Stop potential ADC conversion on going on ADC group regular. */ |
| marcozecchini | 0:9fca2b23d0ba | 490 | if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) |
| marcozecchini | 0:9fca2b23d0ba | 491 | { |
| marcozecchini | 0:9fca2b23d0ba | 492 | if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 493 | { |
| marcozecchini | 0:9fca2b23d0ba | 494 | LL_ADC_REG_StopConversion(ADCx); |
| marcozecchini | 0:9fca2b23d0ba | 495 | } |
| marcozecchini | 0:9fca2b23d0ba | 496 | } |
| marcozecchini | 0:9fca2b23d0ba | 497 | |
| marcozecchini | 0:9fca2b23d0ba | 498 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
| marcozecchini | 0:9fca2b23d0ba | 499 | /* have an external trigger event occurring during the conversion stop */ |
| marcozecchini | 0:9fca2b23d0ba | 500 | /* ADC disable process. */ |
| marcozecchini | 0:9fca2b23d0ba | 501 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
| marcozecchini | 0:9fca2b23d0ba | 502 | |
| marcozecchini | 0:9fca2b23d0ba | 503 | /* Stop potential ADC conversion on going on ADC group injected. */ |
| marcozecchini | 0:9fca2b23d0ba | 504 | if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U) |
| marcozecchini | 0:9fca2b23d0ba | 505 | { |
| marcozecchini | 0:9fca2b23d0ba | 506 | if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 507 | { |
| marcozecchini | 0:9fca2b23d0ba | 508 | LL_ADC_INJ_StopConversion(ADCx); |
| marcozecchini | 0:9fca2b23d0ba | 509 | } |
| marcozecchini | 0:9fca2b23d0ba | 510 | } |
| marcozecchini | 0:9fca2b23d0ba | 511 | |
| marcozecchini | 0:9fca2b23d0ba | 512 | /* Wait for ADC conversions are effectively stopped */ |
| marcozecchini | 0:9fca2b23d0ba | 513 | timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; |
| marcozecchini | 0:9fca2b23d0ba | 514 | while (( LL_ADC_REG_IsStopConversionOngoing(ADCx) |
| marcozecchini | 0:9fca2b23d0ba | 515 | | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U) |
| marcozecchini | 0:9fca2b23d0ba | 516 | { |
| marcozecchini | 0:9fca2b23d0ba | 517 | if(timeout_cpu_cycles-- == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 518 | { |
| marcozecchini | 0:9fca2b23d0ba | 519 | /* Time-out error */ |
| marcozecchini | 0:9fca2b23d0ba | 520 | status = ERROR; |
| marcozecchini | 0:9fca2b23d0ba | 521 | } |
| marcozecchini | 0:9fca2b23d0ba | 522 | } |
| marcozecchini | 0:9fca2b23d0ba | 523 | |
| marcozecchini | 0:9fca2b23d0ba | 524 | /* Flush group injected contexts queue (register JSQR): */ |
| marcozecchini | 0:9fca2b23d0ba | 525 | /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ |
| marcozecchini | 0:9fca2b23d0ba | 526 | /* contexts queue is maintained with the last active context). */ |
| marcozecchini | 0:9fca2b23d0ba | 527 | LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); |
| marcozecchini | 0:9fca2b23d0ba | 528 | |
| marcozecchini | 0:9fca2b23d0ba | 529 | /* Disable the ADC instance */ |
| marcozecchini | 0:9fca2b23d0ba | 530 | LL_ADC_Disable(ADCx); |
| marcozecchini | 0:9fca2b23d0ba | 531 | |
| marcozecchini | 0:9fca2b23d0ba | 532 | /* Wait for ADC instance is effectively disabled */ |
| marcozecchini | 0:9fca2b23d0ba | 533 | timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; |
| marcozecchini | 0:9fca2b23d0ba | 534 | while (LL_ADC_IsDisableOngoing(ADCx) == 1U) |
| marcozecchini | 0:9fca2b23d0ba | 535 | { |
| marcozecchini | 0:9fca2b23d0ba | 536 | if(timeout_cpu_cycles-- == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 537 | { |
| marcozecchini | 0:9fca2b23d0ba | 538 | /* Time-out error */ |
| marcozecchini | 0:9fca2b23d0ba | 539 | status = ERROR; |
| marcozecchini | 0:9fca2b23d0ba | 540 | } |
| marcozecchini | 0:9fca2b23d0ba | 541 | } |
| marcozecchini | 0:9fca2b23d0ba | 542 | } |
| marcozecchini | 0:9fca2b23d0ba | 543 | |
| marcozecchini | 0:9fca2b23d0ba | 544 | /* Check whether ADC state is compliant with expected state */ |
| marcozecchini | 0:9fca2b23d0ba | 545 | if(READ_BIT(ADCx->CR, |
| marcozecchini | 0:9fca2b23d0ba | 546 | ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART |
| marcozecchini | 0:9fca2b23d0ba | 547 | | ADC_CR_ADDIS | ADC_CR_ADEN ) |
| marcozecchini | 0:9fca2b23d0ba | 548 | ) |
| marcozecchini | 0:9fca2b23d0ba | 549 | == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 550 | { |
| marcozecchini | 0:9fca2b23d0ba | 551 | /* ========== Reset ADC registers ========== */ |
| marcozecchini | 0:9fca2b23d0ba | 552 | /* Reset register IER */ |
| marcozecchini | 0:9fca2b23d0ba | 553 | CLEAR_BIT(ADCx->IER, |
| marcozecchini | 0:9fca2b23d0ba | 554 | ( LL_ADC_IT_ADRDY |
| marcozecchini | 0:9fca2b23d0ba | 555 | | LL_ADC_IT_EOC |
| marcozecchini | 0:9fca2b23d0ba | 556 | | LL_ADC_IT_EOS |
| marcozecchini | 0:9fca2b23d0ba | 557 | | LL_ADC_IT_OVR |
| marcozecchini | 0:9fca2b23d0ba | 558 | | LL_ADC_IT_EOSMP |
| marcozecchini | 0:9fca2b23d0ba | 559 | | LL_ADC_IT_JEOC |
| marcozecchini | 0:9fca2b23d0ba | 560 | | LL_ADC_IT_JEOS |
| marcozecchini | 0:9fca2b23d0ba | 561 | | LL_ADC_IT_JQOVF |
| marcozecchini | 0:9fca2b23d0ba | 562 | | LL_ADC_IT_AWD1 |
| marcozecchini | 0:9fca2b23d0ba | 563 | | LL_ADC_IT_AWD2 |
| marcozecchini | 0:9fca2b23d0ba | 564 | | LL_ADC_IT_AWD3 ) |
| marcozecchini | 0:9fca2b23d0ba | 565 | ); |
| marcozecchini | 0:9fca2b23d0ba | 566 | |
| marcozecchini | 0:9fca2b23d0ba | 567 | /* Reset register ISR */ |
| marcozecchini | 0:9fca2b23d0ba | 568 | SET_BIT(ADCx->ISR, |
| marcozecchini | 0:9fca2b23d0ba | 569 | ( LL_ADC_FLAG_ADRDY |
| marcozecchini | 0:9fca2b23d0ba | 570 | | LL_ADC_FLAG_EOC |
| marcozecchini | 0:9fca2b23d0ba | 571 | | LL_ADC_FLAG_EOS |
| marcozecchini | 0:9fca2b23d0ba | 572 | | LL_ADC_FLAG_OVR |
| marcozecchini | 0:9fca2b23d0ba | 573 | | LL_ADC_FLAG_EOSMP |
| marcozecchini | 0:9fca2b23d0ba | 574 | | LL_ADC_FLAG_JEOC |
| marcozecchini | 0:9fca2b23d0ba | 575 | | LL_ADC_FLAG_JEOS |
| marcozecchini | 0:9fca2b23d0ba | 576 | | LL_ADC_FLAG_JQOVF |
| marcozecchini | 0:9fca2b23d0ba | 577 | | LL_ADC_FLAG_AWD1 |
| marcozecchini | 0:9fca2b23d0ba | 578 | | LL_ADC_FLAG_AWD2 |
| marcozecchini | 0:9fca2b23d0ba | 579 | | LL_ADC_FLAG_AWD3 ) |
| marcozecchini | 0:9fca2b23d0ba | 580 | ); |
| marcozecchini | 0:9fca2b23d0ba | 581 | |
| marcozecchini | 0:9fca2b23d0ba | 582 | /* Reset register CR */ |
| marcozecchini | 0:9fca2b23d0ba | 583 | /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ |
| marcozecchini | 0:9fca2b23d0ba | 584 | /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ |
| marcozecchini | 0:9fca2b23d0ba | 585 | /* access mode "read-set": no direct reset applicable. */ |
| marcozecchini | 0:9fca2b23d0ba | 586 | /* - Reset Calibration mode to default setting (single ended). */ |
| marcozecchini | 0:9fca2b23d0ba | 587 | /* - Disable ADC internal voltage regulator. */ |
| marcozecchini | 0:9fca2b23d0ba | 588 | /* - Enable ADC deep power down. */ |
| marcozecchini | 0:9fca2b23d0ba | 589 | /* Note: ADC internal voltage regulator disable and ADC deep power */ |
| marcozecchini | 0:9fca2b23d0ba | 590 | /* down enable are conditioned to ADC state disabled: */ |
| marcozecchini | 0:9fca2b23d0ba | 591 | /* already done above. */ |
| marcozecchini | 0:9fca2b23d0ba | 592 | CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); |
| marcozecchini | 0:9fca2b23d0ba | 593 | SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); |
| marcozecchini | 0:9fca2b23d0ba | 594 | |
| marcozecchini | 0:9fca2b23d0ba | 595 | /* Reset register CFGR */ |
| marcozecchini | 0:9fca2b23d0ba | 596 | MODIFY_REG(ADCx->CFGR, |
| marcozecchini | 0:9fca2b23d0ba | 597 | ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
| marcozecchini | 0:9fca2b23d0ba | 598 | | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
| marcozecchini | 0:9fca2b23d0ba | 599 | | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
| marcozecchini | 0:9fca2b23d0ba | 600 | | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
| marcozecchini | 0:9fca2b23d0ba | 601 | | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |
| marcozecchini | 0:9fca2b23d0ba | 602 | | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ), |
| marcozecchini | 0:9fca2b23d0ba | 603 | ADC_CFGR_JQDIS |
| marcozecchini | 0:9fca2b23d0ba | 604 | ); |
| marcozecchini | 0:9fca2b23d0ba | 605 | |
| marcozecchini | 0:9fca2b23d0ba | 606 | /* Reset register CFGR2 */ |
| marcozecchini | 0:9fca2b23d0ba | 607 | CLEAR_BIT(ADCx->CFGR2, |
| marcozecchini | 0:9fca2b23d0ba | 608 | ( ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
| marcozecchini | 0:9fca2b23d0ba | 609 | | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) |
| marcozecchini | 0:9fca2b23d0ba | 610 | ); |
| marcozecchini | 0:9fca2b23d0ba | 611 | |
| marcozecchini | 0:9fca2b23d0ba | 612 | /* Reset register SMPR1 */ |
| marcozecchini | 0:9fca2b23d0ba | 613 | CLEAR_BIT(ADCx->SMPR1, |
| marcozecchini | 0:9fca2b23d0ba | 614 | ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
| marcozecchini | 0:9fca2b23d0ba | 615 | | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
| marcozecchini | 0:9fca2b23d0ba | 616 | | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) |
| marcozecchini | 0:9fca2b23d0ba | 617 | ); |
| marcozecchini | 0:9fca2b23d0ba | 618 | |
| marcozecchini | 0:9fca2b23d0ba | 619 | /* Reset register SMPR2 */ |
| marcozecchini | 0:9fca2b23d0ba | 620 | CLEAR_BIT(ADCx->SMPR2, |
| marcozecchini | 0:9fca2b23d0ba | 621 | ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
| marcozecchini | 0:9fca2b23d0ba | 622 | | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
| marcozecchini | 0:9fca2b23d0ba | 623 | | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) |
| marcozecchini | 0:9fca2b23d0ba | 624 | ); |
| marcozecchini | 0:9fca2b23d0ba | 625 | |
| marcozecchini | 0:9fca2b23d0ba | 626 | /* Reset register TR1 */ |
| marcozecchini | 0:9fca2b23d0ba | 627 | MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); |
| marcozecchini | 0:9fca2b23d0ba | 628 | |
| marcozecchini | 0:9fca2b23d0ba | 629 | /* Reset register TR2 */ |
| marcozecchini | 0:9fca2b23d0ba | 630 | MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); |
| marcozecchini | 0:9fca2b23d0ba | 631 | |
| marcozecchini | 0:9fca2b23d0ba | 632 | /* Reset register TR3 */ |
| marcozecchini | 0:9fca2b23d0ba | 633 | MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); |
| marcozecchini | 0:9fca2b23d0ba | 634 | |
| marcozecchini | 0:9fca2b23d0ba | 635 | /* Reset register SQR1 */ |
| marcozecchini | 0:9fca2b23d0ba | 636 | CLEAR_BIT(ADCx->SQR1, |
| marcozecchini | 0:9fca2b23d0ba | 637 | ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
| marcozecchini | 0:9fca2b23d0ba | 638 | | ADC_SQR1_SQ1 | ADC_SQR1_L) |
| marcozecchini | 0:9fca2b23d0ba | 639 | ); |
| marcozecchini | 0:9fca2b23d0ba | 640 | |
| marcozecchini | 0:9fca2b23d0ba | 641 | /* Reset register SQR2 */ |
| marcozecchini | 0:9fca2b23d0ba | 642 | CLEAR_BIT(ADCx->SQR2, |
| marcozecchini | 0:9fca2b23d0ba | 643 | ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
| marcozecchini | 0:9fca2b23d0ba | 644 | | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) |
| marcozecchini | 0:9fca2b23d0ba | 645 | ); |
| marcozecchini | 0:9fca2b23d0ba | 646 | |
| marcozecchini | 0:9fca2b23d0ba | 647 | /* Reset register SQR3 */ |
| marcozecchini | 0:9fca2b23d0ba | 648 | CLEAR_BIT(ADCx->SQR3, |
| marcozecchini | 0:9fca2b23d0ba | 649 | ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
| marcozecchini | 0:9fca2b23d0ba | 650 | | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) |
| marcozecchini | 0:9fca2b23d0ba | 651 | ); |
| marcozecchini | 0:9fca2b23d0ba | 652 | |
| marcozecchini | 0:9fca2b23d0ba | 653 | /* Reset register SQR4 */ |
| marcozecchini | 0:9fca2b23d0ba | 654 | CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); |
| marcozecchini | 0:9fca2b23d0ba | 655 | |
| marcozecchini | 0:9fca2b23d0ba | 656 | /* Reset register JSQR */ |
| marcozecchini | 0:9fca2b23d0ba | 657 | CLEAR_BIT(ADCx->JSQR, |
| marcozecchini | 0:9fca2b23d0ba | 658 | ( ADC_JSQR_JL |
| marcozecchini | 0:9fca2b23d0ba | 659 | | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |
| marcozecchini | 0:9fca2b23d0ba | 660 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
| marcozecchini | 0:9fca2b23d0ba | 661 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
| marcozecchini | 0:9fca2b23d0ba | 662 | ); |
| marcozecchini | 0:9fca2b23d0ba | 663 | |
| marcozecchini | 0:9fca2b23d0ba | 664 | /* Reset register DR */ |
| marcozecchini | 0:9fca2b23d0ba | 665 | /* Note: bits in access mode read only, no direct reset applicable */ |
| marcozecchini | 0:9fca2b23d0ba | 666 | |
| marcozecchini | 0:9fca2b23d0ba | 667 | /* Reset register OFR1 */ |
| marcozecchini | 0:9fca2b23d0ba | 668 | CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); |
| marcozecchini | 0:9fca2b23d0ba | 669 | /* Reset register OFR2 */ |
| marcozecchini | 0:9fca2b23d0ba | 670 | CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); |
| marcozecchini | 0:9fca2b23d0ba | 671 | /* Reset register OFR3 */ |
| marcozecchini | 0:9fca2b23d0ba | 672 | CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); |
| marcozecchini | 0:9fca2b23d0ba | 673 | /* Reset register OFR4 */ |
| marcozecchini | 0:9fca2b23d0ba | 674 | CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); |
| marcozecchini | 0:9fca2b23d0ba | 675 | |
| marcozecchini | 0:9fca2b23d0ba | 676 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
| marcozecchini | 0:9fca2b23d0ba | 677 | /* Note: bits in access mode read only, no direct reset applicable */ |
| marcozecchini | 0:9fca2b23d0ba | 678 | |
| marcozecchini | 0:9fca2b23d0ba | 679 | /* Reset register AWD2CR */ |
| marcozecchini | 0:9fca2b23d0ba | 680 | CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); |
| marcozecchini | 0:9fca2b23d0ba | 681 | |
| marcozecchini | 0:9fca2b23d0ba | 682 | /* Reset register AWD3CR */ |
| marcozecchini | 0:9fca2b23d0ba | 683 | CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); |
| marcozecchini | 0:9fca2b23d0ba | 684 | |
| marcozecchini | 0:9fca2b23d0ba | 685 | /* Reset register DIFSEL */ |
| marcozecchini | 0:9fca2b23d0ba | 686 | CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); |
| marcozecchini | 0:9fca2b23d0ba | 687 | |
| marcozecchini | 0:9fca2b23d0ba | 688 | /* Reset register CALFACT */ |
| marcozecchini | 0:9fca2b23d0ba | 689 | CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); |
| marcozecchini | 0:9fca2b23d0ba | 690 | } |
| marcozecchini | 0:9fca2b23d0ba | 691 | else |
| marcozecchini | 0:9fca2b23d0ba | 692 | { |
| marcozecchini | 0:9fca2b23d0ba | 693 | /* ADC instance is in an unknown state */ |
| marcozecchini | 0:9fca2b23d0ba | 694 | /* Need to performing a hard reset of ADC instance, using high level */ |
| marcozecchini | 0:9fca2b23d0ba | 695 | /* clock source RCC ADC reset. */ |
| marcozecchini | 0:9fca2b23d0ba | 696 | /* Caution: On this STM32 serie, if several ADC instances are available */ |
| marcozecchini | 0:9fca2b23d0ba | 697 | /* on the selected device, RCC ADC reset will reset */ |
| marcozecchini | 0:9fca2b23d0ba | 698 | /* all ADC instances belonging to the common ADC instance. */ |
| marcozecchini | 0:9fca2b23d0ba | 699 | /* Caution: On this STM32 serie, if several ADC instances are available */ |
| marcozecchini | 0:9fca2b23d0ba | 700 | /* on the selected device, RCC ADC reset will reset */ |
| marcozecchini | 0:9fca2b23d0ba | 701 | /* all ADC instances belonging to the common ADC instance. */ |
| marcozecchini | 0:9fca2b23d0ba | 702 | status = ERROR; |
| marcozecchini | 0:9fca2b23d0ba | 703 | } |
| marcozecchini | 0:9fca2b23d0ba | 704 | |
| marcozecchini | 0:9fca2b23d0ba | 705 | return status; |
| marcozecchini | 0:9fca2b23d0ba | 706 | } |
| marcozecchini | 0:9fca2b23d0ba | 707 | |
| marcozecchini | 0:9fca2b23d0ba | 708 | /** |
| marcozecchini | 0:9fca2b23d0ba | 709 | * @brief Initialize some features of ADC instance. |
| marcozecchini | 0:9fca2b23d0ba | 710 | * @note These parameters have an impact on ADC scope: ADC instance. |
| marcozecchini | 0:9fca2b23d0ba | 711 | * Affects both group regular and group injected (availability |
| marcozecchini | 0:9fca2b23d0ba | 712 | * of ADC group injected depends on STM32 families). |
| marcozecchini | 0:9fca2b23d0ba | 713 | * Refer to corresponding unitary functions into |
| marcozecchini | 0:9fca2b23d0ba | 714 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
| marcozecchini | 0:9fca2b23d0ba | 715 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| marcozecchini | 0:9fca2b23d0ba | 716 | * is conditioned to ADC state: |
| marcozecchini | 0:9fca2b23d0ba | 717 | * ADC instance must be disabled. |
| marcozecchini | 0:9fca2b23d0ba | 718 | * This condition is applied to all ADC features, for efficiency |
| marcozecchini | 0:9fca2b23d0ba | 719 | * and compatibility over all STM32 families. However, the different |
| marcozecchini | 0:9fca2b23d0ba | 720 | * features can be set under different ADC state conditions |
| marcozecchini | 0:9fca2b23d0ba | 721 | * (setting possible with ADC enabled without conversion on going, |
| marcozecchini | 0:9fca2b23d0ba | 722 | * ADC enabled with conversion on going, ...) |
| marcozecchini | 0:9fca2b23d0ba | 723 | * Each feature can be updated afterwards with a unitary function |
| marcozecchini | 0:9fca2b23d0ba | 724 | * and potentially with ADC in a different state than disabled, |
| marcozecchini | 0:9fca2b23d0ba | 725 | * refer to description of each function for setting |
| marcozecchini | 0:9fca2b23d0ba | 726 | * conditioned to ADC state. |
| marcozecchini | 0:9fca2b23d0ba | 727 | * @note After using this function, some other features must be configured |
| marcozecchini | 0:9fca2b23d0ba | 728 | * using LL unitary functions. |
| marcozecchini | 0:9fca2b23d0ba | 729 | * The minimum configuration remaining to be done is: |
| marcozecchini | 0:9fca2b23d0ba | 730 | * - Set ADC group regular or group injected sequencer: |
| marcozecchini | 0:9fca2b23d0ba | 731 | * map channel on the selected sequencer rank. |
| marcozecchini | 0:9fca2b23d0ba | 732 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| marcozecchini | 0:9fca2b23d0ba | 733 | * - Set ADC channel sampling time |
| marcozecchini | 0:9fca2b23d0ba | 734 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| marcozecchini | 0:9fca2b23d0ba | 735 | * @param ADCx ADC instance |
| marcozecchini | 0:9fca2b23d0ba | 736 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 737 | * @retval An ErrorStatus enumeration value: |
| marcozecchini | 0:9fca2b23d0ba | 738 | * - SUCCESS: ADC registers are initialized |
| marcozecchini | 0:9fca2b23d0ba | 739 | * - ERROR: ADC registers are not initialized |
| marcozecchini | 0:9fca2b23d0ba | 740 | */ |
| marcozecchini | 0:9fca2b23d0ba | 741 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 742 | { |
| marcozecchini | 0:9fca2b23d0ba | 743 | ErrorStatus status = SUCCESS; |
| marcozecchini | 0:9fca2b23d0ba | 744 | |
| marcozecchini | 0:9fca2b23d0ba | 745 | /* Check the parameters */ |
| marcozecchini | 0:9fca2b23d0ba | 746 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| marcozecchini | 0:9fca2b23d0ba | 747 | |
| marcozecchini | 0:9fca2b23d0ba | 748 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
| marcozecchini | 0:9fca2b23d0ba | 749 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
| marcozecchini | 0:9fca2b23d0ba | 750 | assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); |
| marcozecchini | 0:9fca2b23d0ba | 751 | |
| marcozecchini | 0:9fca2b23d0ba | 752 | /* Note: Hardware constraint (refer to description of this function): */ |
| marcozecchini | 0:9fca2b23d0ba | 753 | /* ADC instance must be disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 754 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 755 | { |
| marcozecchini | 0:9fca2b23d0ba | 756 | /* Configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 757 | /* - ADC instance */ |
| marcozecchini | 0:9fca2b23d0ba | 758 | /* - Set ADC data resolution */ |
| marcozecchini | 0:9fca2b23d0ba | 759 | /* - Set ADC conversion data alignment */ |
| marcozecchini | 0:9fca2b23d0ba | 760 | /* - Set ADC low power mode */ |
| marcozecchini | 0:9fca2b23d0ba | 761 | MODIFY_REG(ADCx->CFGR, |
| marcozecchini | 0:9fca2b23d0ba | 762 | ADC_CFGR_RES |
| marcozecchini | 0:9fca2b23d0ba | 763 | | ADC_CFGR_ALIGN |
| marcozecchini | 0:9fca2b23d0ba | 764 | | ADC_CFGR_AUTDLY |
| marcozecchini | 0:9fca2b23d0ba | 765 | , |
| marcozecchini | 0:9fca2b23d0ba | 766 | ADC_InitStruct->Resolution |
| marcozecchini | 0:9fca2b23d0ba | 767 | | ADC_InitStruct->DataAlignment |
| marcozecchini | 0:9fca2b23d0ba | 768 | | ADC_InitStruct->LowPowerMode |
| marcozecchini | 0:9fca2b23d0ba | 769 | ); |
| marcozecchini | 0:9fca2b23d0ba | 770 | |
| marcozecchini | 0:9fca2b23d0ba | 771 | } |
| marcozecchini | 0:9fca2b23d0ba | 772 | else |
| marcozecchini | 0:9fca2b23d0ba | 773 | { |
| marcozecchini | 0:9fca2b23d0ba | 774 | /* Initialization error: ADC instance is not disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 775 | status = ERROR; |
| marcozecchini | 0:9fca2b23d0ba | 776 | } |
| marcozecchini | 0:9fca2b23d0ba | 777 | return status; |
| marcozecchini | 0:9fca2b23d0ba | 778 | } |
| marcozecchini | 0:9fca2b23d0ba | 779 | |
| marcozecchini | 0:9fca2b23d0ba | 780 | /** |
| marcozecchini | 0:9fca2b23d0ba | 781 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
| marcozecchini | 0:9fca2b23d0ba | 782 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 783 | * whose fields will be set to default values. |
| marcozecchini | 0:9fca2b23d0ba | 784 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 785 | */ |
| marcozecchini | 0:9fca2b23d0ba | 786 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 787 | { |
| marcozecchini | 0:9fca2b23d0ba | 788 | /* Set ADC_InitStruct fields to default values */ |
| marcozecchini | 0:9fca2b23d0ba | 789 | /* Set fields of ADC instance */ |
| marcozecchini | 0:9fca2b23d0ba | 790 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
| marcozecchini | 0:9fca2b23d0ba | 791 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
| marcozecchini | 0:9fca2b23d0ba | 792 | ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; |
| marcozecchini | 0:9fca2b23d0ba | 793 | |
| marcozecchini | 0:9fca2b23d0ba | 794 | } |
| marcozecchini | 0:9fca2b23d0ba | 795 | |
| marcozecchini | 0:9fca2b23d0ba | 796 | /** |
| marcozecchini | 0:9fca2b23d0ba | 797 | * @brief Initialize some features of ADC group regular. |
| marcozecchini | 0:9fca2b23d0ba | 798 | * @note These parameters have an impact on ADC scope: ADC group regular. |
| marcozecchini | 0:9fca2b23d0ba | 799 | * Refer to corresponding unitary functions into |
| marcozecchini | 0:9fca2b23d0ba | 800 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| marcozecchini | 0:9fca2b23d0ba | 801 | * (functions with prefix "REG"). |
| marcozecchini | 0:9fca2b23d0ba | 802 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| marcozecchini | 0:9fca2b23d0ba | 803 | * is conditioned to ADC state: |
| marcozecchini | 0:9fca2b23d0ba | 804 | * ADC instance must be disabled. |
| marcozecchini | 0:9fca2b23d0ba | 805 | * This condition is applied to all ADC features, for efficiency |
| marcozecchini | 0:9fca2b23d0ba | 806 | * and compatibility over all STM32 families. However, the different |
| marcozecchini | 0:9fca2b23d0ba | 807 | * features can be set under different ADC state conditions |
| marcozecchini | 0:9fca2b23d0ba | 808 | * (setting possible with ADC enabled without conversion on going, |
| marcozecchini | 0:9fca2b23d0ba | 809 | * ADC enabled with conversion on going, ...) |
| marcozecchini | 0:9fca2b23d0ba | 810 | * Each feature can be updated afterwards with a unitary function |
| marcozecchini | 0:9fca2b23d0ba | 811 | * and potentially with ADC in a different state than disabled, |
| marcozecchini | 0:9fca2b23d0ba | 812 | * refer to description of each function for setting |
| marcozecchini | 0:9fca2b23d0ba | 813 | * conditioned to ADC state. |
| marcozecchini | 0:9fca2b23d0ba | 814 | * @note After using this function, other features must be configured |
| marcozecchini | 0:9fca2b23d0ba | 815 | * using LL unitary functions. |
| marcozecchini | 0:9fca2b23d0ba | 816 | * The minimum configuration remaining to be done is: |
| marcozecchini | 0:9fca2b23d0ba | 817 | * - Set ADC group regular or group injected sequencer: |
| marcozecchini | 0:9fca2b23d0ba | 818 | * map channel on the selected sequencer rank. |
| marcozecchini | 0:9fca2b23d0ba | 819 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| marcozecchini | 0:9fca2b23d0ba | 820 | * - Set ADC channel sampling time |
| marcozecchini | 0:9fca2b23d0ba | 821 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| marcozecchini | 0:9fca2b23d0ba | 822 | * @param ADCx ADC instance |
| marcozecchini | 0:9fca2b23d0ba | 823 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 824 | * @retval An ErrorStatus enumeration value: |
| marcozecchini | 0:9fca2b23d0ba | 825 | * - SUCCESS: ADC registers are initialized |
| marcozecchini | 0:9fca2b23d0ba | 826 | * - ERROR: ADC registers are not initialized |
| marcozecchini | 0:9fca2b23d0ba | 827 | */ |
| marcozecchini | 0:9fca2b23d0ba | 828 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 829 | { |
| marcozecchini | 0:9fca2b23d0ba | 830 | ErrorStatus status = SUCCESS; |
| marcozecchini | 0:9fca2b23d0ba | 831 | |
| marcozecchini | 0:9fca2b23d0ba | 832 | /* Check the parameters */ |
| marcozecchini | 0:9fca2b23d0ba | 833 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| marcozecchini | 0:9fca2b23d0ba | 834 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
| marcozecchini | 0:9fca2b23d0ba | 835 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
| marcozecchini | 0:9fca2b23d0ba | 836 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| marcozecchini | 0:9fca2b23d0ba | 837 | { |
| marcozecchini | 0:9fca2b23d0ba | 838 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
| marcozecchini | 0:9fca2b23d0ba | 839 | } |
| marcozecchini | 0:9fca2b23d0ba | 840 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
| marcozecchini | 0:9fca2b23d0ba | 841 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
| marcozecchini | 0:9fca2b23d0ba | 842 | assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); |
| marcozecchini | 0:9fca2b23d0ba | 843 | |
| marcozecchini | 0:9fca2b23d0ba | 844 | /* Note: Hardware constraint (refer to description of this function): */ |
| marcozecchini | 0:9fca2b23d0ba | 845 | /* ADC instance must be disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 846 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 847 | { |
| marcozecchini | 0:9fca2b23d0ba | 848 | /* Configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 849 | /* - ADC group regular */ |
| marcozecchini | 0:9fca2b23d0ba | 850 | /* - Set ADC group regular trigger source */ |
| marcozecchini | 0:9fca2b23d0ba | 851 | /* - Set ADC group regular sequencer length */ |
| marcozecchini | 0:9fca2b23d0ba | 852 | /* - Set ADC group regular sequencer discontinuous mode */ |
| marcozecchini | 0:9fca2b23d0ba | 853 | /* - Set ADC group regular continuous mode */ |
| marcozecchini | 0:9fca2b23d0ba | 854 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
| marcozecchini | 0:9fca2b23d0ba | 855 | /* transfer by DMA, and DMA requests mode */ |
| marcozecchini | 0:9fca2b23d0ba | 856 | /* - Set ADC group regular overrun behavior */ |
| marcozecchini | 0:9fca2b23d0ba | 857 | /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ |
| marcozecchini | 0:9fca2b23d0ba | 858 | /* setting of trigger source to SW start. */ |
| marcozecchini | 0:9fca2b23d0ba | 859 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| marcozecchini | 0:9fca2b23d0ba | 860 | { |
| marcozecchini | 0:9fca2b23d0ba | 861 | MODIFY_REG(ADCx->CFGR, |
| marcozecchini | 0:9fca2b23d0ba | 862 | ADC_CFGR_EXTSEL |
| marcozecchini | 0:9fca2b23d0ba | 863 | | ADC_CFGR_EXTEN |
| marcozecchini | 0:9fca2b23d0ba | 864 | | ADC_CFGR_DISCEN |
| marcozecchini | 0:9fca2b23d0ba | 865 | | ADC_CFGR_DISCNUM |
| marcozecchini | 0:9fca2b23d0ba | 866 | | ADC_CFGR_CONT |
| marcozecchini | 0:9fca2b23d0ba | 867 | | ADC_CFGR_DMAEN |
| marcozecchini | 0:9fca2b23d0ba | 868 | | ADC_CFGR_DMACFG |
| marcozecchini | 0:9fca2b23d0ba | 869 | | ADC_CFGR_OVRMOD |
| marcozecchini | 0:9fca2b23d0ba | 870 | , |
| marcozecchini | 0:9fca2b23d0ba | 871 | ADC_REG_InitStruct->TriggerSource |
| marcozecchini | 0:9fca2b23d0ba | 872 | | ADC_REG_InitStruct->SequencerDiscont |
| marcozecchini | 0:9fca2b23d0ba | 873 | | ADC_REG_InitStruct->ContinuousMode |
| marcozecchini | 0:9fca2b23d0ba | 874 | | ADC_REG_InitStruct->DMATransfer |
| marcozecchini | 0:9fca2b23d0ba | 875 | | ADC_REG_InitStruct->Overrun |
| marcozecchini | 0:9fca2b23d0ba | 876 | ); |
| marcozecchini | 0:9fca2b23d0ba | 877 | } |
| marcozecchini | 0:9fca2b23d0ba | 878 | else |
| marcozecchini | 0:9fca2b23d0ba | 879 | { |
| marcozecchini | 0:9fca2b23d0ba | 880 | MODIFY_REG(ADCx->CFGR, |
| marcozecchini | 0:9fca2b23d0ba | 881 | ADC_CFGR_EXTSEL |
| marcozecchini | 0:9fca2b23d0ba | 882 | | ADC_CFGR_EXTEN |
| marcozecchini | 0:9fca2b23d0ba | 883 | | ADC_CFGR_DISCEN |
| marcozecchini | 0:9fca2b23d0ba | 884 | | ADC_CFGR_DISCNUM |
| marcozecchini | 0:9fca2b23d0ba | 885 | | ADC_CFGR_CONT |
| marcozecchini | 0:9fca2b23d0ba | 886 | | ADC_CFGR_DMAEN |
| marcozecchini | 0:9fca2b23d0ba | 887 | | ADC_CFGR_DMACFG |
| marcozecchini | 0:9fca2b23d0ba | 888 | | ADC_CFGR_OVRMOD |
| marcozecchini | 0:9fca2b23d0ba | 889 | , |
| marcozecchini | 0:9fca2b23d0ba | 890 | ADC_REG_InitStruct->TriggerSource |
| marcozecchini | 0:9fca2b23d0ba | 891 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
| marcozecchini | 0:9fca2b23d0ba | 892 | | ADC_REG_InitStruct->ContinuousMode |
| marcozecchini | 0:9fca2b23d0ba | 893 | | ADC_REG_InitStruct->DMATransfer |
| marcozecchini | 0:9fca2b23d0ba | 894 | | ADC_REG_InitStruct->Overrun |
| marcozecchini | 0:9fca2b23d0ba | 895 | ); |
| marcozecchini | 0:9fca2b23d0ba | 896 | } |
| marcozecchini | 0:9fca2b23d0ba | 897 | |
| marcozecchini | 0:9fca2b23d0ba | 898 | /* Set ADC group regular sequencer length and scan direction */ |
| marcozecchini | 0:9fca2b23d0ba | 899 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
| marcozecchini | 0:9fca2b23d0ba | 900 | } |
| marcozecchini | 0:9fca2b23d0ba | 901 | else |
| marcozecchini | 0:9fca2b23d0ba | 902 | { |
| marcozecchini | 0:9fca2b23d0ba | 903 | /* Initialization error: ADC instance is not disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 904 | status = ERROR; |
| marcozecchini | 0:9fca2b23d0ba | 905 | } |
| marcozecchini | 0:9fca2b23d0ba | 906 | return status; |
| marcozecchini | 0:9fca2b23d0ba | 907 | } |
| marcozecchini | 0:9fca2b23d0ba | 908 | |
| marcozecchini | 0:9fca2b23d0ba | 909 | /** |
| marcozecchini | 0:9fca2b23d0ba | 910 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
| marcozecchini | 0:9fca2b23d0ba | 911 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 912 | * whose fields will be set to default values. |
| marcozecchini | 0:9fca2b23d0ba | 913 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 914 | */ |
| marcozecchini | 0:9fca2b23d0ba | 915 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 916 | { |
| marcozecchini | 0:9fca2b23d0ba | 917 | /* Set ADC_REG_InitStruct fields to default values */ |
| marcozecchini | 0:9fca2b23d0ba | 918 | /* Set fields of ADC group regular */ |
| marcozecchini | 0:9fca2b23d0ba | 919 | /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ |
| marcozecchini | 0:9fca2b23d0ba | 920 | /* setting of trigger source to SW start. */ |
| marcozecchini | 0:9fca2b23d0ba | 921 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
| marcozecchini | 0:9fca2b23d0ba | 922 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
| marcozecchini | 0:9fca2b23d0ba | 923 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
| marcozecchini | 0:9fca2b23d0ba | 924 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
| marcozecchini | 0:9fca2b23d0ba | 925 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
| marcozecchini | 0:9fca2b23d0ba | 926 | ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; |
| marcozecchini | 0:9fca2b23d0ba | 927 | } |
| marcozecchini | 0:9fca2b23d0ba | 928 | |
| marcozecchini | 0:9fca2b23d0ba | 929 | /** |
| marcozecchini | 0:9fca2b23d0ba | 930 | * @brief Initialize some features of ADC group injected. |
| marcozecchini | 0:9fca2b23d0ba | 931 | * @note These parameters have an impact on ADC scope: ADC group injected. |
| marcozecchini | 0:9fca2b23d0ba | 932 | * Refer to corresponding unitary functions into |
| marcozecchini | 0:9fca2b23d0ba | 933 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| marcozecchini | 0:9fca2b23d0ba | 934 | * (functions with prefix "INJ"). |
| marcozecchini | 0:9fca2b23d0ba | 935 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| marcozecchini | 0:9fca2b23d0ba | 936 | * is conditioned to ADC state: |
| marcozecchini | 0:9fca2b23d0ba | 937 | * ADC instance must be disabled. |
| marcozecchini | 0:9fca2b23d0ba | 938 | * This condition is applied to all ADC features, for efficiency |
| marcozecchini | 0:9fca2b23d0ba | 939 | * and compatibility over all STM32 families. However, the different |
| marcozecchini | 0:9fca2b23d0ba | 940 | * features can be set under different ADC state conditions |
| marcozecchini | 0:9fca2b23d0ba | 941 | * (setting possible with ADC enabled without conversion on going, |
| marcozecchini | 0:9fca2b23d0ba | 942 | * ADC enabled with conversion on going, ...) |
| marcozecchini | 0:9fca2b23d0ba | 943 | * Each feature can be updated afterwards with a unitary function |
| marcozecchini | 0:9fca2b23d0ba | 944 | * and potentially with ADC in a different state than disabled, |
| marcozecchini | 0:9fca2b23d0ba | 945 | * refer to description of each function for setting |
| marcozecchini | 0:9fca2b23d0ba | 946 | * conditioned to ADC state. |
| marcozecchini | 0:9fca2b23d0ba | 947 | * @note After using this function, other features must be configured |
| marcozecchini | 0:9fca2b23d0ba | 948 | * using LL unitary functions. |
| marcozecchini | 0:9fca2b23d0ba | 949 | * The minimum configuration remaining to be done is: |
| marcozecchini | 0:9fca2b23d0ba | 950 | * - Set ADC group injected sequencer: |
| marcozecchini | 0:9fca2b23d0ba | 951 | * map channel on the selected sequencer rank. |
| marcozecchini | 0:9fca2b23d0ba | 952 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
| marcozecchini | 0:9fca2b23d0ba | 953 | * - Set ADC channel sampling time |
| marcozecchini | 0:9fca2b23d0ba | 954 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| marcozecchini | 0:9fca2b23d0ba | 955 | * @param ADCx ADC instance |
| marcozecchini | 0:9fca2b23d0ba | 956 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 957 | * @retval An ErrorStatus enumeration value: |
| marcozecchini | 0:9fca2b23d0ba | 958 | * - SUCCESS: ADC registers are initialized |
| marcozecchini | 0:9fca2b23d0ba | 959 | * - ERROR: ADC registers are not initialized |
| marcozecchini | 0:9fca2b23d0ba | 960 | */ |
| marcozecchini | 0:9fca2b23d0ba | 961 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 962 | { |
| marcozecchini | 0:9fca2b23d0ba | 963 | ErrorStatus status = SUCCESS; |
| marcozecchini | 0:9fca2b23d0ba | 964 | |
| marcozecchini | 0:9fca2b23d0ba | 965 | /* Check the parameters */ |
| marcozecchini | 0:9fca2b23d0ba | 966 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| marcozecchini | 0:9fca2b23d0ba | 967 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
| marcozecchini | 0:9fca2b23d0ba | 968 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
| marcozecchini | 0:9fca2b23d0ba | 969 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
| marcozecchini | 0:9fca2b23d0ba | 970 | { |
| marcozecchini | 0:9fca2b23d0ba | 971 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
| marcozecchini | 0:9fca2b23d0ba | 972 | } |
| marcozecchini | 0:9fca2b23d0ba | 973 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
| marcozecchini | 0:9fca2b23d0ba | 974 | |
| marcozecchini | 0:9fca2b23d0ba | 975 | /* Note: Hardware constraint (refer to description of this function): */ |
| marcozecchini | 0:9fca2b23d0ba | 976 | /* ADC instance must be disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 977 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| marcozecchini | 0:9fca2b23d0ba | 978 | { |
| marcozecchini | 0:9fca2b23d0ba | 979 | /* Configuration of ADC hierarchical scope: */ |
| marcozecchini | 0:9fca2b23d0ba | 980 | /* - ADC group injected */ |
| marcozecchini | 0:9fca2b23d0ba | 981 | /* - Set ADC group injected trigger source */ |
| marcozecchini | 0:9fca2b23d0ba | 982 | /* - Set ADC group injected sequencer length */ |
| marcozecchini | 0:9fca2b23d0ba | 983 | /* - Set ADC group injected sequencer discontinuous mode */ |
| marcozecchini | 0:9fca2b23d0ba | 984 | /* - Set ADC group injected conversion trigger: independent or */ |
| marcozecchini | 0:9fca2b23d0ba | 985 | /* from ADC group regular */ |
| marcozecchini | 0:9fca2b23d0ba | 986 | /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ |
| marcozecchini | 0:9fca2b23d0ba | 987 | /* setting of trigger source to SW start. */ |
| marcozecchini | 0:9fca2b23d0ba | 988 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| marcozecchini | 0:9fca2b23d0ba | 989 | { |
| marcozecchini | 0:9fca2b23d0ba | 990 | MODIFY_REG(ADCx->CFGR, |
| marcozecchini | 0:9fca2b23d0ba | 991 | ADC_CFGR_JDISCEN |
| marcozecchini | 0:9fca2b23d0ba | 992 | | ADC_CFGR_JAUTO |
| marcozecchini | 0:9fca2b23d0ba | 993 | , |
| marcozecchini | 0:9fca2b23d0ba | 994 | ADC_INJ_InitStruct->SequencerDiscont |
| marcozecchini | 0:9fca2b23d0ba | 995 | | ADC_INJ_InitStruct->TrigAuto |
| marcozecchini | 0:9fca2b23d0ba | 996 | ); |
| marcozecchini | 0:9fca2b23d0ba | 997 | } |
| marcozecchini | 0:9fca2b23d0ba | 998 | else |
| marcozecchini | 0:9fca2b23d0ba | 999 | { |
| marcozecchini | 0:9fca2b23d0ba | 1000 | MODIFY_REG(ADCx->CFGR, |
| marcozecchini | 0:9fca2b23d0ba | 1001 | ADC_CFGR_JDISCEN |
| marcozecchini | 0:9fca2b23d0ba | 1002 | | ADC_CFGR_JAUTO |
| marcozecchini | 0:9fca2b23d0ba | 1003 | , |
| marcozecchini | 0:9fca2b23d0ba | 1004 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
| marcozecchini | 0:9fca2b23d0ba | 1005 | | ADC_INJ_InitStruct->TrigAuto |
| marcozecchini | 0:9fca2b23d0ba | 1006 | ); |
| marcozecchini | 0:9fca2b23d0ba | 1007 | } |
| marcozecchini | 0:9fca2b23d0ba | 1008 | |
| marcozecchini | 0:9fca2b23d0ba | 1009 | MODIFY_REG(ADCx->JSQR, |
| marcozecchini | 0:9fca2b23d0ba | 1010 | ADC_JSQR_JEXTSEL |
| marcozecchini | 0:9fca2b23d0ba | 1011 | | ADC_JSQR_JEXTEN |
| marcozecchini | 0:9fca2b23d0ba | 1012 | | ADC_JSQR_JL |
| marcozecchini | 0:9fca2b23d0ba | 1013 | , |
| marcozecchini | 0:9fca2b23d0ba | 1014 | ADC_INJ_InitStruct->TriggerSource |
| marcozecchini | 0:9fca2b23d0ba | 1015 | | ADC_INJ_InitStruct->SequencerLength |
| marcozecchini | 0:9fca2b23d0ba | 1016 | ); |
| marcozecchini | 0:9fca2b23d0ba | 1017 | } |
| marcozecchini | 0:9fca2b23d0ba | 1018 | else |
| marcozecchini | 0:9fca2b23d0ba | 1019 | { |
| marcozecchini | 0:9fca2b23d0ba | 1020 | /* Initialization error: ADC instance is not disabled. */ |
| marcozecchini | 0:9fca2b23d0ba | 1021 | status = ERROR; |
| marcozecchini | 0:9fca2b23d0ba | 1022 | } |
| marcozecchini | 0:9fca2b23d0ba | 1023 | return status; |
| marcozecchini | 0:9fca2b23d0ba | 1024 | } |
| marcozecchini | 0:9fca2b23d0ba | 1025 | |
| marcozecchini | 0:9fca2b23d0ba | 1026 | /** |
| marcozecchini | 0:9fca2b23d0ba | 1027 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
| marcozecchini | 0:9fca2b23d0ba | 1028 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
| marcozecchini | 0:9fca2b23d0ba | 1029 | * whose fields will be set to default values. |
| marcozecchini | 0:9fca2b23d0ba | 1030 | * @retval None |
| marcozecchini | 0:9fca2b23d0ba | 1031 | */ |
| marcozecchini | 0:9fca2b23d0ba | 1032 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
| marcozecchini | 0:9fca2b23d0ba | 1033 | { |
| marcozecchini | 0:9fca2b23d0ba | 1034 | /* Set ADC_INJ_InitStruct fields to default values */ |
| marcozecchini | 0:9fca2b23d0ba | 1035 | /* Set fields of ADC group injected */ |
| marcozecchini | 0:9fca2b23d0ba | 1036 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
| marcozecchini | 0:9fca2b23d0ba | 1037 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
| marcozecchini | 0:9fca2b23d0ba | 1038 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
| marcozecchini | 0:9fca2b23d0ba | 1039 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
| marcozecchini | 0:9fca2b23d0ba | 1040 | } |
| marcozecchini | 0:9fca2b23d0ba | 1041 | |
| marcozecchini | 0:9fca2b23d0ba | 1042 | /** |
| marcozecchini | 0:9fca2b23d0ba | 1043 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 1044 | */ |
| marcozecchini | 0:9fca2b23d0ba | 1045 | |
| marcozecchini | 0:9fca2b23d0ba | 1046 | /** |
| marcozecchini | 0:9fca2b23d0ba | 1047 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 1048 | */ |
| marcozecchini | 0:9fca2b23d0ba | 1049 | |
| marcozecchini | 0:9fca2b23d0ba | 1050 | /** |
| marcozecchini | 0:9fca2b23d0ba | 1051 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 1052 | */ |
| marcozecchini | 0:9fca2b23d0ba | 1053 | |
| marcozecchini | 0:9fca2b23d0ba | 1054 | #endif /* ADC1 || ADC2 || ADC3 */ |
| marcozecchini | 0:9fca2b23d0ba | 1055 | |
| marcozecchini | 0:9fca2b23d0ba | 1056 | /** |
| marcozecchini | 0:9fca2b23d0ba | 1057 | * @} |
| marcozecchini | 0:9fca2b23d0ba | 1058 | */ |
| marcozecchini | 0:9fca2b23d0ba | 1059 | |
| marcozecchini | 0:9fca2b23d0ba | 1060 | #endif /* USE_FULL_LL_DRIVER */ |
| marcozecchini | 0:9fca2b23d0ba | 1061 | |
| marcozecchini | 0:9fca2b23d0ba | 1062 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |