Manh Pham / Mbed OS Nucleo_rtos_basic_ir_controller

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mbed-os/targets/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c@0:c8673aa96267, 2018-04-07 (annotated)

Committer:
manhpham
Date:
Sat Apr 07 09:22:54 2018 +0000
Revision:
0:c8673aa96267
Nucleo_rtos_basic_ir_controller

Who changed what in which revision?

UserRevisionLine numberNew contents of line
manhpham 0:c8673aa96267 1 /* mbed Microcontroller Library
manhpham 0:c8673aa96267 2 * Copyright (c) 2006-2013 ARM Limited
manhpham 0:c8673aa96267 3 *
manhpham 0:c8673aa96267 4 * Licensed under the Apache License, Version 2.0 (the "License");
manhpham 0:c8673aa96267 5 * you may not use this file except in compliance with the License.
manhpham 0:c8673aa96267 6 * You may obtain a copy of the License at
manhpham 0:c8673aa96267 7 *
manhpham 0:c8673aa96267 8 * http://www.apache.org/licenses/LICENSE-2.0
manhpham 0:c8673aa96267 9 *
manhpham 0:c8673aa96267 10 * Unless required by applicable law or agreed to in writing, software
manhpham 0:c8673aa96267 11 * distributed under the License is distributed on an "AS IS" BASIS,
manhpham 0:c8673aa96267 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
manhpham 0:c8673aa96267 13 * See the License for the specific language governing permissions and
manhpham 0:c8673aa96267 14 * limitations under the License.
manhpham 0:c8673aa96267 15 */
manhpham 0:c8673aa96267 16 #include <stddef.h>
manhpham 0:c8673aa96267 17
manhpham 0:c8673aa96267 18 #include "cmsis.h"
manhpham 0:c8673aa96267 19 #include "gpio_irq_api.h"
manhpham 0:c8673aa96267 20 #include "mbed_error.h"
manhpham 0:c8673aa96267 21
manhpham 0:c8673aa96267 22 #if DEVICE_INTERRUPTIN
manhpham 0:c8673aa96267 23
manhpham 0:c8673aa96267 24 #define CHANNEL_NUM 8
manhpham 0:c8673aa96267 25 #define LPC_GPIO_X LPC_PIN_INT
manhpham 0:c8673aa96267 26 #define PININT_IRQ PIN_INT0_IRQn
manhpham 0:c8673aa96267 27
manhpham 0:c8673aa96267 28 static uint32_t channel_ids[CHANNEL_NUM] = {0};
manhpham 0:c8673aa96267 29 static gpio_irq_handler irq_handler;
manhpham 0:c8673aa96267 30
manhpham 0:c8673aa96267 31 static inline void handle_interrupt_in(uint32_t channel)
manhpham 0:c8673aa96267 32 {
manhpham 0:c8673aa96267 33 uint32_t ch_bit = (1 << channel);
manhpham 0:c8673aa96267 34 // Return immediately if:
manhpham 0:c8673aa96267 35 // * The interrupt was already served
manhpham 0:c8673aa96267 36 // * There is no user handler
manhpham 0:c8673aa96267 37 // * It is a level interrupt, not an edge interrupt
manhpham 0:c8673aa96267 38 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
manhpham 0:c8673aa96267 39 (channel_ids[channel] == 0 ) ||
manhpham 0:c8673aa96267 40 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
manhpham 0:c8673aa96267 41
manhpham 0:c8673aa96267 42 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
manhpham 0:c8673aa96267 43 irq_handler(channel_ids[channel], IRQ_RISE);
manhpham 0:c8673aa96267 44 LPC_GPIO_X->RISE = ch_bit;
manhpham 0:c8673aa96267 45 }
manhpham 0:c8673aa96267 46 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
manhpham 0:c8673aa96267 47 irq_handler(channel_ids[channel], IRQ_FALL);
manhpham 0:c8673aa96267 48 }
manhpham 0:c8673aa96267 49 LPC_GPIO_X->IST = ch_bit;
manhpham 0:c8673aa96267 50 }
manhpham 0:c8673aa96267 51
manhpham 0:c8673aa96267 52 void gpio_irq0(void) {handle_interrupt_in(0);}
manhpham 0:c8673aa96267 53 void gpio_irq1(void) {handle_interrupt_in(1);}
manhpham 0:c8673aa96267 54 void gpio_irq2(void) {handle_interrupt_in(2);}
manhpham 0:c8673aa96267 55 void gpio_irq3(void) {handle_interrupt_in(3);}
manhpham 0:c8673aa96267 56 void gpio_irq4(void) {handle_interrupt_in(4);}
manhpham 0:c8673aa96267 57 void gpio_irq5(void) {handle_interrupt_in(5);}
manhpham 0:c8673aa96267 58 void gpio_irq6(void) {handle_interrupt_in(6);}
manhpham 0:c8673aa96267 59 void gpio_irq7(void) {handle_interrupt_in(7);}
manhpham 0:c8673aa96267 60
manhpham 0:c8673aa96267 61 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
manhpham 0:c8673aa96267 62 {
manhpham 0:c8673aa96267 63 if (pin == NC) return -1;
manhpham 0:c8673aa96267 64
manhpham 0:c8673aa96267 65 irq_handler = handler;
manhpham 0:c8673aa96267 66
manhpham 0:c8673aa96267 67 int found_free_channel = 0;
manhpham 0:c8673aa96267 68 int i = 0;
manhpham 0:c8673aa96267 69 for (i=0; i<CHANNEL_NUM; i++) {
manhpham 0:c8673aa96267 70 if (channel_ids[i] == 0) {
manhpham 0:c8673aa96267 71 channel_ids[i] = id;
manhpham 0:c8673aa96267 72 obj->ch = i;
manhpham 0:c8673aa96267 73 found_free_channel = 1;
manhpham 0:c8673aa96267 74 break;
manhpham 0:c8673aa96267 75 }
manhpham 0:c8673aa96267 76 }
manhpham 0:c8673aa96267 77 if (!found_free_channel) return -1;
manhpham 0:c8673aa96267 78
manhpham 0:c8673aa96267 79 /* Enable AHB clock to the GPIO domain. */
manhpham 0:c8673aa96267 80 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
manhpham 0:c8673aa96267 81
manhpham 0:c8673aa96267 82 LPC_SYSCON->PINTSEL[obj->ch] = (pin >> PIN_SHIFT);
manhpham 0:c8673aa96267 83
manhpham 0:c8673aa96267 84 // Interrupt Wake-Up Enable
manhpham 0:c8673aa96267 85 LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
manhpham 0:c8673aa96267 86
manhpham 0:c8673aa96267 87 void (*channels_irq)(void) = NULL;
manhpham 0:c8673aa96267 88 switch (obj->ch) {
manhpham 0:c8673aa96267 89 case 0: channels_irq = &gpio_irq0; break;
manhpham 0:c8673aa96267 90 case 1: channels_irq = &gpio_irq1; break;
manhpham 0:c8673aa96267 91 case 2: channels_irq = &gpio_irq2; break;
manhpham 0:c8673aa96267 92 case 3: channels_irq = &gpio_irq3; break;
manhpham 0:c8673aa96267 93 case 4: channels_irq = &gpio_irq4; break;
manhpham 0:c8673aa96267 94 case 5: channels_irq = &gpio_irq5; break;
manhpham 0:c8673aa96267 95 case 6: channels_irq = &gpio_irq6; break;
manhpham 0:c8673aa96267 96 case 7: channels_irq = &gpio_irq7; break;
manhpham 0:c8673aa96267 97 }
manhpham 0:c8673aa96267 98 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
manhpham 0:c8673aa96267 99 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
manhpham 0:c8673aa96267 100
manhpham 0:c8673aa96267 101 return 0;
manhpham 0:c8673aa96267 102 }
manhpham 0:c8673aa96267 103
manhpham 0:c8673aa96267 104 void gpio_irq_free(gpio_irq_t *obj)
manhpham 0:c8673aa96267 105 {
manhpham 0:c8673aa96267 106 channel_ids[obj->ch] = 0;
manhpham 0:c8673aa96267 107 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
manhpham 0:c8673aa96267 108 }
manhpham 0:c8673aa96267 109
manhpham 0:c8673aa96267 110 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
manhpham 0:c8673aa96267 111 {
manhpham 0:c8673aa96267 112 unsigned int ch_bit = (1 << obj->ch);
manhpham 0:c8673aa96267 113
manhpham 0:c8673aa96267 114 // Clear interrupt
manhpham 0:c8673aa96267 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
manhpham 0:c8673aa96267 116 LPC_GPIO_X->IST = ch_bit;
manhpham 0:c8673aa96267 117
manhpham 0:c8673aa96267 118 // Edge trigger
manhpham 0:c8673aa96267 119 LPC_GPIO_X->ISEL &= ~ch_bit;
manhpham 0:c8673aa96267 120 if (event == IRQ_RISE) {
manhpham 0:c8673aa96267 121 if (enable) {
manhpham 0:c8673aa96267 122 LPC_GPIO_X->IENR |= ch_bit;
manhpham 0:c8673aa96267 123 } else {
manhpham 0:c8673aa96267 124 LPC_GPIO_X->IENR &= ~ch_bit;
manhpham 0:c8673aa96267 125 }
manhpham 0:c8673aa96267 126 } else {
manhpham 0:c8673aa96267 127 if (enable) {
manhpham 0:c8673aa96267 128 LPC_GPIO_X->IENF |= ch_bit;
manhpham 0:c8673aa96267 129 } else {
manhpham 0:c8673aa96267 130 LPC_GPIO_X->IENF &= ~ch_bit;
manhpham 0:c8673aa96267 131 }
manhpham 0:c8673aa96267 132 }
manhpham 0:c8673aa96267 133 }
manhpham 0:c8673aa96267 134
manhpham 0:c8673aa96267 135 void gpio_irq_enable(gpio_irq_t *obj)
manhpham 0:c8673aa96267 136 {
manhpham 0:c8673aa96267 137 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
manhpham 0:c8673aa96267 138 }
manhpham 0:c8673aa96267 139
manhpham 0:c8673aa96267 140 void gpio_irq_disable(gpio_irq_t *obj)
manhpham 0:c8673aa96267 141 {
manhpham 0:c8673aa96267 142 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
manhpham 0:c8673aa96267 143 }
manhpham 0:c8673aa96267 144
manhpham 0:c8673aa96267 145 #endif