Manh Pham / Mbed OS Nucleo_rtos_basic_ir_controller

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

mbed-os/targets/TARGET_Maxim/TARGET_MAX32620/device/system_max32620.c@0:c8673aa96267, 2018-04-07 (annotated)

Committer:
manhpham
Date:
Sat Apr 07 09:22:54 2018 +0000
Revision:
0:c8673aa96267
Nucleo_rtos_basic_ir_controller

Who changed what in which revision?

UserRevisionLine numberNew contents of line
manhpham 0:c8673aa96267 1 /*******************************************************************************
manhpham 0:c8673aa96267 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
manhpham 0:c8673aa96267 3 *
manhpham 0:c8673aa96267 4 * Permission is hereby granted, free of charge, to any person obtaining a
manhpham 0:c8673aa96267 5 * copy of this software and associated documentation files (the "Software"),
manhpham 0:c8673aa96267 6 * to deal in the Software without restriction, including without limitation
manhpham 0:c8673aa96267 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
manhpham 0:c8673aa96267 8 * and/or sell copies of the Software, and to permit persons to whom the
manhpham 0:c8673aa96267 9 * Software is furnished to do so, subject to the following conditions:
manhpham 0:c8673aa96267 10 *
manhpham 0:c8673aa96267 11 * The above copyright notice and this permission notice shall be included
manhpham 0:c8673aa96267 12 * in all copies or substantial portions of the Software.
manhpham 0:c8673aa96267 13 *
manhpham 0:c8673aa96267 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
manhpham 0:c8673aa96267 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
manhpham 0:c8673aa96267 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
manhpham 0:c8673aa96267 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
manhpham 0:c8673aa96267 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
manhpham 0:c8673aa96267 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
manhpham 0:c8673aa96267 20 * OTHER DEALINGS IN THE SOFTWARE.
manhpham 0:c8673aa96267 21 *
manhpham 0:c8673aa96267 22 * Except as contained in this notice, the name of Maxim Integrated
manhpham 0:c8673aa96267 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
manhpham 0:c8673aa96267 24 * Products, Inc. Branding Policy.
manhpham 0:c8673aa96267 25 *
manhpham 0:c8673aa96267 26 * The mere transfer of this software does not imply any licenses
manhpham 0:c8673aa96267 27 * of trade secrets, proprietary technology, copyrights, patents,
manhpham 0:c8673aa96267 28 * trademarks, maskwork rights, or any other form of intellectual
manhpham 0:c8673aa96267 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
manhpham 0:c8673aa96267 30 * ownership rights.
manhpham 0:c8673aa96267 31 *******************************************************************************
manhpham 0:c8673aa96267 32 */
manhpham 0:c8673aa96267 33
manhpham 0:c8673aa96267 34 #include "max32620.h"
manhpham 0:c8673aa96267 35 #include "clkman_regs.h"
manhpham 0:c8673aa96267 36 #include "icc_regs.h"
manhpham 0:c8673aa96267 37 #include "pwrseq_regs.h"
manhpham 0:c8673aa96267 38 #include "pwrman_regs.h"
manhpham 0:c8673aa96267 39 #include "adc_regs.h"
manhpham 0:c8673aa96267 40 #include "flc_regs.h"
manhpham 0:c8673aa96267 41 #include "trim_regs.h"
manhpham 0:c8673aa96267 42 #include "rtc_regs.h"
manhpham 0:c8673aa96267 43
manhpham 0:c8673aa96267 44 /* SCB CPACR Register Definitions */
manhpham 0:c8673aa96267 45 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
manhpham 0:c8673aa96267 46 #define SCB_CPACR_CP10_Pos 20 /* SCB CPACR: Coprocessor 10 Position */
manhpham 0:c8673aa96267 47 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /* SCB CPACR: Coprocessor 10 Mask */
manhpham 0:c8673aa96267 48 #define SCB_CPACR_CP11_Pos 22 /* SCB CPACR: Coprocessor 11 Position */
manhpham 0:c8673aa96267 49 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /* SCB CPACR: Coprocessor 11 Mask */
manhpham 0:c8673aa96267 50
manhpham 0:c8673aa96267 51 static uint8_t running;
manhpham 0:c8673aa96267 52
manhpham 0:c8673aa96267 53 // NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will
manhpham 0:c8673aa96267 54 // be AFTER SystemInit() runs. This is required so the hal drivers will have
manhpham 0:c8673aa96267 55 // the correct value when the DATA sections are initialized.
manhpham 0:c8673aa96267 56 uint32_t SystemCoreClock = RO_FREQ / 2;
manhpham 0:c8673aa96267 57
manhpham 0:c8673aa96267 58 void SystemCoreClockUpdate(void)
manhpham 0:c8673aa96267 59 {
manhpham 0:c8673aa96267 60 switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
manhpham 0:c8673aa96267 61
manhpham 0:c8673aa96267 62 case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2:
manhpham 0:c8673aa96267 63 default:
manhpham 0:c8673aa96267 64 SystemCoreClock = RO_FREQ / 2;
manhpham 0:c8673aa96267 65 break;
manhpham 0:c8673aa96267 66 case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO:
manhpham 0:c8673aa96267 67 SystemCoreClock = RO_FREQ;
manhpham 0:c8673aa96267 68 break;
manhpham 0:c8673aa96267 69 }
manhpham 0:c8673aa96267 70 }
manhpham 0:c8673aa96267 71
manhpham 0:c8673aa96267 72 void Trim_ROAtomic(void)
manhpham 0:c8673aa96267 73 {
manhpham 0:c8673aa96267 74 uint32_t trim;
manhpham 0:c8673aa96267 75
manhpham 0:c8673aa96267 76 // Step 1: enable 32KHz RTC
manhpham 0:c8673aa96267 77 running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
manhpham 0:c8673aa96267 78 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
manhpham 0:c8673aa96267 79
manhpham 0:c8673aa96267 80 // Step 2: enable RO calibration complete interrupt
manhpham 0:c8673aa96267 81 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IE;
manhpham 0:c8673aa96267 82
manhpham 0:c8673aa96267 83 // Step 3: clear RO calibration complete interrupt
manhpham 0:c8673aa96267 84 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IF;
manhpham 0:c8673aa96267 85
manhpham 0:c8673aa96267 86 /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
manhpham 0:c8673aa96267 87
manhpham 0:c8673aa96267 88 /* Step 5: write initial trim to frequency calibration initial condition register */
manhpham 0:c8673aa96267 89 trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
manhpham 0:c8673aa96267 90 MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
manhpham 0:c8673aa96267 91 ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
manhpham 0:c8673aa96267 92
manhpham 0:c8673aa96267 93 // Step 6: load initial trim to active frequency trim register
manhpham 0:c8673aa96267 94 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
manhpham 0:c8673aa96267 95
manhpham 0:c8673aa96267 96 // Step 7: enable frequency loop to control RO trim
manhpham 0:c8673aa96267 97 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
manhpham 0:c8673aa96267 98
manhpham 0:c8673aa96267 99 // Step 8: run frequency calibration in atomic mode
manhpham 0:c8673aa96267 100 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
manhpham 0:c8673aa96267 101
manhpham 0:c8673aa96267 102 // Step 9: waiting for ro_cal_done flag
manhpham 0:c8673aa96267 103 while (!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
manhpham 0:c8673aa96267 104
manhpham 0:c8673aa96267 105 // Step 10: stop frequency calibration
manhpham 0:c8673aa96267 106 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
manhpham 0:c8673aa96267 107
manhpham 0:c8673aa96267 108 // Step 11: disable RO calibration complete interrupt
manhpham 0:c8673aa96267 109 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) & ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
manhpham 0:c8673aa96267 110
manhpham 0:c8673aa96267 111 // Step 12: read final frequency trim value
manhpham 0:c8673aa96267 112 trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
manhpham 0:c8673aa96267 113
manhpham 0:c8673aa96267 114 /* Step 13: write final trim to RO flash trim shadow register */
manhpham 0:c8673aa96267 115 MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
manhpham 0:c8673aa96267 116 ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
manhpham 0:c8673aa96267 117
manhpham 0:c8673aa96267 118 // Step 14: restore RTC status
manhpham 0:c8673aa96267 119 if (!running) {
manhpham 0:c8673aa96267 120 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
manhpham 0:c8673aa96267 121 }
manhpham 0:c8673aa96267 122
manhpham 0:c8673aa96267 123 // Step 15: disable frequency loop to control RO trim
manhpham 0:c8673aa96267 124 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
manhpham 0:c8673aa96267 125 }
manhpham 0:c8673aa96267 126
manhpham 0:c8673aa96267 127 static void ICC_Enable(void)
manhpham 0:c8673aa96267 128 {
manhpham 0:c8673aa96267 129 /* Invalidate cache and wait until ready */
manhpham 0:c8673aa96267 130 MXC_ICC->invdt_all = 1;
manhpham 0:c8673aa96267 131 while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
manhpham 0:c8673aa96267 132
manhpham 0:c8673aa96267 133 /* Enable cache */
manhpham 0:c8673aa96267 134 MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
manhpham 0:c8673aa96267 135
manhpham 0:c8673aa96267 136 /* Must invalidate a second time for proper use */
manhpham 0:c8673aa96267 137 MXC_ICC->invdt_all = 1;
manhpham 0:c8673aa96267 138 }
manhpham 0:c8673aa96267 139
manhpham 0:c8673aa96267 140 // This function to be implemented by the hal
manhpham 0:c8673aa96267 141 extern void low_level_init(void);
manhpham 0:c8673aa96267 142
manhpham 0:c8673aa96267 143 // Note: This is called before C run-time initialization. Do not use any initialized variables.
manhpham 0:c8673aa96267 144 void SystemInit(void)
manhpham 0:c8673aa96267 145 {
manhpham 0:c8673aa96267 146 ICC_Enable();
manhpham 0:c8673aa96267 147
manhpham 0:c8673aa96267 148 low_level_init();
manhpham 0:c8673aa96267 149
manhpham 0:c8673aa96267 150 // Select 48MHz ring oscillator as clock source
manhpham 0:c8673aa96267 151 uint32_t reg = MXC_CLKMAN->clk_ctrl;
manhpham 0:c8673aa96267 152 reg &= ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT;
manhpham 0:c8673aa96267 153 MXC_CLKMAN->clk_ctrl = reg;
manhpham 0:c8673aa96267 154
manhpham 0:c8673aa96267 155 // Copy trim information from shadow registers into power manager registers
manhpham 0:c8673aa96267 156 // NOTE: Checks have been added to prevent bad/missing trim values from being loaded
manhpham 0:c8673aa96267 157 if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
manhpham 0:c8673aa96267 158 (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
manhpham 0:c8673aa96267 159 (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
manhpham 0:c8673aa96267 160 MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
manhpham 0:c8673aa96267 161 MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
manhpham 0:c8673aa96267 162 } else {
manhpham 0:c8673aa96267 163 /* No valid info block, use some reasonable defaults */
manhpham 0:c8673aa96267 164 MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
manhpham 0:c8673aa96267 165 MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
manhpham 0:c8673aa96267 166 }
manhpham 0:c8673aa96267 167
manhpham 0:c8673aa96267 168 // Use ASYNC flags, and ASYNC Reset of flags to improve synchronization speed
manhpham 0:c8673aa96267 169 // between RTC and ARM core. Also avoid delayed RTC interrupts after lp wake.
manhpham 0:c8673aa96267 170 MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS | MXC_F_RTC_CTRL_AGGRESSIVE_RST);
manhpham 0:c8673aa96267 171
manhpham 0:c8673aa96267 172 /* Clear the GPIO WUD event if not waking up from LP0 */
manhpham 0:c8673aa96267 173 /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
manhpham 0:c8673aa96267 174 if (MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT || !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
manhpham 0:c8673aa96267 175 /* Clear GPIO WUD event and configuration registers, globally */
manhpham 0:c8673aa96267 176 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
manhpham 0:c8673aa96267 177 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
manhpham 0:c8673aa96267 178 } else {
manhpham 0:c8673aa96267 179 /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
manhpham 0:c8673aa96267 180 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
manhpham 0:c8673aa96267 181 }
manhpham 0:c8673aa96267 182
manhpham 0:c8673aa96267 183 // Turn on retention regulator
manhpham 0:c8673aa96267 184 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
manhpham 0:c8673aa96267 185
manhpham 0:c8673aa96267 186 // Clear all unused wakeup sources
manhpham 0:c8673aa96267 187 // Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals
manhpham 0:c8673aa96267 188 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
manhpham 0:c8673aa96267 189 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
manhpham 0:c8673aa96267 190
manhpham 0:c8673aa96267 191 // RTC sources are inverted, so a 1 will disable them
manhpham 0:c8673aa96267 192 MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
manhpham 0:c8673aa96267 193 MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
manhpham 0:c8673aa96267 194
manhpham 0:c8673aa96267 195 /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
manhpham 0:c8673aa96267 196 MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
manhpham 0:c8673aa96267 197
manhpham 0:c8673aa96267 198 // Enable real-time clock during sleep mode
manhpham 0:c8673aa96267 199 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
manhpham 0:c8673aa96267 200
manhpham 0:c8673aa96267 201 #if (__FPU_PRESENT == 1)
manhpham 0:c8673aa96267 202 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
manhpham 0:c8673aa96267 203 /* Grant full access, per "Table B3-24 CPACR bit assignments". */
manhpham 0:c8673aa96267 204 /* DDI0403D "ARMv7-M Architecture Reference Manual" */
manhpham 0:c8673aa96267 205 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
manhpham 0:c8673aa96267 206 __DSB();
manhpham 0:c8673aa96267 207 __ISB();
manhpham 0:c8673aa96267 208 #endif
manhpham 0:c8673aa96267 209
manhpham 0:c8673aa96267 210 // Trim ring oscillator
manhpham 0:c8673aa96267 211 Trim_ROAtomic();
manhpham 0:c8673aa96267 212 }