Manh Pham / Mbed OS Nucleo_rtos_basic_ir_controller

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mbed-os/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c@0:c8673aa96267, 2018-04-07 (annotated)

Committer:
manhpham
Date:
Sat Apr 07 09:22:54 2018 +0000
Revision:
0:c8673aa96267
Nucleo_rtos_basic_ir_controller

Who changed what in which revision?

UserRevisionLine numberNew contents of line
manhpham 0:c8673aa96267 1 /* mbed Microcontroller Library
manhpham 0:c8673aa96267 2 * Copyright (c) 2013 ARM Limited
manhpham 0:c8673aa96267 3 *
manhpham 0:c8673aa96267 4 * Licensed under the Apache License, Version 2.0 (the "License");
manhpham 0:c8673aa96267 5 * you may not use this file except in compliance with the License.
manhpham 0:c8673aa96267 6 * You may obtain a copy of the License at
manhpham 0:c8673aa96267 7 *
manhpham 0:c8673aa96267 8 * http://www.apache.org/licenses/LICENSE-2.0
manhpham 0:c8673aa96267 9 *
manhpham 0:c8673aa96267 10 * Unless required by applicable law or agreed to in writing, software
manhpham 0:c8673aa96267 11 * distributed under the License is distributed on an "AS IS" BASIS,
manhpham 0:c8673aa96267 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
manhpham 0:c8673aa96267 13 * See the License for the specific language governing permissions and
manhpham 0:c8673aa96267 14 * limitations under the License.
manhpham 0:c8673aa96267 15 */
manhpham 0:c8673aa96267 16 #include <math.h>
manhpham 0:c8673aa96267 17 #include "mbed_assert.h"
manhpham 0:c8673aa96267 18
manhpham 0:c8673aa96267 19 #include "spi_api.h"
manhpham 0:c8673aa96267 20
manhpham 0:c8673aa96267 21 #if DEVICE_SPI
manhpham 0:c8673aa96267 22
manhpham 0:c8673aa96267 23 #include "cmsis.h"
manhpham 0:c8673aa96267 24 #include "pinmap.h"
manhpham 0:c8673aa96267 25 #include "mbed_error.h"
manhpham 0:c8673aa96267 26 #include "fsl_dspi.h"
manhpham 0:c8673aa96267 27 #include "peripheral_clock_defines.h"
manhpham 0:c8673aa96267 28 #include "PeripheralPins.h"
manhpham 0:c8673aa96267 29
manhpham 0:c8673aa96267 30 /* Array of SPI peripheral base address. */
manhpham 0:c8673aa96267 31 static SPI_Type *const spi_address[] = SPI_BASE_PTRS;
manhpham 0:c8673aa96267 32 /* Array of SPI bus clock frequencies */
manhpham 0:c8673aa96267 33 static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS;
manhpham 0:c8673aa96267 34
manhpham 0:c8673aa96267 35 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
manhpham 0:c8673aa96267 36 {
manhpham 0:c8673aa96267 37 // determine the SPI to use
manhpham 0:c8673aa96267 38 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
manhpham 0:c8673aa96267 39 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
manhpham 0:c8673aa96267 40 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
manhpham 0:c8673aa96267 41 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
manhpham 0:c8673aa96267 42 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
manhpham 0:c8673aa96267 43 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
manhpham 0:c8673aa96267 44
manhpham 0:c8673aa96267 45 obj->instance = pinmap_merge(spi_data, spi_cntl);
manhpham 0:c8673aa96267 46 MBED_ASSERT((int)obj->instance != NC);
manhpham 0:c8673aa96267 47
manhpham 0:c8673aa96267 48 // pin out the spi pins
manhpham 0:c8673aa96267 49 pinmap_pinout(mosi, PinMap_SPI_MOSI);
manhpham 0:c8673aa96267 50 pinmap_pinout(miso, PinMap_SPI_MISO);
manhpham 0:c8673aa96267 51 pinmap_pinout(sclk, PinMap_SPI_SCLK);
manhpham 0:c8673aa96267 52 if (ssel != NC) {
manhpham 0:c8673aa96267 53 pinmap_pinout(ssel, PinMap_SPI_SSEL);
manhpham 0:c8673aa96267 54 }
manhpham 0:c8673aa96267 55 }
manhpham 0:c8673aa96267 56
manhpham 0:c8673aa96267 57 void spi_free(spi_t *obj)
manhpham 0:c8673aa96267 58 {
manhpham 0:c8673aa96267 59 DSPI_Deinit(spi_address[obj->instance]);
manhpham 0:c8673aa96267 60 }
manhpham 0:c8673aa96267 61
manhpham 0:c8673aa96267 62 void spi_format(spi_t *obj, int bits, int mode, int slave)
manhpham 0:c8673aa96267 63 {
manhpham 0:c8673aa96267 64 dspi_master_config_t master_config;
manhpham 0:c8673aa96267 65 dspi_slave_config_t slave_config;
manhpham 0:c8673aa96267 66
manhpham 0:c8673aa96267 67 if (slave) {
manhpham 0:c8673aa96267 68 /* Slave config */
manhpham 0:c8673aa96267 69 DSPI_SlaveGetDefaultConfig(&slave_config);
manhpham 0:c8673aa96267 70 slave_config.whichCtar = kDSPI_Ctar0;
manhpham 0:c8673aa96267 71 slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;;
manhpham 0:c8673aa96267 72 slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
manhpham 0:c8673aa96267 73 slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
manhpham 0:c8673aa96267 74
manhpham 0:c8673aa96267 75 DSPI_SlaveInit(spi_address[obj->instance], &slave_config);
manhpham 0:c8673aa96267 76 } else {
manhpham 0:c8673aa96267 77 /* Master config */
manhpham 0:c8673aa96267 78 DSPI_MasterGetDefaultConfig(&master_config);
manhpham 0:c8673aa96267 79 master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;;
manhpham 0:c8673aa96267 80 master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
manhpham 0:c8673aa96267 81 master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
manhpham 0:c8673aa96267 82 master_config.ctarConfig.direction = kDSPI_MsbFirst;
manhpham 0:c8673aa96267 83 master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
manhpham 0:c8673aa96267 84
manhpham 0:c8673aa96267 85 DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
manhpham 0:c8673aa96267 86 }
manhpham 0:c8673aa96267 87 }
manhpham 0:c8673aa96267 88
manhpham 0:c8673aa96267 89 void spi_frequency(spi_t *obj, int hz)
manhpham 0:c8673aa96267 90 {
manhpham 0:c8673aa96267 91 uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->instance]);
manhpham 0:c8673aa96267 92 DSPI_MasterSetBaudRate(spi_address[obj->instance], kDSPI_Ctar0, (uint32_t)hz, busClock);
manhpham 0:c8673aa96267 93 //Half clock period delay after SPI transfer
manhpham 0:c8673aa96267 94 DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
manhpham 0:c8673aa96267 95 }
manhpham 0:c8673aa96267 96
manhpham 0:c8673aa96267 97 static inline int spi_readable(spi_t * obj)
manhpham 0:c8673aa96267 98 {
manhpham 0:c8673aa96267 99 return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
manhpham 0:c8673aa96267 100 }
manhpham 0:c8673aa96267 101
manhpham 0:c8673aa96267 102 int spi_master_write(spi_t *obj, int value)
manhpham 0:c8673aa96267 103 {
manhpham 0:c8673aa96267 104 dspi_command_data_config_t command;
manhpham 0:c8673aa96267 105 uint32_t rx_data;
manhpham 0:c8673aa96267 106 DSPI_GetDefaultDataCommandConfig(&command);
manhpham 0:c8673aa96267 107 command.isEndOfQueue = true;
manhpham 0:c8673aa96267 108
manhpham 0:c8673aa96267 109 DSPI_MasterWriteDataBlocking(spi_address[obj->instance], &command, (uint16_t)value);
manhpham 0:c8673aa96267 110
manhpham 0:c8673aa96267 111 DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_TxFifoFillRequestFlag);
manhpham 0:c8673aa96267 112
manhpham 0:c8673aa96267 113 // wait rx buffer full
manhpham 0:c8673aa96267 114 while (!spi_readable(obj));
manhpham 0:c8673aa96267 115 rx_data = DSPI_ReadData(spi_address[obj->instance]);
manhpham 0:c8673aa96267 116 DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
manhpham 0:c8673aa96267 117 return rx_data & 0xffff;
manhpham 0:c8673aa96267 118 }
manhpham 0:c8673aa96267 119
manhpham 0:c8673aa96267 120 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
manhpham 0:c8673aa96267 121 char *rx_buffer, int rx_length, char write_fill) {
manhpham 0:c8673aa96267 122 int total = (tx_length > rx_length) ? tx_length : rx_length;
manhpham 0:c8673aa96267 123
manhpham 0:c8673aa96267 124 for (int i = 0; i < total; i++) {
manhpham 0:c8673aa96267 125 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
manhpham 0:c8673aa96267 126 char in = spi_master_write(obj, out);
manhpham 0:c8673aa96267 127 if (i < rx_length) {
manhpham 0:c8673aa96267 128 rx_buffer[i] = in;
manhpham 0:c8673aa96267 129 }
manhpham 0:c8673aa96267 130 }
manhpham 0:c8673aa96267 131
manhpham 0:c8673aa96267 132 return total;
manhpham 0:c8673aa96267 133 }
manhpham 0:c8673aa96267 134
manhpham 0:c8673aa96267 135 int spi_slave_receive(spi_t *obj)
manhpham 0:c8673aa96267 136 {
manhpham 0:c8673aa96267 137 return spi_readable(obj);
manhpham 0:c8673aa96267 138 }
manhpham 0:c8673aa96267 139
manhpham 0:c8673aa96267 140 int spi_slave_read(spi_t *obj)
manhpham 0:c8673aa96267 141 {
manhpham 0:c8673aa96267 142 uint32_t rx_data;
manhpham 0:c8673aa96267 143
manhpham 0:c8673aa96267 144 while (!spi_readable(obj));
manhpham 0:c8673aa96267 145 rx_data = DSPI_ReadData(spi_address[obj->instance]);
manhpham 0:c8673aa96267 146 DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag);
manhpham 0:c8673aa96267 147 return rx_data & 0xffff;
manhpham 0:c8673aa96267 148 }
manhpham 0:c8673aa96267 149
manhpham 0:c8673aa96267 150 void spi_slave_write(spi_t *obj, int value)
manhpham 0:c8673aa96267 151 {
manhpham 0:c8673aa96267 152 DSPI_SlaveWriteDataBlocking(spi_address[obj->instance], (uint32_t)value);
manhpham 0:c8673aa96267 153 }
manhpham 0:c8673aa96267 154
manhpham 0:c8673aa96267 155 #endif