João Victor / stm32f4-discovery-CAN-Activation

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_adc.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief This file provides firmware functions to manage the following
<> 149:156823d33999 8 * functionalities of the Analog to Digital Convertor (ADC)
<> 149:156823d33999 9 * peripheral:
<> 149:156823d33999 10 * + Initialization and de-initialization functions
<> 149:156823d33999 11 * ++ Initialization and Configuration of ADC
<> 149:156823d33999 12 * + Operation functions
<> 149:156823d33999 13 * ++ Start, stop, get result of conversions of regular
<> 149:156823d33999 14 * group, using 3 possible modes: polling, interruption or DMA.
<> 149:156823d33999 15 * + Control functions
<> 149:156823d33999 16 * ++ Channels configuration on regular group
<> 149:156823d33999 17 * ++ Channels configuration on injected group
<> 149:156823d33999 18 * ++ Analog Watchdog configuration
<> 149:156823d33999 19 * + State functions
<> 149:156823d33999 20 * ++ ADC state machine management
<> 149:156823d33999 21 * ++ Interrupts and flags management
<> 149:156823d33999 22 * Other functions (extended functions) are available in file
<> 149:156823d33999 23 * "stm32l1xx_hal_adc_ex.c".
<> 149:156823d33999 24 *
<> 149:156823d33999 25 @verbatim
<> 149:156823d33999 26 ==============================================================================
<> 149:156823d33999 27 ##### ADC peripheral features #####
<> 149:156823d33999 28 ==============================================================================
<> 149:156823d33999 29 [..]
<> 149:156823d33999 30 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
<> 149:156823d33999 31
<> 149:156823d33999 32 (+) Interrupt generation at the end of regular conversion, end of injected
<> 149:156823d33999 33 conversion, and in case of analog watchdog or overrun events.
<> 149:156823d33999 34
<> 149:156823d33999 35 (+) Single and continuous conversion modes.
<> 149:156823d33999 36
<> 149:156823d33999 37 (+) Scan mode for conversion of several channels sequentially.
<> 149:156823d33999 38
<> 149:156823d33999 39 (+) Data alignment with in-built data coherency.
<> 149:156823d33999 40
<> 149:156823d33999 41 (+) Programmable sampling time (channel wise)
<> 149:156823d33999 42
<> 149:156823d33999 43 (+) ADC conversion of regular group and injected group.
<> 149:156823d33999 44
<> 149:156823d33999 45 (+) External trigger (timer or EXTI) with configurable polarity
<> 149:156823d33999 46 for both regular and injected groups.
<> 149:156823d33999 47
<> 149:156823d33999 48 (+) DMA request generation for transfer of conversions data of regular group.
<> 149:156823d33999 49
<> 149:156823d33999 50 (+) ADC offset on injected channels
<> 149:156823d33999 51
<> 149:156823d33999 52 (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
<> 149:156823d33999 53 slower speed.
<> 149:156823d33999 54
<> 149:156823d33999 55 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
<> 149:156823d33999 56 Vdda or to an external voltage reference).
<> 149:156823d33999 57
<> 149:156823d33999 58
<> 149:156823d33999 59 ##### How to use this driver #####
<> 149:156823d33999 60 ==============================================================================
<> 149:156823d33999 61 [..]
<> 149:156823d33999 62
<> 149:156823d33999 63 *** Configuration of top level parameters related to ADC ***
<> 149:156823d33999 64 ============================================================
<> 149:156823d33999 65 [..]
<> 149:156823d33999 66
<> 149:156823d33999 67 (#) Enable the ADC interface
<> 149:156823d33999 68 (++) As prerequisite, ADC clock must be configured at RCC top level.
<> 149:156823d33999 69 Caution: On STM32L1, ADC clock frequency max is 16MHz (refer
<> 149:156823d33999 70 to device datasheet).
<> 149:156823d33999 71 Therefore, ADC clock prescaler must be configured in
<> 149:156823d33999 72 function of ADC clock source frequency to remain below
<> 149:156823d33999 73 this maximum frequency.
<> 149:156823d33999 74
<> 149:156823d33999 75 (++) Two clock settings are mandatory:
<> 149:156823d33999 76 (+++) ADC clock (core clock).
<> 149:156823d33999 77 (+++) ADC clock (conversions clock).
<> 149:156823d33999 78 Only one possible clock source: derived from HSI RC 16MHz oscillator
<> 149:156823d33999 79 (HSI).
<> 149:156823d33999 80 ADC is connected directly to HSI RC 16MHz oscillator.
<> 149:156823d33999 81 Therefore, RCC PLL setting has no impact on ADC.
<> 149:156823d33999 82 PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or
<> 149:156823d33999 83 enabled with HSI16 as clock source
<> 149:156823d33999 84 (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device
<> 149:156823d33999 85 main clock source SYSCLK.
<> 149:156823d33999 86 The only mandatory setting is ".HSIState = RCC_HSI_ON"
<> 149:156823d33999 87
<> 149:156823d33999 88 (+++) Example:
<> 149:156823d33999 89 Into HAL_ADC_MspInit() (recommended code location) or with
<> 149:156823d33999 90 other device clock parameters configuration:
<> 149:156823d33999 91 (+++) __HAL_RCC_ADC1_CLK_ENABLE();
<> 149:156823d33999 92
<> 149:156823d33999 93 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
<> 149:156823d33999 94 (+++) RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI);
<> 149:156823d33999 95 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_ON;
<> 149:156823d33999 96 (+++) RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
<> 149:156823d33999 97 (+++) RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
<> 149:156823d33999 98 (+++) RCC_OscInitStructure.PLL.PLLSource = ...
<> 149:156823d33999 99 (+++) RCC_OscInitStructure.PLL...
<> 149:156823d33999 100 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<> 149:156823d33999 101
<> 149:156823d33999 102 (++) ADC clock prescaler is configured at ADC level with
<> 149:156823d33999 103 parameter "ClockPrescaler" using function HAL_ADC_Init().
<> 149:156823d33999 104
<> 149:156823d33999 105 (#) ADC pins configuration
<> 149:156823d33999 106 (++) Enable the clock for the ADC GPIOs
<> 149:156823d33999 107 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
<> 149:156823d33999 108 (++) Configure these ADC pins in analog mode
<> 149:156823d33999 109 using function HAL_GPIO_Init()
<> 149:156823d33999 110
<> 149:156823d33999 111 (#) Optionally, in case of usage of ADC with interruptions:
<> 149:156823d33999 112 (++) Configure the NVIC for ADC
<> 149:156823d33999 113 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 149:156823d33999 114 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 149:156823d33999 115 into the function of corresponding ADC interruption vector
<> 149:156823d33999 116 ADCx_IRQHandler().
<> 149:156823d33999 117
<> 149:156823d33999 118 (#) Optionally, in case of usage of DMA:
<> 149:156823d33999 119 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
<> 149:156823d33999 120 using function HAL_DMA_Init().
<> 149:156823d33999 121 (++) Configure the NVIC for DMA
<> 149:156823d33999 122 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 149:156823d33999 123 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
<> 149:156823d33999 124 into the function of corresponding DMA interruption vector
<> 149:156823d33999 125 DMAx_Channelx_IRQHandler().
<> 149:156823d33999 126
<> 149:156823d33999 127 *** Configuration of ADC, groups regular/injected, channels parameters ***
<> 149:156823d33999 128 ==========================================================================
<> 149:156823d33999 129 [..]
<> 149:156823d33999 130
<> 149:156823d33999 131 (#) Configure the ADC parameters (resolution, data alignment, ...)
<> 149:156823d33999 132 and regular group parameters (conversion trigger, sequencer, ...)
<> 149:156823d33999 133 using function HAL_ADC_Init().
<> 149:156823d33999 134
<> 149:156823d33999 135 (#) Configure the channels for regular group parameters (channel number,
<> 149:156823d33999 136 channel rank into sequencer, ..., into regular group)
<> 149:156823d33999 137 using function HAL_ADC_ConfigChannel().
<> 149:156823d33999 138
<> 149:156823d33999 139 (#) Optionally, configure the injected group parameters (conversion trigger,
<> 149:156823d33999 140 sequencer, ..., of injected group)
<> 149:156823d33999 141 and the channels for injected group parameters (channel number,
<> 149:156823d33999 142 channel rank into sequencer, ..., into injected group)
<> 149:156823d33999 143 using function HAL_ADCEx_InjectedConfigChannel().
<> 149:156823d33999 144
<> 149:156823d33999 145 (#) Optionally, configure the analog watchdog parameters (channels
<> 149:156823d33999 146 monitored, thresholds, ...)
<> 149:156823d33999 147 using function HAL_ADC_AnalogWDGConfig().
<> 149:156823d33999 148
<> 149:156823d33999 149 (#) Optionally, for devices with several ADC instances: configure the
<> 149:156823d33999 150 multimode parameters
<> 149:156823d33999 151 using function HAL_ADCEx_MultiModeConfigChannel().
<> 149:156823d33999 152
<> 149:156823d33999 153 *** Execution of ADC conversions ***
<> 149:156823d33999 154 ====================================
<> 149:156823d33999 155 [..]
<> 149:156823d33999 156
<> 149:156823d33999 157 (#) ADC driver can be used among three modes: polling, interruption,
<> 149:156823d33999 158 transfer by DMA.
<> 149:156823d33999 159
<> 149:156823d33999 160 (++) ADC conversion by polling:
<> 149:156823d33999 161 (+++) Activate the ADC peripheral and start conversions
<> 149:156823d33999 162 using function HAL_ADC_Start()
<> 149:156823d33999 163 (+++) Wait for ADC conversion completion
<> 149:156823d33999 164 using function HAL_ADC_PollForConversion()
<> 149:156823d33999 165 (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
<> 149:156823d33999 166 (+++) Retrieve conversion results
<> 149:156823d33999 167 using function HAL_ADC_GetValue()
<> 149:156823d33999 168 (or for injected group: HAL_ADCEx_InjectedGetValue() )
<> 149:156823d33999 169 (+++) Stop conversion and disable the ADC peripheral
<> 149:156823d33999 170 using function HAL_ADC_Stop()
<> 149:156823d33999 171
<> 149:156823d33999 172 (++) ADC conversion by interruption:
<> 149:156823d33999 173 (+++) Activate the ADC peripheral and start conversions
<> 149:156823d33999 174 using function HAL_ADC_Start_IT()
<> 149:156823d33999 175 (+++) Wait for ADC conversion completion by call of function
<> 149:156823d33999 176 HAL_ADC_ConvCpltCallback()
<> 149:156823d33999 177 (this function must be implemented in user program)
<> 149:156823d33999 178 (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
<> 149:156823d33999 179 (+++) Retrieve conversion results
<> 149:156823d33999 180 using function HAL_ADC_GetValue()
<> 149:156823d33999 181 (or for injected group: HAL_ADCEx_InjectedGetValue() )
<> 149:156823d33999 182 (+++) Stop conversion and disable the ADC peripheral
<> 149:156823d33999 183 using function HAL_ADC_Stop_IT()
<> 149:156823d33999 184
<> 149:156823d33999 185 (++) ADC conversion with transfer by DMA:
<> 149:156823d33999 186 (+++) Activate the ADC peripheral and start conversions
<> 149:156823d33999 187 using function HAL_ADC_Start_DMA()
<> 149:156823d33999 188 (+++) Wait for ADC conversion completion by call of function
<> 149:156823d33999 189 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
<> 149:156823d33999 190 (these functions must be implemented in user program)
<> 149:156823d33999 191 (+++) Conversion results are automatically transferred by DMA into
<> 149:156823d33999 192 destination variable address.
<> 149:156823d33999 193 (+++) Stop conversion and disable the ADC peripheral
<> 149:156823d33999 194 using function HAL_ADC_Stop_DMA()
<> 149:156823d33999 195
<> 149:156823d33999 196 (++) For devices with several ADCs: ADC multimode conversion
<> 149:156823d33999 197 with transfer by DMA:
<> 149:156823d33999 198 (+++) Activate the ADC peripheral (slave) and start conversions
<> 149:156823d33999 199 using function HAL_ADC_Start()
<> 149:156823d33999 200 (+++) Activate the ADC peripheral (master) and start conversions
<> 149:156823d33999 201 using function HAL_ADCEx_MultiModeStart_DMA()
<> 149:156823d33999 202 (+++) Wait for ADC conversion completion by call of function
<> 149:156823d33999 203 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
<> 149:156823d33999 204 (these functions must be implemented in user program)
<> 149:156823d33999 205 (+++) Conversion results are automatically transferred by DMA into
<> 149:156823d33999 206 destination variable address.
<> 149:156823d33999 207 (+++) Stop conversion and disable the ADC peripheral (master)
<> 149:156823d33999 208 using function HAL_ADCEx_MultiModeStop_DMA()
<> 149:156823d33999 209 (+++) Stop conversion and disable the ADC peripheral (slave)
<> 149:156823d33999 210 using function HAL_ADC_Stop_IT()
<> 149:156823d33999 211
<> 149:156823d33999 212 [..]
<> 149:156823d33999 213
<> 149:156823d33999 214 (@) Callback functions must be implemented in user program:
<> 149:156823d33999 215 (+@) HAL_ADC_ErrorCallback()
<> 149:156823d33999 216 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
<> 149:156823d33999 217 (+@) HAL_ADC_ConvCpltCallback()
<> 149:156823d33999 218 (+@) HAL_ADC_ConvHalfCpltCallback
<> 149:156823d33999 219 (+@) HAL_ADCEx_InjectedConvCpltCallback()
<> 149:156823d33999 220
<> 149:156823d33999 221 *** Deinitialization of ADC ***
<> 149:156823d33999 222 ============================================================
<> 149:156823d33999 223 [..]
<> 149:156823d33999 224
<> 149:156823d33999 225 (#) Disable the ADC interface
<> 149:156823d33999 226 (++) ADC clock can be hard reset and disabled at RCC top level.
<> 149:156823d33999 227 (++) Hard reset of ADC peripherals
<> 149:156823d33999 228 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
<> 149:156823d33999 229 (++) ADC clock disable
<> 149:156823d33999 230 using the equivalent macro/functions as configuration step.
<> 149:156823d33999 231 (+++) Example:
<> 149:156823d33999 232 Into HAL_ADC_MspDeInit() (recommended code location) or with
<> 149:156823d33999 233 other device clock parameters configuration:
<> 149:156823d33999 234 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
<> 149:156823d33999 235 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
<> 149:156823d33999 236 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
<> 149:156823d33999 237 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
<> 149:156823d33999 238
<> 149:156823d33999 239 (#) ADC pins configuration
<> 149:156823d33999 240 (++) Disable the clock for the ADC GPIOs
<> 149:156823d33999 241 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
<> 149:156823d33999 242
<> 149:156823d33999 243 (#) Optionally, in case of usage of ADC with interruptions:
<> 149:156823d33999 244 (++) Disable the NVIC for ADC
<> 149:156823d33999 245 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
<> 149:156823d33999 246
<> 149:156823d33999 247 (#) Optionally, in case of usage of DMA:
<> 149:156823d33999 248 (++) Deinitialize the DMA
<> 149:156823d33999 249 using function HAL_DMA_Init().
<> 149:156823d33999 250 (++) Disable the NVIC for DMA
<> 149:156823d33999 251 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
<> 149:156823d33999 252
<> 149:156823d33999 253 [..]
<> 149:156823d33999 254
<> 149:156823d33999 255 @endverbatim
<> 149:156823d33999 256 ******************************************************************************
<> 149:156823d33999 257 * @attention
<> 149:156823d33999 258 *
<> 149:156823d33999 259 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 260 *
<> 149:156823d33999 261 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 262 * are permitted provided that the following conditions are met:
<> 149:156823d33999 263 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 264 * this list of conditions and the following disclaimer.
<> 149:156823d33999 265 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 266 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 267 * and/or other materials provided with the distribution.
<> 149:156823d33999 268 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 269 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 270 * without specific prior written permission.
<> 149:156823d33999 271 *
<> 149:156823d33999 272 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 273 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 274 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 275 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 276 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 277 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 278 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 279 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 280 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 281 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 282 *
<> 149:156823d33999 283 ******************************************************************************
<> 149:156823d33999 284 */
<> 149:156823d33999 285
<> 149:156823d33999 286 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 287 #include "stm32l1xx_hal.h"
<> 149:156823d33999 288
<> 149:156823d33999 289 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 290 * @{
<> 149:156823d33999 291 */
<> 149:156823d33999 292
<> 149:156823d33999 293 /** @defgroup ADC ADC
<> 149:156823d33999 294 * @brief ADC HAL module driver
<> 149:156823d33999 295 * @{
<> 149:156823d33999 296 */
<> 149:156823d33999 297
<> 149:156823d33999 298 #ifdef HAL_ADC_MODULE_ENABLED
<> 149:156823d33999 299
<> 149:156823d33999 300 /* Private typedef -----------------------------------------------------------*/
<> 149:156823d33999 301 /* Private define ------------------------------------------------------------*/
<> 149:156823d33999 302 /** @defgroup ADC_Private_Constants ADC Private Constants
<> 149:156823d33999 303 * @{
<> 149:156823d33999 304 */
<> 149:156823d33999 305
<> 149:156823d33999 306 /* Timeout values for ADC enable and disable settling time. */
<> 149:156823d33999 307 /* Values defined to be higher than worst cases: low clocks freq, */
<> 149:156823d33999 308 /* maximum prescaler. */
<> 149:156823d33999 309 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
<> 149:156823d33999 310 /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
<> 149:156823d33999 311 /* Unit: ms */
<> 149:156823d33999 312 #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
<> 149:156823d33999 313 #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
<> 149:156823d33999 314
<> 149:156823d33999 315 /* Delay for ADC stabilization time. */
<> 149:156823d33999 316 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
<> 149:156823d33999 317 /* Unit: us */
<> 149:156823d33999 318 #define ADC_STAB_DELAY_US ((uint32_t) 3)
<> 149:156823d33999 319
<> 149:156823d33999 320 /* Delay for temperature sensor stabilization time. */
<> 149:156823d33999 321 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<> 149:156823d33999 322 /* Unit: us */
<> 149:156823d33999 323 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
<> 149:156823d33999 324
<> 149:156823d33999 325 /**
<> 149:156823d33999 326 * @}
<> 149:156823d33999 327 */
<> 149:156823d33999 328
<> 149:156823d33999 329 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 330 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 331 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 332 /** @defgroup ADC_Private_Functions ADC Private Functions
<> 149:156823d33999 333 * @{
<> 149:156823d33999 334 */
<> 149:156823d33999 335 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 336 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 337 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
<> 149:156823d33999 338 /**
<> 149:156823d33999 339 * @}
<> 149:156823d33999 340 */
<> 149:156823d33999 341
<> 149:156823d33999 342 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 343
<> 149:156823d33999 344 /** @defgroup ADC_Exported_Functions ADC Exported Functions
<> 149:156823d33999 345 * @{
<> 149:156823d33999 346 */
<> 149:156823d33999 347
<> 149:156823d33999 348 /** @defgroup ADC_Exported_Functions_Group1 ADC Initialization/de-initialization functions
<> 149:156823d33999 349 * @brief ADC Initialization and Configuration functions
<> 149:156823d33999 350 *
<> 149:156823d33999 351 @verbatim
<> 149:156823d33999 352 ===============================================================================
<> 149:156823d33999 353 ##### Initialization and de-initialization functions #####
<> 149:156823d33999 354 ===============================================================================
<> 149:156823d33999 355 [..] This section provides functions allowing to:
<> 149:156823d33999 356 (+) Initialize and configure the ADC.
<> 149:156823d33999 357 (+) De-initialize the ADC.
<> 149:156823d33999 358 @endverbatim
<> 149:156823d33999 359 * @{
<> 149:156823d33999 360 */
<> 149:156823d33999 361
<> 149:156823d33999 362 /**
<> 149:156823d33999 363 * @brief Initializes the ADC peripheral and regular group according to
<> 149:156823d33999 364 * parameters specified in structure "ADC_InitTypeDef".
<> 149:156823d33999 365 * @note As prerequisite, ADC clock must be configured at RCC top level
<> 149:156823d33999 366 * (clock source APB2).
<> 149:156823d33999 367 * See commented example code below that can be copied and uncommented
<> 149:156823d33999 368 * into HAL_ADC_MspInit().
<> 149:156823d33999 369 * @note Possibility to update parameters on the fly:
<> 149:156823d33999 370 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
<> 149:156823d33999 371 * coming from ADC state reset. Following calls to this function can
<> 149:156823d33999 372 * be used to reconfigure some parameters of ADC_InitTypeDef
<> 149:156823d33999 373 * structure on the fly, without modifying MSP configuration. If ADC
<> 149:156823d33999 374 * MSP has to be modified again, HAL_ADC_DeInit() must be called
<> 149:156823d33999 375 * before HAL_ADC_Init().
<> 149:156823d33999 376 * The setting of these parameters is conditioned to ADC state.
<> 149:156823d33999 377 * For parameters constraints, see comments of structure
<> 149:156823d33999 378 * "ADC_InitTypeDef".
<> 149:156823d33999 379 * @note This function configures the ADC within 2 scopes: scope of entire
<> 149:156823d33999 380 * ADC and scope of regular group. For parameters details, see comments
<> 149:156823d33999 381 * of structure "ADC_InitTypeDef".
<> 149:156823d33999 382 * @param hadc: ADC handle
<> 149:156823d33999 383 * @retval HAL status
<> 149:156823d33999 384 */
<> 149:156823d33999 385 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 386 {
<> 149:156823d33999 387 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 388 uint32_t tmp_cr1 = 0;
<> 149:156823d33999 389 uint32_t tmp_cr2 = 0;
<> 149:156823d33999 390
<> 149:156823d33999 391 /* Check ADC handle */
<> 149:156823d33999 392 if(hadc == NULL)
<> 149:156823d33999 393 {
<> 149:156823d33999 394 return HAL_ERROR;
<> 149:156823d33999 395 }
<> 149:156823d33999 396
<> 149:156823d33999 397 /* Check the parameters */
<> 149:156823d33999 398 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 399 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
<> 149:156823d33999 400 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
<> 149:156823d33999 401 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
<> 149:156823d33999 402 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
<> 149:156823d33999 403 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
<> 149:156823d33999 404 assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait));
<> 149:156823d33999 405 assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff));
<> 149:156823d33999 406 assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
<> 149:156823d33999 407 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 149:156823d33999 408 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
<> 149:156823d33999 409 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
<> 149:156823d33999 410
<> 149:156823d33999 411 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 149:156823d33999 412 {
<> 149:156823d33999 413 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<> 149:156823d33999 414 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
<> 149:156823d33999 415 if(hadc->Init.DiscontinuousConvMode != DISABLE)
<> 149:156823d33999 416 {
<> 149:156823d33999 417 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
<> 149:156823d33999 418 }
<> 149:156823d33999 419 }
<> 149:156823d33999 420
<> 149:156823d33999 421 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<> 149:156823d33999 422 {
<> 149:156823d33999 423 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
<> 149:156823d33999 424 }
<> 149:156823d33999 425
<> 149:156823d33999 426
<> 149:156823d33999 427 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
<> 149:156823d33999 428 /* at RCC top level. */
<> 149:156823d33999 429 /* Refer to header of this file for more details on clock enabling */
<> 149:156823d33999 430 /* procedure. */
<> 149:156823d33999 431
<> 149:156823d33999 432 /* Actions performed only if ADC is coming from state reset: */
<> 149:156823d33999 433 /* - Initialization of ADC MSP */
<> 149:156823d33999 434 if (hadc->State == HAL_ADC_STATE_RESET)
<> 149:156823d33999 435 {
<> 149:156823d33999 436 /* Initialize ADC error code */
<> 149:156823d33999 437 ADC_CLEAR_ERRORCODE(hadc);
<> 149:156823d33999 438
<> 149:156823d33999 439 /* Allocate lock resource and initialize it */
<> 149:156823d33999 440 hadc->Lock = HAL_UNLOCKED;
<> 149:156823d33999 441
<> 149:156823d33999 442 /* Enable SYSCFG clock to control the routing Interface (RI) */
<> 149:156823d33999 443 __HAL_RCC_SYSCFG_CLK_ENABLE();
<> 149:156823d33999 444
<> 149:156823d33999 445 /* Init the low level hardware */
<> 149:156823d33999 446 HAL_ADC_MspInit(hadc);
<> 149:156823d33999 447 }
<> 149:156823d33999 448
<> 149:156823d33999 449 /* Configuration of ADC parameters if previous preliminary actions are */
<> 149:156823d33999 450 /* correctly completed. */
<> 149:156823d33999 451 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 149:156823d33999 452 {
<> 149:156823d33999 453 /* Set ADC state */
<> 149:156823d33999 454 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 455 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 149:156823d33999 456 HAL_ADC_STATE_BUSY_INTERNAL);
<> 149:156823d33999 457
<> 149:156823d33999 458 /* Set ADC parameters */
<> 149:156823d33999 459
<> 149:156823d33999 460 /* Configuration of common ADC clock: clock source HSI with selectable */
<> 149:156823d33999 461 /* prescaler */
<> 149:156823d33999 462 MODIFY_REG(ADC->CCR ,
<> 149:156823d33999 463 ADC_CCR_ADCPRE ,
<> 149:156823d33999 464 hadc->Init.ClockPrescaler );
<> 149:156823d33999 465
<> 149:156823d33999 466 /* Configuration of ADC: */
<> 149:156823d33999 467 /* - external trigger polarity */
<> 149:156823d33999 468 /* - End of conversion selection */
<> 149:156823d33999 469 /* - DMA continuous request */
<> 149:156823d33999 470 /* - Channels bank (Banks availability depends on devices categories) */
<> 149:156823d33999 471 /* - continuous conversion mode */
<> 149:156823d33999 472 tmp_cr2 |= (hadc->Init.DataAlign |
<> 149:156823d33999 473 hadc->Init.EOCSelection |
<> 149:156823d33999 474 ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) |
<> 149:156823d33999 475 hadc->Init.ChannelsBank |
<> 149:156823d33999 476 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
<> 149:156823d33999 477
<> 149:156823d33999 478 /* Enable external trigger if trigger selection is different of software */
<> 149:156823d33999 479 /* start. */
<> 149:156823d33999 480 /* Note: This configuration keeps the hardware feature of parameter */
<> 149:156823d33999 481 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
<> 149:156823d33999 482 /* software start. */
<> 149:156823d33999 483 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
<> 149:156823d33999 484 {
<> 149:156823d33999 485 tmp_cr2 |= ( hadc->Init.ExternalTrigConv |
<> 149:156823d33999 486 hadc->Init.ExternalTrigConvEdge );
<> 149:156823d33999 487 }
<> 149:156823d33999 488
<> 149:156823d33999 489 /* Parameters update conditioned to ADC state: */
<> 149:156823d33999 490 /* Parameters that can be updated only when ADC is disabled: */
<> 149:156823d33999 491 /* - delay selection (LowPowerAutoWait mode) */
<> 149:156823d33999 492 /* - resolution */
<> 149:156823d33999 493 /* - auto power off (LowPowerAutoPowerOff mode) */
<> 149:156823d33999 494 /* - scan mode */
<> 149:156823d33999 495 /* - discontinuous mode disable/enable */
<> 149:156823d33999 496 /* - discontinuous mode number of conversions */
<> 149:156823d33999 497 if ((ADC_IS_ENABLE(hadc) == RESET))
<> 149:156823d33999 498 {
<> 149:156823d33999 499 tmp_cr2 |= hadc->Init.LowPowerAutoWait;
<> 149:156823d33999 500
<> 149:156823d33999 501 tmp_cr1 |= (hadc->Init.Resolution |
<> 149:156823d33999 502 hadc->Init.LowPowerAutoPowerOff |
<> 149:156823d33999 503 ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) );
<> 149:156823d33999 504
<> 149:156823d33999 505 /* Enable discontinuous mode only if continuous mode is disabled */
<> 149:156823d33999 506 /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
<> 149:156823d33999 507 /* discontinuous is set anyway, but has no effect on ADC HW. */
<> 149:156823d33999 508 if (hadc->Init.DiscontinuousConvMode == ENABLE)
<> 149:156823d33999 509 {
<> 149:156823d33999 510 if (hadc->Init.ContinuousConvMode == DISABLE)
<> 149:156823d33999 511 {
<> 149:156823d33999 512 /* Enable the selected ADC regular discontinuous mode */
<> 149:156823d33999 513 /* Set the number of channels to be converted in discontinuous mode */
<> 149:156823d33999 514 SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
<> 149:156823d33999 515 ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
<> 149:156823d33999 516 }
<> 149:156823d33999 517 else
<> 149:156823d33999 518 {
<> 149:156823d33999 519 /* ADC regular group settings continuous and sequencer discontinuous*/
<> 149:156823d33999 520 /* cannot be enabled simultaneously. */
<> 149:156823d33999 521
<> 149:156823d33999 522 /* Update ADC state machine to error */
<> 149:156823d33999 523 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 149:156823d33999 524
<> 149:156823d33999 525 /* Set ADC error code to ADC IP internal error */
<> 149:156823d33999 526 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 149:156823d33999 527 }
<> 149:156823d33999 528 }
<> 149:156823d33999 529
<> 149:156823d33999 530 /* Update ADC configuration register CR1 with previous settings */
<> 149:156823d33999 531 MODIFY_REG(hadc->Instance->CR1,
<> 149:156823d33999 532 ADC_CR1_RES |
<> 149:156823d33999 533 ADC_CR1_PDI |
<> 149:156823d33999 534 ADC_CR1_PDD |
<> 149:156823d33999 535 ADC_CR1_DISCNUM |
<> 149:156823d33999 536 ADC_CR1_DISCEN |
<> 149:156823d33999 537 ADC_CR1_SCAN ,
<> 149:156823d33999 538 tmp_cr1 );
<> 149:156823d33999 539 }
<> 149:156823d33999 540
<> 149:156823d33999 541 /* Update ADC configuration register CR2 with previous settings */
<> 149:156823d33999 542 MODIFY_REG(hadc->Instance->CR2 ,
<> 149:156823d33999 543 ADC_CR2_MASK_ADCINIT() ,
<> 149:156823d33999 544 tmp_cr2 );
<> 149:156823d33999 545
<> 149:156823d33999 546 /* Configuration of regular group sequencer: */
<> 149:156823d33999 547 /* - if scan mode is disabled, regular channels sequence length is set to */
<> 149:156823d33999 548 /* 0x00: 1 channel converted (channel on regular rank 1) */
<> 149:156823d33999 549 /* Parameter "NbrOfConversion" is discarded. */
<> 149:156823d33999 550 /* Note: Scan mode is present by hardware on this device and, if */
<> 149:156823d33999 551 /* disabled, discards automatically nb of conversions. Anyway, nb of */
<> 149:156823d33999 552 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
<> 149:156823d33999 553 /* - if scan mode is enabled, regular channels sequence length is set to */
<> 149:156823d33999 554 /* parameter "NbrOfConversion" */
<> 149:156823d33999 555 if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
<> 149:156823d33999 556 {
<> 149:156823d33999 557 MODIFY_REG(hadc->Instance->SQR1 ,
<> 149:156823d33999 558 ADC_SQR1_L ,
<> 149:156823d33999 559 ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) );
<> 149:156823d33999 560 }
<> 149:156823d33999 561 else
<> 149:156823d33999 562 {
<> 149:156823d33999 563 MODIFY_REG(hadc->Instance->SQR1,
<> 149:156823d33999 564 ADC_SQR1_L ,
<> 149:156823d33999 565 0x00000000 );
<> 149:156823d33999 566 }
<> 149:156823d33999 567
<> 149:156823d33999 568 /* Check back that ADC registers have effectively been configured to */
<> 149:156823d33999 569 /* ensure of no potential problem of ADC core IP clocking. */
<> 149:156823d33999 570 /* Check through register CR2 (excluding execution control bits ADON, */
<> 149:156823d33999 571 /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */
<> 149:156823d33999 572 if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON |
<> 149:156823d33999 573 ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
<> 149:156823d33999 574 ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL ))
<> 149:156823d33999 575 == tmp_cr2)
<> 149:156823d33999 576 {
<> 149:156823d33999 577 /* Set ADC error code to none */
<> 149:156823d33999 578 ADC_CLEAR_ERRORCODE(hadc);
<> 149:156823d33999 579
<> 149:156823d33999 580 /* Set the ADC state */
<> 149:156823d33999 581 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 582 HAL_ADC_STATE_BUSY_INTERNAL,
<> 149:156823d33999 583 HAL_ADC_STATE_READY);
<> 149:156823d33999 584 }
<> 149:156823d33999 585 else
<> 149:156823d33999 586 {
<> 149:156823d33999 587 /* Update ADC state machine to error */
<> 149:156823d33999 588 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 589 HAL_ADC_STATE_BUSY_INTERNAL,
<> 149:156823d33999 590 HAL_ADC_STATE_ERROR_INTERNAL);
<> 149:156823d33999 591
<> 149:156823d33999 592 /* Set ADC error code to ADC IP internal error */
<> 149:156823d33999 593 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 149:156823d33999 594
<> 149:156823d33999 595 tmp_hal_status = HAL_ERROR;
<> 149:156823d33999 596 }
<> 149:156823d33999 597
<> 149:156823d33999 598 }
<> 149:156823d33999 599 else
<> 149:156823d33999 600 {
<> 149:156823d33999 601 tmp_hal_status = HAL_ERROR;
<> 149:156823d33999 602 }
<> 149:156823d33999 603
<> 149:156823d33999 604 /* Return function status */
<> 149:156823d33999 605 return tmp_hal_status;
<> 149:156823d33999 606 }
<> 149:156823d33999 607
<> 149:156823d33999 608 /**
<> 149:156823d33999 609 * @brief Deinitialize the ADC peripheral registers to its default reset values.
<> 149:156823d33999 610 * @note To not impact other ADCs, reset of common ADC registers have been
<> 149:156823d33999 611 * left commented below.
<> 149:156823d33999 612 * If needed, the example code can be copied and uncommented into
<> 149:156823d33999 613 * function HAL_ADC_MspDeInit().
<> 149:156823d33999 614 * @param hadc: ADC handle
<> 149:156823d33999 615 * @retval HAL status
<> 149:156823d33999 616 */
<> 149:156823d33999 617 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 618 {
<> 149:156823d33999 619 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 620
<> 149:156823d33999 621 /* Check ADC handle */
<> 149:156823d33999 622 if(hadc == NULL)
<> 149:156823d33999 623 {
<> 149:156823d33999 624 return HAL_ERROR;
<> 149:156823d33999 625 }
<> 149:156823d33999 626
<> 149:156823d33999 627 /* Check the parameters */
<> 149:156823d33999 628 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 629
<> 149:156823d33999 630 /* Set ADC state */
<> 149:156823d33999 631 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
<> 149:156823d33999 632
<> 149:156823d33999 633 /* Stop potential conversion on going, on regular and injected groups */
<> 149:156823d33999 634 /* Disable ADC peripheral */
<> 149:156823d33999 635 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 149:156823d33999 636
<> 149:156823d33999 637
<> 149:156823d33999 638 /* Configuration of ADC parameters if previous preliminary actions are */
<> 149:156823d33999 639 /* correctly completed. */
<> 149:156823d33999 640 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 641 {
<> 149:156823d33999 642 /* ========== Reset ADC registers ========== */
<> 149:156823d33999 643 /* Reset register SR */
<> 149:156823d33999 644 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
<> 149:156823d33999 645 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
<> 149:156823d33999 646
<> 149:156823d33999 647 /* Reset register CR1 */
<> 149:156823d33999 648 CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
<> 149:156823d33999 649 ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD |
<> 149:156823d33999 650 ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
<> 149:156823d33999 651 ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
<> 149:156823d33999 652 ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
<> 149:156823d33999 653 ADC_CR1_AWDCH ));
<> 149:156823d33999 654
<> 149:156823d33999 655 /* Reset register CR2 */
<> 149:156823d33999 656 ADC_CR2_CLEAR(hadc);
<> 149:156823d33999 657
<> 149:156823d33999 658 /* Reset register SMPR0 */
<> 149:156823d33999 659 ADC_SMPR0_CLEAR(hadc);
<> 149:156823d33999 660
<> 149:156823d33999 661 /* Reset register SMPR1 */
<> 149:156823d33999 662 ADC_SMPR1_CLEAR(hadc);
<> 149:156823d33999 663
<> 149:156823d33999 664 /* Reset register SMPR2 */
<> 149:156823d33999 665 CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 |
<> 149:156823d33999 666 ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 |
<> 149:156823d33999 667 ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
<> 149:156823d33999 668 ADC_SMPR2_SMP10 ));
<> 149:156823d33999 669
<> 149:156823d33999 670 /* Reset register SMPR3 */
<> 149:156823d33999 671 CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 |
<> 149:156823d33999 672 ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 |
<> 149:156823d33999 673 ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
<> 149:156823d33999 674 ADC_SMPR3_SMP0 ));
<> 149:156823d33999 675
<> 149:156823d33999 676 /* Reset register JOFR1 */
<> 149:156823d33999 677 CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
<> 149:156823d33999 678 /* Reset register JOFR2 */
<> 149:156823d33999 679 CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
<> 149:156823d33999 680 /* Reset register JOFR3 */
<> 149:156823d33999 681 CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
<> 149:156823d33999 682 /* Reset register JOFR4 */
<> 149:156823d33999 683 CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
<> 149:156823d33999 684
<> 149:156823d33999 685 /* Reset register HTR */
<> 149:156823d33999 686 CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
<> 149:156823d33999 687 /* Reset register LTR */
<> 149:156823d33999 688 CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
<> 149:156823d33999 689
<> 149:156823d33999 690 /* Reset register SQR1 */
<> 149:156823d33999 691 CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX));
<> 149:156823d33999 692
<> 149:156823d33999 693 /* Reset register SQR2 */
<> 149:156823d33999 694 CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 |
<> 149:156823d33999 695 ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19 ));
<> 149:156823d33999 696
<> 149:156823d33999 697 /* Reset register SQR3 */
<> 149:156823d33999 698 CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 |
<> 149:156823d33999 699 ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13 ));
<> 149:156823d33999 700
<> 149:156823d33999 701 /* Reset register SQR4 */
<> 149:156823d33999 702 CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 |
<> 149:156823d33999 703 ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 ));
<> 149:156823d33999 704
<> 149:156823d33999 705 /* Reset register SQR5 */
<> 149:156823d33999 706 CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 |
<> 149:156823d33999 707 ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 ));
<> 149:156823d33999 708
<> 149:156823d33999 709
<> 149:156823d33999 710 /* Reset register JSQR */
<> 149:156823d33999 711 CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL |
<> 149:156823d33999 712 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
<> 149:156823d33999 713 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ));
<> 149:156823d33999 714
<> 149:156823d33999 715 /* Reset register DR */
<> 149:156823d33999 716 /* bits in access mode read only, no direct reset applicable*/
<> 149:156823d33999 717
<> 149:156823d33999 718 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
<> 149:156823d33999 719 /* bits in access mode read only, no direct reset applicable*/
<> 149:156823d33999 720
<> 149:156823d33999 721 /* Reset register CCR */
<> 149:156823d33999 722 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE);
<> 149:156823d33999 723
<> 149:156823d33999 724 /* ========== Hard reset ADC peripheral ========== */
<> 149:156823d33999 725 /* Performs a global reset of the entire ADC peripheral: ADC state is */
<> 149:156823d33999 726 /* forced to a similar state after device power-on. */
<> 149:156823d33999 727 /* If needed, copy-paste and uncomment the following reset code into */
<> 149:156823d33999 728 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
<> 149:156823d33999 729 /* */
<> 149:156823d33999 730 /* __HAL_RCC_ADC1_FORCE_RESET() */
<> 149:156823d33999 731 /* __HAL_RCC_ADC1_RELEASE_RESET() */
<> 149:156823d33999 732
<> 149:156823d33999 733 /* DeInit the low level hardware */
<> 149:156823d33999 734 HAL_ADC_MspDeInit(hadc);
<> 149:156823d33999 735
<> 149:156823d33999 736 /* Set ADC error code to none */
<> 149:156823d33999 737 ADC_CLEAR_ERRORCODE(hadc);
<> 149:156823d33999 738
<> 149:156823d33999 739 /* Set ADC state */
<> 149:156823d33999 740 hadc->State = HAL_ADC_STATE_RESET;
<> 149:156823d33999 741
<> 149:156823d33999 742 }
<> 149:156823d33999 743
<> 149:156823d33999 744 /* Process unlocked */
<> 149:156823d33999 745 __HAL_UNLOCK(hadc);
<> 149:156823d33999 746
<> 149:156823d33999 747 /* Return function status */
<> 149:156823d33999 748 return tmp_hal_status;
<> 149:156823d33999 749 }
<> 149:156823d33999 750
<> 149:156823d33999 751 /**
<> 149:156823d33999 752 * @brief Initializes the ADC MSP.
<> 149:156823d33999 753 * @param hadc: ADC handle
<> 149:156823d33999 754 * @retval None
<> 149:156823d33999 755 */
<> 149:156823d33999 756 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 757 {
<> 149:156823d33999 758 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 759 UNUSED(hadc);
<> 149:156823d33999 760
<> 149:156823d33999 761 /* NOTE : This function should not be modified. When the callback is needed,
<> 149:156823d33999 762 function HAL_ADC_MspInit must be implemented in the user file.
<> 149:156823d33999 763 */
<> 149:156823d33999 764 }
<> 149:156823d33999 765
<> 149:156823d33999 766 /**
<> 149:156823d33999 767 * @brief DeInitializes the ADC MSP.
<> 149:156823d33999 768 * @param hadc: ADC handle
<> 149:156823d33999 769 * @retval None
<> 149:156823d33999 770 */
<> 149:156823d33999 771 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 772 {
<> 149:156823d33999 773 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 774 UNUSED(hadc);
<> 149:156823d33999 775
<> 149:156823d33999 776 /* NOTE : This function should not be modified. When the callback is needed,
<> 149:156823d33999 777 function HAL_ADC_MspDeInit must be implemented in the user file.
<> 149:156823d33999 778 */
<> 149:156823d33999 779 }
<> 149:156823d33999 780
<> 149:156823d33999 781 /**
<> 149:156823d33999 782 * @}
<> 149:156823d33999 783 */
<> 149:156823d33999 784
<> 149:156823d33999 785 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
<> 149:156823d33999 786 * @brief ADC IO operation functions
<> 149:156823d33999 787 *
<> 149:156823d33999 788 @verbatim
<> 149:156823d33999 789 ===============================================================================
<> 149:156823d33999 790 ##### IO operation functions #####
<> 149:156823d33999 791 ===============================================================================
<> 149:156823d33999 792 [..] This section provides functions allowing to:
<> 149:156823d33999 793 (+) Start conversion of regular group.
<> 149:156823d33999 794 (+) Stop conversion of regular group.
<> 149:156823d33999 795 (+) Poll for conversion complete on regular group.
<> 149:156823d33999 796 (+) Poll for conversion event.
<> 149:156823d33999 797 (+) Get result of regular channel conversion.
<> 149:156823d33999 798 (+) Start conversion of regular group and enable interruptions.
<> 149:156823d33999 799 (+) Stop conversion of regular group and disable interruptions.
<> 149:156823d33999 800 (+) Handle ADC interrupt request
<> 149:156823d33999 801 (+) Start conversion of regular group and enable DMA transfer.
<> 149:156823d33999 802 (+) Stop conversion of regular group and disable ADC DMA transfer.
<> 149:156823d33999 803 @endverbatim
<> 149:156823d33999 804 * @{
<> 149:156823d33999 805 */
<> 149:156823d33999 806
<> 149:156823d33999 807 /**
<> 149:156823d33999 808 * @brief Enables ADC, starts conversion of regular group.
<> 149:156823d33999 809 * Interruptions enabled in this function: None.
<> 149:156823d33999 810 * @param hadc: ADC handle
<> 149:156823d33999 811 * @retval HAL status
<> 149:156823d33999 812 */
<> 149:156823d33999 813 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 814 {
<> 149:156823d33999 815 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 816
<> 149:156823d33999 817 /* Check the parameters */
<> 149:156823d33999 818 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 819
<> 149:156823d33999 820 /* Process locked */
<> 149:156823d33999 821 __HAL_LOCK(hadc);
<> 149:156823d33999 822
<> 149:156823d33999 823 /* Enable the ADC peripheral */
<> 149:156823d33999 824 tmp_hal_status = ADC_Enable(hadc);
<> 149:156823d33999 825
<> 149:156823d33999 826 /* Start conversion if ADC is effectively enabled */
<> 149:156823d33999 827 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 828 {
<> 149:156823d33999 829 /* Set ADC state */
<> 149:156823d33999 830 /* - Clear state bitfield related to regular group conversion results */
<> 149:156823d33999 831 /* - Set state bitfield related to regular group operation */
<> 149:156823d33999 832 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 833 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
<> 149:156823d33999 834 HAL_ADC_STATE_REG_BUSY);
<> 149:156823d33999 835
<> 149:156823d33999 836 /* If conversions on group regular are also triggering group injected, */
<> 149:156823d33999 837 /* update ADC state. */
<> 149:156823d33999 838 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 149:156823d33999 839 {
<> 149:156823d33999 840 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 149:156823d33999 841 }
<> 149:156823d33999 842
<> 149:156823d33999 843 /* State machine update: Check if an injected conversion is ongoing */
<> 149:156823d33999 844 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 149:156823d33999 845 {
<> 149:156823d33999 846 /* Reset ADC error code fields related to conversions on group regular */
<> 149:156823d33999 847 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 149:156823d33999 848 }
<> 149:156823d33999 849 else
<> 149:156823d33999 850 {
<> 149:156823d33999 851 /* Reset ADC all error code fields */
<> 149:156823d33999 852 ADC_CLEAR_ERRORCODE(hadc);
<> 149:156823d33999 853 }
<> 149:156823d33999 854
<> 149:156823d33999 855 /* Process unlocked */
<> 149:156823d33999 856 /* Unlock before starting ADC conversions: in case of potential */
<> 149:156823d33999 857 /* interruption, to let the process to ADC IRQ Handler. */
<> 149:156823d33999 858 __HAL_UNLOCK(hadc);
<> 149:156823d33999 859
<> 149:156823d33999 860 /* Clear regular group conversion flag and overrun flag */
<> 149:156823d33999 861 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 149:156823d33999 862 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
<> 149:156823d33999 863
<> 149:156823d33999 864 /* Enable conversion of regular group. */
<> 149:156823d33999 865 /* If software start has been selected, conversion starts immediately. */
<> 149:156823d33999 866 /* If external trigger has been selected, conversion will start at next */
<> 149:156823d33999 867 /* trigger event. */
<> 149:156823d33999 868 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<> 149:156823d33999 869 {
<> 149:156823d33999 870 /* Start ADC conversion on regular group */
<> 149:156823d33999 871 SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
<> 149:156823d33999 872 }
<> 149:156823d33999 873 }
<> 149:156823d33999 874
<> 149:156823d33999 875 /* Return function status */
<> 149:156823d33999 876 return tmp_hal_status;
<> 149:156823d33999 877 }
<> 149:156823d33999 878
<> 149:156823d33999 879 /**
<> 149:156823d33999 880 * @brief Stop ADC conversion of regular group (and injected channels in
<> 149:156823d33999 881 * case of auto_injection mode), disable ADC peripheral.
<> 149:156823d33999 882 * @note: ADC peripheral disable is forcing stop of potential
<> 149:156823d33999 883 * conversion on injected group. If injected group is under use, it
<> 149:156823d33999 884 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<> 149:156823d33999 885 * @param hadc: ADC handle
<> 149:156823d33999 886 * @retval HAL status.
<> 149:156823d33999 887 */
<> 149:156823d33999 888 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 889 {
<> 149:156823d33999 890 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 891
<> 149:156823d33999 892 /* Check the parameters */
<> 149:156823d33999 893 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 894
<> 149:156823d33999 895 /* Process locked */
<> 149:156823d33999 896 __HAL_LOCK(hadc);
<> 149:156823d33999 897
<> 149:156823d33999 898 /* Stop potential conversion on going, on regular and injected groups */
<> 149:156823d33999 899 /* Disable ADC peripheral */
<> 149:156823d33999 900 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 149:156823d33999 901
<> 149:156823d33999 902 /* Check if ADC is effectively disabled */
<> 149:156823d33999 903 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 904 {
<> 149:156823d33999 905 /* Set ADC state */
<> 149:156823d33999 906 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 907 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 149:156823d33999 908 HAL_ADC_STATE_READY);
<> 149:156823d33999 909 }
<> 149:156823d33999 910
<> 149:156823d33999 911 /* Process unlocked */
<> 149:156823d33999 912 __HAL_UNLOCK(hadc);
<> 149:156823d33999 913
<> 149:156823d33999 914 /* Return function status */
<> 149:156823d33999 915 return tmp_hal_status;
<> 149:156823d33999 916 }
<> 149:156823d33999 917
<> 149:156823d33999 918 /**
<> 149:156823d33999 919 * @brief Wait for regular group conversion to be completed.
<> 149:156823d33999 920 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
<> 149:156823d33999 921 * conversion) are cleared by this function, with an exception:
<> 149:156823d33999 922 * if low power feature "LowPowerAutoWait" is enabled, flags are
<> 149:156823d33999 923 * not cleared to not interfere with this feature until data register
<> 149:156823d33999 924 * is read using function HAL_ADC_GetValue().
<> 149:156823d33999 925 * @note This function cannot be used in a particular setup: ADC configured
<> 149:156823d33999 926 * in DMA mode and polling for end of each conversion (ADC init
<> 149:156823d33999 927 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
<> 149:156823d33999 928 * In this case, DMA resets the flag EOC and polling cannot be
<> 149:156823d33999 929 * performed on each conversion. Nevertheless, polling can still
<> 149:156823d33999 930 * be performed on the complete sequence (ADC init
<> 149:156823d33999 931 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
<> 149:156823d33999 932 * @param hadc: ADC handle
<> 149:156823d33999 933 * @param Timeout: Timeout value in millisecond.
<> 149:156823d33999 934 * @retval HAL status
<> 149:156823d33999 935 */
<> 149:156823d33999 936 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 149:156823d33999 937 {
<> 149:156823d33999 938 uint32_t tickstart = 0;
<> 149:156823d33999 939
<> 149:156823d33999 940 /* Check the parameters */
<> 149:156823d33999 941 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 942
<> 149:156823d33999 943 /* Verification that ADC configuration is compliant with polling for */
<> 149:156823d33999 944 /* each conversion: */
<> 149:156823d33999 945 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
<> 149:156823d33999 946 /* several ranks and polling for end of each conversion. */
<> 149:156823d33999 947 /* For code simplicity sake, this particular case is generalized to */
<> 149:156823d33999 948 /* ADC configured in DMA mode and and polling for end of each conversion. */
<> 149:156823d33999 949 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
<> 149:156823d33999 950 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
<> 149:156823d33999 951 {
<> 149:156823d33999 952 /* Update ADC state machine to error */
<> 149:156823d33999 953 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 149:156823d33999 954
<> 149:156823d33999 955 /* Process unlocked */
<> 149:156823d33999 956 __HAL_UNLOCK(hadc);
<> 149:156823d33999 957
<> 149:156823d33999 958 return HAL_ERROR;
<> 149:156823d33999 959 }
<> 149:156823d33999 960
<> 149:156823d33999 961 /* Get tick count */
<> 149:156823d33999 962 tickstart = HAL_GetTick();
<> 149:156823d33999 963
<> 149:156823d33999 964 /* Wait until End of Conversion flag is raised */
<> 149:156823d33999 965 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
<> 149:156823d33999 966 {
<> 149:156823d33999 967 /* Check if timeout is disabled (set to infinite wait) */
<> 149:156823d33999 968 if(Timeout != HAL_MAX_DELAY)
<> 149:156823d33999 969 {
<> 149:156823d33999 970 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 149:156823d33999 971 {
<> 149:156823d33999 972 /* Update ADC state machine to timeout */
<> 149:156823d33999 973 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 149:156823d33999 974
<> 149:156823d33999 975 /* Process unlocked */
<> 149:156823d33999 976 __HAL_UNLOCK(hadc);
<> 149:156823d33999 977
<> 149:156823d33999 978 return HAL_TIMEOUT;
<> 149:156823d33999 979 }
<> 149:156823d33999 980 }
<> 149:156823d33999 981 }
<> 149:156823d33999 982
<> 149:156823d33999 983 /* Clear end of conversion flag of regular group if low power feature */
<> 149:156823d33999 984 /* "Auto Wait" is disabled, to not interfere with this feature until data */
<> 149:156823d33999 985 /* register is read using function HAL_ADC_GetValue(). */
<> 149:156823d33999 986 if (hadc->Init.LowPowerAutoWait == DISABLE)
<> 149:156823d33999 987 {
<> 149:156823d33999 988 /* Clear regular group conversion flag */
<> 149:156823d33999 989 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
<> 149:156823d33999 990 }
<> 149:156823d33999 991
<> 149:156823d33999 992 /* Update ADC state machine */
<> 149:156823d33999 993 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 149:156823d33999 994
<> 149:156823d33999 995 /* Determine whether any further conversion upcoming on group regular */
<> 149:156823d33999 996 /* by external trigger, continuous mode or scan sequence on going. */
<> 149:156823d33999 997 /* Note: On STM32L1, there is no independent flag of end of sequence. */
<> 149:156823d33999 998 /* The test of scan sequence on going is done either with scan */
<> 149:156823d33999 999 /* sequence disabled or with end of conversion flag set to */
<> 149:156823d33999 1000 /* of end of sequence. */
<> 149:156823d33999 1001 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 149:156823d33999 1002 (hadc->Init.ContinuousConvMode == DISABLE) &&
<> 149:156823d33999 1003 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
<> 149:156823d33999 1004 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
<> 149:156823d33999 1005 {
<> 149:156823d33999 1006 /* Set ADC state */
<> 149:156823d33999 1007 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 149:156823d33999 1008
<> 149:156823d33999 1009 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 149:156823d33999 1010 {
<> 149:156823d33999 1011 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 149:156823d33999 1012 }
<> 149:156823d33999 1013 }
<> 149:156823d33999 1014
<> 149:156823d33999 1015 /* Return ADC state */
<> 149:156823d33999 1016 return HAL_OK;
<> 149:156823d33999 1017 }
<> 149:156823d33999 1018
<> 149:156823d33999 1019 /**
<> 149:156823d33999 1020 * @brief Poll for conversion event.
<> 149:156823d33999 1021 * @param hadc: ADC handle
<> 149:156823d33999 1022 * @param EventType: the ADC event type.
<> 149:156823d33999 1023 * This parameter can be one of the following values:
<> 149:156823d33999 1024 * @arg ADC_AWD_EVENT: ADC Analog watchdog event.
<> 149:156823d33999 1025 * @arg ADC_OVR_EVENT: ADC Overrun event.
<> 149:156823d33999 1026 * @param Timeout: Timeout value in millisecond.
<> 149:156823d33999 1027 * @retval HAL status
<> 149:156823d33999 1028 */
<> 149:156823d33999 1029 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
<> 149:156823d33999 1030 {
<> 149:156823d33999 1031 uint32_t tickstart = 0;
<> 149:156823d33999 1032
<> 149:156823d33999 1033 /* Check the parameters */
<> 149:156823d33999 1034 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1035 assert_param(IS_ADC_EVENT_TYPE(EventType));
<> 149:156823d33999 1036
<> 149:156823d33999 1037 /* Get tick count */
<> 149:156823d33999 1038 tickstart = HAL_GetTick();
<> 149:156823d33999 1039
<> 149:156823d33999 1040 /* Check selected event flag */
<> 149:156823d33999 1041 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
<> 149:156823d33999 1042 {
<> 149:156823d33999 1043 /* Check if timeout is disabled (set to infinite wait) */
<> 149:156823d33999 1044 if(Timeout != HAL_MAX_DELAY)
<> 149:156823d33999 1045 {
<> 149:156823d33999 1046 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 149:156823d33999 1047 {
<> 149:156823d33999 1048 /* Update ADC state machine to timeout */
<> 149:156823d33999 1049 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 149:156823d33999 1050
<> 149:156823d33999 1051 /* Process unlocked */
<> 149:156823d33999 1052 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1053
<> 149:156823d33999 1054 return HAL_TIMEOUT;
<> 149:156823d33999 1055 }
<> 149:156823d33999 1056 }
<> 149:156823d33999 1057 }
<> 149:156823d33999 1058
<> 149:156823d33999 1059 switch(EventType)
<> 149:156823d33999 1060 {
<> 149:156823d33999 1061 /* Analog watchdog (level out of window) event */
<> 149:156823d33999 1062 case ADC_AWD_EVENT:
<> 149:156823d33999 1063 /* Set ADC state */
<> 149:156823d33999 1064 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 149:156823d33999 1065
<> 149:156823d33999 1066 /* Clear ADC analog watchdog flag */
<> 149:156823d33999 1067 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 149:156823d33999 1068 break;
<> 149:156823d33999 1069
<> 149:156823d33999 1070 /* Overrun event */
<> 149:156823d33999 1071 default: /* Case ADC_OVR_EVENT */
<> 149:156823d33999 1072 /* Note: On STM32L1, ADC overrun can be set through other parameters */
<> 149:156823d33999 1073 /* refer to description of parameter "EOCSelection" for more */
<> 149:156823d33999 1074 /* details. */
<> 149:156823d33999 1075
<> 149:156823d33999 1076 /* Set ADC state */
<> 149:156823d33999 1077 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
<> 149:156823d33999 1078 /* Set ADC error code to overrun */
<> 149:156823d33999 1079 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 149:156823d33999 1080
<> 149:156823d33999 1081 /* Clear ADC overrun flag */
<> 149:156823d33999 1082 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 149:156823d33999 1083 break;
<> 149:156823d33999 1084 }
<> 149:156823d33999 1085
<> 149:156823d33999 1086 /* Return ADC state */
<> 149:156823d33999 1087 return HAL_OK;
<> 149:156823d33999 1088 }
<> 149:156823d33999 1089
<> 149:156823d33999 1090 /**
<> 149:156823d33999 1091 * @brief Enables ADC, starts conversion of regular group with interruption.
<> 149:156823d33999 1092 * Interruptions enabled in this function:
<> 149:156823d33999 1093 * - EOC (end of conversion of regular group)
<> 149:156823d33999 1094 * - overrun
<> 149:156823d33999 1095 * Each of these interruptions has its dedicated callback function.
<> 149:156823d33999 1096 * @param hadc: ADC handle
<> 149:156823d33999 1097 * @retval HAL status
<> 149:156823d33999 1098 */
<> 149:156823d33999 1099 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1100 {
<> 149:156823d33999 1101 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 1102
<> 149:156823d33999 1103 /* Check the parameters */
<> 149:156823d33999 1104 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1105
<> 149:156823d33999 1106 /* Process locked */
<> 149:156823d33999 1107 __HAL_LOCK(hadc);
<> 149:156823d33999 1108
<> 149:156823d33999 1109 /* Enable the ADC peripheral */
<> 149:156823d33999 1110 tmp_hal_status = ADC_Enable(hadc);
<> 149:156823d33999 1111
<> 149:156823d33999 1112 /* Start conversion if ADC is effectively enabled */
<> 149:156823d33999 1113 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 1114 {
<> 149:156823d33999 1115 /* Set ADC state */
<> 149:156823d33999 1116 /* - Clear state bitfield related to regular group conversion results */
<> 149:156823d33999 1117 /* - Set state bitfield related to regular group operation */
<> 149:156823d33999 1118 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 1119 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
<> 149:156823d33999 1120 HAL_ADC_STATE_REG_BUSY);
<> 149:156823d33999 1121
<> 149:156823d33999 1122 /* If conversions on group regular are also triggering group injected, */
<> 149:156823d33999 1123 /* update ADC state. */
<> 149:156823d33999 1124 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 149:156823d33999 1125 {
<> 149:156823d33999 1126 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 149:156823d33999 1127 }
<> 149:156823d33999 1128
<> 149:156823d33999 1129 /* State machine update: Check if an injected conversion is ongoing */
<> 149:156823d33999 1130 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 149:156823d33999 1131 {
<> 149:156823d33999 1132 /* Reset ADC error code fields related to conversions on group regular */
<> 149:156823d33999 1133 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 149:156823d33999 1134 }
<> 149:156823d33999 1135 else
<> 149:156823d33999 1136 {
<> 149:156823d33999 1137 /* Reset ADC all error code fields */
<> 149:156823d33999 1138 ADC_CLEAR_ERRORCODE(hadc);
<> 149:156823d33999 1139 }
<> 149:156823d33999 1140
<> 149:156823d33999 1141 /* Process unlocked */
<> 149:156823d33999 1142 /* Unlock before starting ADC conversions: in case of potential */
<> 149:156823d33999 1143 /* interruption, to let the process to ADC IRQ Handler. */
<> 149:156823d33999 1144 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1145
<> 149:156823d33999 1146 /* Clear regular group conversion flag and overrun flag */
<> 149:156823d33999 1147 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 149:156823d33999 1148 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
<> 149:156823d33999 1149
<> 149:156823d33999 1150 /* Enable end of conversion interrupt for regular group */
<> 149:156823d33999 1151 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
<> 149:156823d33999 1152
<> 149:156823d33999 1153 /* Enable conversion of regular group. */
<> 149:156823d33999 1154 /* If software start has been selected, conversion starts immediately. */
<> 149:156823d33999 1155 /* If external trigger has been selected, conversion will start at next */
<> 149:156823d33999 1156 /* trigger event. */
<> 149:156823d33999 1157 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<> 149:156823d33999 1158 {
<> 149:156823d33999 1159 /* Start ADC conversion on regular group */
<> 149:156823d33999 1160 SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
<> 149:156823d33999 1161 }
<> 149:156823d33999 1162 }
<> 149:156823d33999 1163
<> 149:156823d33999 1164 /* Return function status */
<> 149:156823d33999 1165 return tmp_hal_status;
<> 149:156823d33999 1166 }
<> 149:156823d33999 1167
<> 149:156823d33999 1168 /**
<> 149:156823d33999 1169 * @brief Stop ADC conversion of regular group (and injected group in
<> 149:156823d33999 1170 * case of auto_injection mode), disable interrution of
<> 149:156823d33999 1171 * end-of-conversion, disable ADC peripheral.
<> 149:156823d33999 1172 * @param hadc: ADC handle
<> 149:156823d33999 1173 * @retval None
<> 149:156823d33999 1174 */
<> 149:156823d33999 1175 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1176 {
<> 149:156823d33999 1177 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 1178
<> 149:156823d33999 1179 /* Check the parameters */
<> 149:156823d33999 1180 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1181
<> 149:156823d33999 1182 /* Process locked */
<> 149:156823d33999 1183 __HAL_LOCK(hadc);
<> 149:156823d33999 1184
<> 149:156823d33999 1185 /* Stop potential conversion on going, on regular and injected groups */
<> 149:156823d33999 1186 /* Disable ADC peripheral */
<> 149:156823d33999 1187 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 149:156823d33999 1188
<> 149:156823d33999 1189 /* Check if ADC is effectively disabled */
<> 149:156823d33999 1190 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 1191 {
<> 149:156823d33999 1192 /* Disable ADC end of conversion interrupt for regular group */
<> 149:156823d33999 1193 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 149:156823d33999 1194
<> 149:156823d33999 1195 /* Set ADC state */
<> 149:156823d33999 1196 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 1197 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 149:156823d33999 1198 HAL_ADC_STATE_READY);
<> 149:156823d33999 1199 }
<> 149:156823d33999 1200
<> 149:156823d33999 1201 /* Process unlocked */
<> 149:156823d33999 1202 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1203
<> 149:156823d33999 1204 /* Return function status */
<> 149:156823d33999 1205 return tmp_hal_status;
<> 149:156823d33999 1206 }
<> 149:156823d33999 1207
<> 149:156823d33999 1208 /**
<> 149:156823d33999 1209 * @brief Enables ADC, starts conversion of regular group and transfers result
<> 149:156823d33999 1210 * through DMA.
<> 149:156823d33999 1211 * Interruptions enabled in this function:
<> 149:156823d33999 1212 * - DMA transfer complete
<> 149:156823d33999 1213 * - DMA half transfer
<> 149:156823d33999 1214 * - overrun
<> 149:156823d33999 1215 * Each of these interruptions has its dedicated callback function.
<> 149:156823d33999 1216 * @param hadc: ADC handle
<> 149:156823d33999 1217 * @param pData: The destination Buffer address.
<> 149:156823d33999 1218 * @param Length: The length of data to be transferred from ADC peripheral to memory.
<> 149:156823d33999 1219 * @retval None
<> 149:156823d33999 1220 */
<> 149:156823d33999 1221 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
<> 149:156823d33999 1222 {
<> 149:156823d33999 1223 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 1224
<> 149:156823d33999 1225 /* Check the parameters */
<> 149:156823d33999 1226 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1227
<> 149:156823d33999 1228 /* Process locked */
<> 149:156823d33999 1229 __HAL_LOCK(hadc);
<> 149:156823d33999 1230
<> 149:156823d33999 1231 /* Enable the ADC peripheral */
<> 149:156823d33999 1232 tmp_hal_status = ADC_Enable(hadc);
<> 149:156823d33999 1233
<> 149:156823d33999 1234 /* Start conversion if ADC is effectively enabled */
<> 149:156823d33999 1235 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 1236 {
<> 149:156823d33999 1237 /* Set ADC state */
<> 149:156823d33999 1238 /* - Clear state bitfield related to regular group conversion results */
<> 149:156823d33999 1239 /* - Set state bitfield related to regular group operation */
<> 149:156823d33999 1240 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 1241 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
<> 149:156823d33999 1242 HAL_ADC_STATE_REG_BUSY);
<> 149:156823d33999 1243
<> 149:156823d33999 1244 /* If conversions on group regular are also triggering group injected, */
<> 149:156823d33999 1245 /* update ADC state. */
<> 149:156823d33999 1246 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
<> 149:156823d33999 1247 {
<> 149:156823d33999 1248 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
<> 149:156823d33999 1249 }
<> 149:156823d33999 1250
<> 149:156823d33999 1251 /* State machine update: Check if an injected conversion is ongoing */
<> 149:156823d33999 1252 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 149:156823d33999 1253 {
<> 149:156823d33999 1254 /* Reset ADC error code fields related to conversions on group regular */
<> 149:156823d33999 1255 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
<> 149:156823d33999 1256 }
<> 149:156823d33999 1257 else
<> 149:156823d33999 1258 {
<> 149:156823d33999 1259 /* Reset ADC all error code fields */
<> 149:156823d33999 1260 ADC_CLEAR_ERRORCODE(hadc);
<> 149:156823d33999 1261 }
<> 149:156823d33999 1262
<> 149:156823d33999 1263 /* Process unlocked */
<> 149:156823d33999 1264 /* Unlock before starting ADC conversions: in case of potential */
<> 149:156823d33999 1265 /* interruption, to let the process to ADC IRQ Handler. */
<> 149:156823d33999 1266 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1267
<> 149:156823d33999 1268 /* Set the DMA transfer complete callback */
<> 149:156823d33999 1269 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
<> 149:156823d33999 1270
<> 149:156823d33999 1271 /* Set the DMA half transfer complete callback */
<> 149:156823d33999 1272 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
<> 149:156823d33999 1273
<> 149:156823d33999 1274 /* Set the DMA error callback */
<> 149:156823d33999 1275 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
<> 149:156823d33999 1276
<> 149:156823d33999 1277
<> 149:156823d33999 1278 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
<> 149:156823d33999 1279 /* start (in case of SW start): */
<> 149:156823d33999 1280
<> 149:156823d33999 1281 /* Clear regular group conversion flag and overrun flag */
<> 149:156823d33999 1282 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 149:156823d33999 1283 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
<> 149:156823d33999 1284
<> 149:156823d33999 1285 /* Enable ADC overrun interrupt */
<> 149:156823d33999 1286 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
<> 149:156823d33999 1287
<> 149:156823d33999 1288 /* Enable ADC DMA mode */
<> 149:156823d33999 1289 hadc->Instance->CR2 |= ADC_CR2_DMA;
<> 149:156823d33999 1290
<> 149:156823d33999 1291 /* Start the DMA channel */
<> 149:156823d33999 1292 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
<> 149:156823d33999 1293
<> 149:156823d33999 1294 /* Enable conversion of regular group. */
<> 149:156823d33999 1295 /* If software start has been selected, conversion starts immediately. */
<> 149:156823d33999 1296 /* If external trigger has been selected, conversion will start at next */
<> 149:156823d33999 1297 /* trigger event. */
<> 149:156823d33999 1298 /* Note: Alternate trigger for single conversion could be to force an */
<> 149:156823d33999 1299 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
<> 149:156823d33999 1300 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
<> 149:156823d33999 1301 {
<> 149:156823d33999 1302 /* Start ADC conversion on regular group */
<> 149:156823d33999 1303 SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
<> 149:156823d33999 1304 }
<> 149:156823d33999 1305 }
<> 149:156823d33999 1306
<> 149:156823d33999 1307 /* Return function status */
<> 149:156823d33999 1308 return tmp_hal_status;
<> 149:156823d33999 1309 }
<> 149:156823d33999 1310
<> 149:156823d33999 1311 /**
<> 149:156823d33999 1312 * @brief Stop ADC conversion of regular group (and injected group in
<> 149:156823d33999 1313 * case of auto_injection mode), disable ADC DMA transfer, disable
<> 149:156823d33999 1314 * ADC peripheral.
<> 149:156823d33999 1315 * @note: ADC peripheral disable is forcing stop of potential
<> 149:156823d33999 1316 * conversion on injected group. If injected group is under use, it
<> 149:156823d33999 1317 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
<> 149:156823d33999 1318 * @param hadc: ADC handle
<> 149:156823d33999 1319 * @retval HAL status.
<> 149:156823d33999 1320 */
<> 149:156823d33999 1321 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1322 {
<> 149:156823d33999 1323 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 1324
<> 149:156823d33999 1325 /* Check the parameters */
<> 149:156823d33999 1326 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1327
<> 149:156823d33999 1328 /* Process locked */
<> 149:156823d33999 1329 __HAL_LOCK(hadc);
<> 149:156823d33999 1330
<> 149:156823d33999 1331 /* Stop potential conversion on going, on regular and injected groups */
<> 149:156823d33999 1332 /* Disable ADC peripheral */
<> 149:156823d33999 1333 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 149:156823d33999 1334
<> 149:156823d33999 1335 /* Check if ADC is effectively disabled */
<> 149:156823d33999 1336 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 1337 {
<> 149:156823d33999 1338 /* Disable ADC DMA mode */
<> 149:156823d33999 1339 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
<> 149:156823d33999 1340
<> 149:156823d33999 1341 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
<> 149:156823d33999 1342 /* DMA transfer is on going) */
<> 149:156823d33999 1343 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
<> 149:156823d33999 1344
<> 149:156823d33999 1345 /* Check if DMA channel effectively disabled */
<> 149:156823d33999 1346 if (tmp_hal_status == HAL_OK)
<> 149:156823d33999 1347 {
<> 149:156823d33999 1348 /* Set ADC state */
<> 149:156823d33999 1349 ADC_STATE_CLR_SET(hadc->State,
<> 149:156823d33999 1350 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 149:156823d33999 1351 HAL_ADC_STATE_READY);
<> 149:156823d33999 1352 }
<> 149:156823d33999 1353 else
<> 149:156823d33999 1354 {
<> 149:156823d33999 1355 /* Update ADC state machine to error */
<> 149:156823d33999 1356 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 149:156823d33999 1357 }
<> 149:156823d33999 1358
<> 149:156823d33999 1359 /* Disable ADC overrun interrupt */
<> 149:156823d33999 1360 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
<> 149:156823d33999 1361 }
<> 149:156823d33999 1362
<> 149:156823d33999 1363 /* Process unlocked */
<> 149:156823d33999 1364 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1365
<> 149:156823d33999 1366 /* Return function status */
<> 149:156823d33999 1367 return tmp_hal_status;
<> 149:156823d33999 1368 }
<> 149:156823d33999 1369
<> 149:156823d33999 1370 /**
<> 149:156823d33999 1371 * @brief Get ADC regular group conversion result.
<> 149:156823d33999 1372 * @note Reading register DR automatically clears ADC flag EOC
<> 149:156823d33999 1373 * (ADC group regular end of unitary conversion).
<> 149:156823d33999 1374 * @note This function does not clear ADC flag EOS
<> 149:156823d33999 1375 * (ADC group regular end of sequence conversion).
<> 149:156823d33999 1376 * Occurrence of flag EOS rising:
<> 149:156823d33999 1377 * - If sequencer is composed of 1 rank, flag EOS is equivalent
<> 149:156823d33999 1378 * to flag EOC.
<> 149:156823d33999 1379 * - If sequencer is composed of several ranks, during the scan
<> 149:156823d33999 1380 * sequence flag EOC only is raised, at the end of the scan sequence
<> 149:156823d33999 1381 * both flags EOC and EOS are raised.
<> 149:156823d33999 1382 * To clear this flag, either use function:
<> 149:156823d33999 1383 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 149:156823d33999 1384 * model polling: @ref HAL_ADC_PollForConversion()
<> 149:156823d33999 1385 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
<> 149:156823d33999 1386 * @param hadc: ADC handle
<> 149:156823d33999 1387 * @retval ADC group regular conversion data
<> 149:156823d33999 1388 */
<> 149:156823d33999 1389 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1390 {
<> 149:156823d33999 1391 /* Check the parameters */
<> 149:156823d33999 1392 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1393
<> 149:156823d33999 1394 /* Note: EOC flag is not cleared here by software because automatically */
<> 149:156823d33999 1395 /* cleared by hardware when reading register DR. */
<> 149:156823d33999 1396
<> 149:156823d33999 1397 /* Return ADC converted value */
<> 149:156823d33999 1398 return hadc->Instance->DR;
<> 149:156823d33999 1399 }
<> 149:156823d33999 1400
<> 149:156823d33999 1401 /**
<> 149:156823d33999 1402 * @brief Handles ADC interrupt request
<> 149:156823d33999 1403 * @param hadc: ADC handle
<> 149:156823d33999 1404 * @retval None
<> 149:156823d33999 1405 */
<> 149:156823d33999 1406 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1407 {
<> 149:156823d33999 1408 /* Check the parameters */
<> 149:156823d33999 1409 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1410 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
<> 149:156823d33999 1411 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
<> 149:156823d33999 1412
<> 149:156823d33999 1413
<> 149:156823d33999 1414 /* ========== Check End of Conversion flag for regular group ========== */
<> 149:156823d33999 1415 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
<> 149:156823d33999 1416 {
<> 149:156823d33999 1417 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
<> 149:156823d33999 1418 {
<> 149:156823d33999 1419 /* Update state machine on conversion status if not in error state */
<> 149:156823d33999 1420 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 149:156823d33999 1421 {
<> 149:156823d33999 1422 /* Set ADC state */
<> 149:156823d33999 1423 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 149:156823d33999 1424 }
<> 149:156823d33999 1425
<> 149:156823d33999 1426 /* Determine whether any further conversion upcoming on group regular */
<> 149:156823d33999 1427 /* by external trigger, continuous mode or scan sequence on going. */
<> 149:156823d33999 1428 /* Note: On STM32L1, there is no independent flag of end of sequence. */
<> 149:156823d33999 1429 /* The test of scan sequence on going is done either with scan */
<> 149:156823d33999 1430 /* sequence disabled or with end of conversion flag set to */
<> 149:156823d33999 1431 /* of end of sequence. */
<> 149:156823d33999 1432 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 149:156823d33999 1433 (hadc->Init.ContinuousConvMode == DISABLE) &&
<> 149:156823d33999 1434 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
<> 149:156823d33999 1435 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
<> 149:156823d33999 1436 {
<> 149:156823d33999 1437 /* Disable ADC end of single conversion interrupt on group regular */
<> 149:156823d33999 1438 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 149:156823d33999 1439 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
<> 149:156823d33999 1440 /* by overrun IRQ process below. */
<> 149:156823d33999 1441 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 149:156823d33999 1442
<> 149:156823d33999 1443 /* Set ADC state */
<> 149:156823d33999 1444 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 149:156823d33999 1445
<> 149:156823d33999 1446 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 149:156823d33999 1447 {
<> 149:156823d33999 1448 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 149:156823d33999 1449 }
<> 149:156823d33999 1450 }
<> 149:156823d33999 1451
<> 149:156823d33999 1452 /* Conversion complete callback */
<> 149:156823d33999 1453 HAL_ADC_ConvCpltCallback(hadc);
<> 149:156823d33999 1454
<> 149:156823d33999 1455 /* Clear regular group conversion flag */
<> 149:156823d33999 1456 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
<> 149:156823d33999 1457 }
<> 149:156823d33999 1458 }
<> 149:156823d33999 1459
<> 149:156823d33999 1460 /* ========== Check End of Conversion flag for injected group ========== */
<> 149:156823d33999 1461 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
<> 149:156823d33999 1462 {
<> 149:156823d33999 1463 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
<> 149:156823d33999 1464 {
<> 149:156823d33999 1465 /* Update state machine on conversion status if not in error state */
<> 149:156823d33999 1466 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
<> 149:156823d33999 1467 {
<> 149:156823d33999 1468 /* Set ADC state */
<> 149:156823d33999 1469 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 149:156823d33999 1470 }
<> 149:156823d33999 1471
<> 149:156823d33999 1472 /* Determine whether any further conversion upcoming on group injected */
<> 149:156823d33999 1473 /* by external trigger, scan sequence on going or by automatic injected */
<> 149:156823d33999 1474 /* conversion from group regular (same conditions as group regular */
<> 149:156823d33999 1475 /* interruption disabling above). */
<> 149:156823d33999 1476 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
<> 149:156823d33999 1477 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
<> 149:156823d33999 1478 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
<> 149:156823d33999 1479 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
<> 149:156823d33999 1480 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 149:156823d33999 1481 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
<> 149:156823d33999 1482 {
<> 149:156823d33999 1483 /* Disable ADC end of single conversion interrupt on group injected */
<> 149:156823d33999 1484 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 149:156823d33999 1485
<> 149:156823d33999 1486 /* Set ADC state */
<> 149:156823d33999 1487 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 149:156823d33999 1488
<> 149:156823d33999 1489 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 149:156823d33999 1490 {
<> 149:156823d33999 1491 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 149:156823d33999 1492 }
<> 149:156823d33999 1493 }
<> 149:156823d33999 1494
<> 149:156823d33999 1495 /* Conversion complete callback */
<> 149:156823d33999 1496 HAL_ADCEx_InjectedConvCpltCallback(hadc);
<> 149:156823d33999 1497
<> 149:156823d33999 1498 /* Clear injected group conversion flag */
<> 149:156823d33999 1499 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
<> 149:156823d33999 1500 }
<> 149:156823d33999 1501 }
<> 149:156823d33999 1502
<> 149:156823d33999 1503 /* ========== Check Analog watchdog flags ========== */
<> 149:156823d33999 1504 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
<> 149:156823d33999 1505 {
<> 149:156823d33999 1506 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
<> 149:156823d33999 1507 {
<> 149:156823d33999 1508 /* Set ADC state */
<> 149:156823d33999 1509 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
<> 149:156823d33999 1510
<> 149:156823d33999 1511 /* Level out of window callback */
<> 149:156823d33999 1512 HAL_ADC_LevelOutOfWindowCallback(hadc);
<> 149:156823d33999 1513
<> 149:156823d33999 1514 /* Clear the ADC analog watchdog flag */
<> 149:156823d33999 1515 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
<> 149:156823d33999 1516 }
<> 149:156823d33999 1517 }
<> 149:156823d33999 1518
<> 149:156823d33999 1519 /* ========== Check Overrun flag ========== */
<> 149:156823d33999 1520 if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
<> 149:156823d33999 1521 {
<> 149:156823d33999 1522 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR))
<> 149:156823d33999 1523 {
<> 149:156823d33999 1524 /* Note: On STM32L1, ADC overrun can be set through other parameters */
<> 149:156823d33999 1525 /* refer to description of parameter "EOCSelection" for more */
<> 149:156823d33999 1526 /* details. */
<> 149:156823d33999 1527
<> 149:156823d33999 1528 /* Set ADC error code to overrun */
<> 149:156823d33999 1529 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
<> 149:156823d33999 1530
<> 149:156823d33999 1531 /* Clear ADC overrun flag */
<> 149:156823d33999 1532 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 149:156823d33999 1533
<> 149:156823d33999 1534 /* Error callback */
<> 149:156823d33999 1535 HAL_ADC_ErrorCallback(hadc);
<> 149:156823d33999 1536
<> 149:156823d33999 1537 /* Clear the Overrun flag */
<> 149:156823d33999 1538 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
<> 149:156823d33999 1539 }
<> 149:156823d33999 1540 }
<> 149:156823d33999 1541
<> 149:156823d33999 1542 }
<> 149:156823d33999 1543
<> 149:156823d33999 1544 /**
<> 149:156823d33999 1545 * @brief Conversion complete callback in non blocking mode
<> 149:156823d33999 1546 * @param hadc: ADC handle
<> 149:156823d33999 1547 * @retval None
<> 149:156823d33999 1548 */
<> 149:156823d33999 1549 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1550 {
<> 149:156823d33999 1551 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 1552 UNUSED(hadc);
<> 149:156823d33999 1553
<> 149:156823d33999 1554 /* NOTE : This function should not be modified. When the callback is needed,
<> 149:156823d33999 1555 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
<> 149:156823d33999 1556 */
<> 149:156823d33999 1557 }
<> 149:156823d33999 1558
<> 149:156823d33999 1559 /**
<> 149:156823d33999 1560 * @brief Conversion DMA half-transfer callback in non blocking mode
<> 149:156823d33999 1561 * @param hadc: ADC handle
<> 149:156823d33999 1562 * @retval None
<> 149:156823d33999 1563 */
<> 149:156823d33999 1564 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1565 {
<> 149:156823d33999 1566 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 1567 UNUSED(hadc);
<> 149:156823d33999 1568
<> 149:156823d33999 1569 /* NOTE : This function should not be modified. When the callback is needed,
<> 149:156823d33999 1570 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
<> 149:156823d33999 1571 */
<> 149:156823d33999 1572 }
<> 149:156823d33999 1573
<> 149:156823d33999 1574 /**
<> 149:156823d33999 1575 * @brief Analog watchdog callback in non blocking mode.
<> 149:156823d33999 1576 * @param hadc: ADC handle
<> 149:156823d33999 1577 * @retval None
<> 149:156823d33999 1578 */
<> 149:156823d33999 1579 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1580 {
<> 149:156823d33999 1581 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 1582 UNUSED(hadc);
<> 149:156823d33999 1583
<> 149:156823d33999 1584 /* NOTE : This function should not be modified. When the callback is needed,
<> 149:156823d33999 1585 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
<> 149:156823d33999 1586 */
<> 149:156823d33999 1587 }
<> 149:156823d33999 1588
<> 149:156823d33999 1589 /**
<> 149:156823d33999 1590 * @brief ADC error callback in non blocking mode
<> 149:156823d33999 1591 * (ADC conversion with interruption or transfer by DMA)
<> 149:156823d33999 1592 * @note In case of error due to overrun when using ADC with DMA transfer
<> 149:156823d33999 1593 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
<> 149:156823d33999 1594 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
<> 149:156823d33999 1595 * - If needed, restart a new ADC conversion using function
<> 149:156823d33999 1596 * "HAL_ADC_Start_DMA()"
<> 149:156823d33999 1597 * (this function is also clearing overrun flag)
<> 149:156823d33999 1598 * @param hadc: ADC handle
<> 149:156823d33999 1599 * @retval None
<> 149:156823d33999 1600 */
<> 149:156823d33999 1601 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
<> 149:156823d33999 1602 {
<> 149:156823d33999 1603 /* Prevent unused argument(s) compilation warning */
<> 149:156823d33999 1604 UNUSED(hadc);
<> 149:156823d33999 1605
<> 149:156823d33999 1606 /* NOTE : This function should not be modified. When the callback is needed,
<> 149:156823d33999 1607 function HAL_ADC_ErrorCallback must be implemented in the user file.
<> 149:156823d33999 1608 */
<> 149:156823d33999 1609 }
<> 149:156823d33999 1610
<> 149:156823d33999 1611
<> 149:156823d33999 1612 /**
<> 149:156823d33999 1613 * @}
<> 149:156823d33999 1614 */
<> 149:156823d33999 1615
<> 149:156823d33999 1616 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
<> 149:156823d33999 1617 * @brief Peripheral Control functions
<> 149:156823d33999 1618 *
<> 149:156823d33999 1619 @verbatim
<> 149:156823d33999 1620 ===============================================================================
<> 149:156823d33999 1621 ##### Peripheral Control functions #####
<> 149:156823d33999 1622 ===============================================================================
<> 149:156823d33999 1623 [..] This section provides functions allowing to:
<> 149:156823d33999 1624 (+) Configure channels on regular group
<> 149:156823d33999 1625 (+) Configure the analog watchdog
<> 149:156823d33999 1626
<> 149:156823d33999 1627 @endverbatim
<> 149:156823d33999 1628 * @{
<> 149:156823d33999 1629 */
<> 149:156823d33999 1630
<> 149:156823d33999 1631 /**
<> 149:156823d33999 1632 * @brief Configures the the selected channel to be linked to the regular
<> 149:156823d33999 1633 * group.
<> 149:156823d33999 1634 * @note In case of usage of internal measurement channels:
<> 149:156823d33999 1635 * Vbat/VrefInt/TempSensor.
<> 149:156823d33999 1636 * These internal paths can be be disabled using function
<> 149:156823d33999 1637 * HAL_ADC_DeInit().
<> 149:156823d33999 1638 * @note Possibility to update parameters on the fly:
<> 149:156823d33999 1639 * This function initializes channel into regular group, following
<> 149:156823d33999 1640 * calls to this function can be used to reconfigure some parameters
<> 149:156823d33999 1641 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
<> 149:156823d33999 1642 * the ADC.
<> 149:156823d33999 1643 * The setting of these parameters is conditioned to ADC state.
<> 149:156823d33999 1644 * For parameters constraints, see comments of structure
<> 149:156823d33999 1645 * "ADC_ChannelConfTypeDef".
<> 149:156823d33999 1646 * @param hadc: ADC handle
<> 149:156823d33999 1647 * @param sConfig: Structure of ADC channel for regular group.
<> 149:156823d33999 1648 * @retval HAL status
<> 149:156823d33999 1649 */
<> 149:156823d33999 1650 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
<> 149:156823d33999 1651 {
<> 149:156823d33999 1652 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 149:156823d33999 1653 __IO uint32_t wait_loop_index = 0;
<> 149:156823d33999 1654
<> 149:156823d33999 1655 /* Check the parameters */
<> 149:156823d33999 1656 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1657 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
<> 149:156823d33999 1658 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
<> 149:156823d33999 1659 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
<> 149:156823d33999 1660
<> 149:156823d33999 1661 /* Process locked */
<> 149:156823d33999 1662 __HAL_LOCK(hadc);
<> 149:156823d33999 1663
<> 149:156823d33999 1664
<> 149:156823d33999 1665 /* Regular sequence configuration */
<> 149:156823d33999 1666 /* For Rank 1 to 6 */
<> 149:156823d33999 1667 if (sConfig->Rank < 7)
<> 149:156823d33999 1668 {
<> 149:156823d33999 1669 MODIFY_REG(hadc->Instance->SQR5,
<> 149:156823d33999 1670 ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
<> 149:156823d33999 1671 ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
<> 149:156823d33999 1672 }
<> 149:156823d33999 1673 /* For Rank 7 to 12 */
<> 149:156823d33999 1674 else if (sConfig->Rank < 13)
<> 149:156823d33999 1675 {
<> 149:156823d33999 1676 MODIFY_REG(hadc->Instance->SQR4,
<> 149:156823d33999 1677 ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
<> 149:156823d33999 1678 ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
<> 149:156823d33999 1679 }
<> 149:156823d33999 1680 /* For Rank 13 to 18 */
<> 149:156823d33999 1681 else if (sConfig->Rank < 19)
<> 149:156823d33999 1682 {
<> 149:156823d33999 1683 MODIFY_REG(hadc->Instance->SQR3,
<> 149:156823d33999 1684 ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
<> 149:156823d33999 1685 ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
<> 149:156823d33999 1686 }
<> 149:156823d33999 1687 /* For Rank 19 to 24 */
<> 149:156823d33999 1688 else if (sConfig->Rank < 25)
<> 149:156823d33999 1689 {
<> 149:156823d33999 1690 MODIFY_REG(hadc->Instance->SQR2,
<> 149:156823d33999 1691 ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank),
<> 149:156823d33999 1692 ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
<> 149:156823d33999 1693 }
<> 149:156823d33999 1694 /* For Rank 25 to 28 */
<> 149:156823d33999 1695 else
<> 149:156823d33999 1696 {
<> 149:156823d33999 1697 MODIFY_REG(hadc->Instance->SQR1,
<> 149:156823d33999 1698 ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank),
<> 149:156823d33999 1699 ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
<> 149:156823d33999 1700 }
<> 149:156823d33999 1701
<> 149:156823d33999 1702
<> 149:156823d33999 1703 /* Channel sampling time configuration */
<> 149:156823d33999 1704 /* For channels 0 to 9 */
<> 149:156823d33999 1705 if (sConfig->Channel < ADC_CHANNEL_10)
<> 149:156823d33999 1706 {
<> 149:156823d33999 1707 MODIFY_REG(hadc->Instance->SMPR3,
<> 149:156823d33999 1708 ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
<> 149:156823d33999 1709 ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
<> 149:156823d33999 1710 }
<> 149:156823d33999 1711 /* For channels 10 to 19 */
<> 149:156823d33999 1712 else if (sConfig->Channel < ADC_CHANNEL_20)
<> 149:156823d33999 1713 {
<> 149:156823d33999 1714 MODIFY_REG(hadc->Instance->SMPR2,
<> 149:156823d33999 1715 ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
<> 149:156823d33999 1716 ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
<> 149:156823d33999 1717 }
<> 149:156823d33999 1718 /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
<> 149:156823d33999 1719 /* For channels 20 to 29 for devices Cat4, Cat.5 */
<> 149:156823d33999 1720 else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
<> 149:156823d33999 1721 {
<> 149:156823d33999 1722 MODIFY_REG(hadc->Instance->SMPR1,
<> 149:156823d33999 1723 ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel),
<> 149:156823d33999 1724 ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
<> 149:156823d33999 1725 }
<> 149:156823d33999 1726 /* For channels 30 to 31 for devices Cat4, Cat.5 */
<> 149:156823d33999 1727 else
<> 149:156823d33999 1728 {
<> 149:156823d33999 1729 ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
<> 149:156823d33999 1730 }
<> 149:156823d33999 1731
<> 149:156823d33999 1732 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
<> 149:156823d33999 1733 /* and VREFINT measurement path. */
<> 149:156823d33999 1734 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
<> 149:156823d33999 1735 (sConfig->Channel == ADC_CHANNEL_VREFINT) )
<> 149:156823d33999 1736 {
<> 149:156823d33999 1737 if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET)
<> 149:156823d33999 1738 {
<> 149:156823d33999 1739 SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
<> 149:156823d33999 1740
<> 149:156823d33999 1741 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
<> 149:156823d33999 1742 {
<> 149:156823d33999 1743 /* Delay for temperature sensor stabilization time */
<> 149:156823d33999 1744 /* Compute number of CPU cycles to wait for */
<> 149:156823d33999 1745 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 149:156823d33999 1746 while(wait_loop_index != 0)
<> 149:156823d33999 1747 {
<> 149:156823d33999 1748 wait_loop_index--;
<> 149:156823d33999 1749 }
<> 149:156823d33999 1750 }
<> 149:156823d33999 1751 }
<> 149:156823d33999 1752 }
<> 149:156823d33999 1753
<> 149:156823d33999 1754 /* Process unlocked */
<> 149:156823d33999 1755 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1756
<> 149:156823d33999 1757 /* Return function status */
<> 149:156823d33999 1758 return tmp_hal_status;
<> 149:156823d33999 1759 }
<> 149:156823d33999 1760
<> 149:156823d33999 1761 /**
<> 149:156823d33999 1762 * @brief Configures the analog watchdog.
<> 149:156823d33999 1763 * @note Analog watchdog thresholds can be modified while ADC conversion
<> 149:156823d33999 1764 * is on going.
<> 149:156823d33999 1765 * In this case, some constraints must be taken into account:
<> 149:156823d33999 1766 * the programmed threshold values are effective from the next
<> 149:156823d33999 1767 * ADC EOC (end of unitary conversion).
<> 149:156823d33999 1768 * Considering that registers write delay may happen due to
<> 149:156823d33999 1769 * bus activity, this might cause an uncertainty on the
<> 149:156823d33999 1770 * effective timing of the new programmed threshold values.
<> 149:156823d33999 1771 * @param hadc: ADC handle
<> 149:156823d33999 1772 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
<> 149:156823d33999 1773 * @retval HAL status
<> 149:156823d33999 1774 */
<> 149:156823d33999 1775 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
<> 149:156823d33999 1776 {
<> 149:156823d33999 1777 /* Check the parameters */
<> 149:156823d33999 1778 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 149:156823d33999 1779 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
<> 149:156823d33999 1780 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
<> 149:156823d33999 1781 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
<> 149:156823d33999 1782 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
<> 149:156823d33999 1783
<> 149:156823d33999 1784 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
<> 149:156823d33999 1785 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
<> 149:156823d33999 1786 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
<> 149:156823d33999 1787 {
<> 149:156823d33999 1788 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
<> 149:156823d33999 1789 }
<> 149:156823d33999 1790
<> 149:156823d33999 1791 /* Process locked */
<> 149:156823d33999 1792 __HAL_LOCK(hadc);
<> 149:156823d33999 1793
<> 149:156823d33999 1794 /* Analog watchdog configuration */
<> 149:156823d33999 1795
<> 149:156823d33999 1796 /* Configure ADC Analog watchdog interrupt */
<> 149:156823d33999 1797 if(AnalogWDGConfig->ITMode == ENABLE)
<> 149:156823d33999 1798 {
<> 149:156823d33999 1799 /* Enable the ADC Analog watchdog interrupt */
<> 149:156823d33999 1800 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
<> 149:156823d33999 1801 }
<> 149:156823d33999 1802 else
<> 149:156823d33999 1803 {
<> 149:156823d33999 1804 /* Disable the ADC Analog watchdog interrupt */
<> 149:156823d33999 1805 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
<> 149:156823d33999 1806 }
<> 149:156823d33999 1807
<> 149:156823d33999 1808 /* Configuration of analog watchdog: */
<> 149:156823d33999 1809 /* - Set the analog watchdog enable mode: regular and/or injected groups, */
<> 149:156823d33999 1810 /* one or all channels. */
<> 149:156823d33999 1811 /* - Set the Analog watchdog channel (is not used if watchdog */
<> 149:156823d33999 1812 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
<> 149:156823d33999 1813 hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL |
<> 149:156823d33999 1814 ADC_CR1_JAWDEN |
<> 149:156823d33999 1815 ADC_CR1_AWDEN |
<> 149:156823d33999 1816 ADC_CR1_AWDCH );
<> 149:156823d33999 1817
<> 149:156823d33999 1818 hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode |
<> 149:156823d33999 1819 AnalogWDGConfig->Channel );
<> 149:156823d33999 1820
<> 149:156823d33999 1821 /* Set the high threshold */
<> 149:156823d33999 1822 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
<> 149:156823d33999 1823
<> 149:156823d33999 1824 /* Set the low threshold */
<> 149:156823d33999 1825 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
<> 149:156823d33999 1826
<> 149:156823d33999 1827 /* Process unlocked */
<> 149:156823d33999 1828 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1829
<> 149:156823d33999 1830 /* Return function status */
<> 149:156823d33999 1831 return HAL_OK;
<> 149:156823d33999 1832 }
<> 149:156823d33999 1833
<> 149:156823d33999 1834
<> 149:156823d33999 1835 /**
<> 149:156823d33999 1836 * @}
<> 149:156823d33999 1837 */
<> 149:156823d33999 1838
<> 149:156823d33999 1839
<> 149:156823d33999 1840 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
<> 149:156823d33999 1841 * @brief Peripheral State functions
<> 149:156823d33999 1842 *
<> 149:156823d33999 1843 @verbatim
<> 149:156823d33999 1844 ===============================================================================
<> 149:156823d33999 1845 ##### Peripheral State and Errors functions #####
<> 149:156823d33999 1846 ===============================================================================
<> 149:156823d33999 1847 [..]
<> 149:156823d33999 1848 This subsection provides functions to get in run-time the status of the
<> 149:156823d33999 1849 peripheral.
<> 149:156823d33999 1850 (+) Check the ADC state
<> 149:156823d33999 1851 (+) Check the ADC error code
<> 149:156823d33999 1852
<> 149:156823d33999 1853 @endverbatim
<> 149:156823d33999 1854 * @{
<> 149:156823d33999 1855 */
<> 149:156823d33999 1856
<> 149:156823d33999 1857 /**
<> 149:156823d33999 1858 * @brief return the ADC state
<> 149:156823d33999 1859 * @param hadc: ADC handle
<> 149:156823d33999 1860 * @retval HAL state
<> 149:156823d33999 1861 */
<> 149:156823d33999 1862 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1863 {
<> 149:156823d33999 1864 /* Return ADC state */
<> 149:156823d33999 1865 return hadc->State;
<> 149:156823d33999 1866 }
<> 149:156823d33999 1867
<> 149:156823d33999 1868 /**
<> 149:156823d33999 1869 * @brief Return the ADC error code
<> 149:156823d33999 1870 * @param hadc: ADC handle
<> 149:156823d33999 1871 * @retval ADC Error Code
<> 149:156823d33999 1872 */
<> 149:156823d33999 1873 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
<> 149:156823d33999 1874 {
<> 149:156823d33999 1875 return hadc->ErrorCode;
<> 149:156823d33999 1876 }
<> 149:156823d33999 1877
<> 149:156823d33999 1878 /**
<> 149:156823d33999 1879 * @}
<> 149:156823d33999 1880 */
<> 149:156823d33999 1881
<> 149:156823d33999 1882 /**
<> 149:156823d33999 1883 * @}
<> 149:156823d33999 1884 */
<> 149:156823d33999 1885
<> 149:156823d33999 1886 /** @defgroup ADC_Private_Functions ADC Private Functions
<> 149:156823d33999 1887 * @{
<> 149:156823d33999 1888 */
<> 149:156823d33999 1889
<> 149:156823d33999 1890 /**
<> 149:156823d33999 1891 * @brief Enable the selected ADC.
<> 149:156823d33999 1892 * @note Prerequisite condition to use this function: ADC must be disabled
<> 149:156823d33999 1893 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
<> 149:156823d33999 1894 * @note If low power mode AutoPowerOff is enabled, power-on/off phases are
<> 149:156823d33999 1895 * performed automatically by hardware.
<> 149:156823d33999 1896 * In this mode, this function is useless and must not be called because
<> 149:156823d33999 1897 * flag ADC_FLAG_RDY is not usable.
<> 149:156823d33999 1898 * Therefore, this function must be called under condition of
<> 149:156823d33999 1899 * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
<> 149:156823d33999 1900 * @param hadc: ADC handle
<> 149:156823d33999 1901 * @retval HAL status.
<> 149:156823d33999 1902 */
<> 149:156823d33999 1903 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1904 {
<> 149:156823d33999 1905 uint32_t tickstart = 0;
<> 149:156823d33999 1906 __IO uint32_t wait_loop_index = 0;
<> 149:156823d33999 1907
<> 149:156823d33999 1908 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
<> 149:156823d33999 1909 /* enabling phase not yet completed: flag ADC ready not yet set). */
<> 149:156823d33999 1910 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
<> 149:156823d33999 1911 /* causes: ADC clock not running, ...). */
<> 149:156823d33999 1912 if (ADC_IS_ENABLE(hadc) == RESET)
<> 149:156823d33999 1913 {
<> 149:156823d33999 1914 /* Enable the Peripheral */
<> 149:156823d33999 1915 __HAL_ADC_ENABLE(hadc);
<> 149:156823d33999 1916
<> 149:156823d33999 1917 /* Delay for ADC stabilization time */
<> 149:156823d33999 1918 /* Compute number of CPU cycles to wait for */
<> 149:156823d33999 1919 wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
<> 149:156823d33999 1920 while(wait_loop_index != 0)
<> 149:156823d33999 1921 {
<> 149:156823d33999 1922 wait_loop_index--;
<> 149:156823d33999 1923 }
<> 149:156823d33999 1924
<> 149:156823d33999 1925 /* Get tick count */
<> 149:156823d33999 1926 tickstart = HAL_GetTick();
<> 149:156823d33999 1927
<> 149:156823d33999 1928 /* Wait for ADC effectively enabled */
<> 149:156823d33999 1929 while(ADC_IS_ENABLE(hadc) == RESET)
<> 149:156823d33999 1930 {
<> 149:156823d33999 1931 if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
<> 149:156823d33999 1932 {
<> 149:156823d33999 1933 /* Update ADC state machine to error */
<> 149:156823d33999 1934 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 149:156823d33999 1935
<> 149:156823d33999 1936 /* Set ADC error code to ADC IP internal error */
<> 149:156823d33999 1937 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 149:156823d33999 1938
<> 149:156823d33999 1939 /* Process unlocked */
<> 149:156823d33999 1940 __HAL_UNLOCK(hadc);
<> 149:156823d33999 1941
<> 149:156823d33999 1942 return HAL_ERROR;
<> 149:156823d33999 1943 }
<> 149:156823d33999 1944 }
<> 149:156823d33999 1945 }
<> 149:156823d33999 1946
<> 149:156823d33999 1947 /* Return HAL status */
<> 149:156823d33999 1948 return HAL_OK;
<> 149:156823d33999 1949 }
<> 149:156823d33999 1950
<> 149:156823d33999 1951 /**
<> 149:156823d33999 1952 * @brief Stop ADC conversion and disable the selected ADC
<> 149:156823d33999 1953 * @note Prerequisite condition to use this function: ADC conversions must be
<> 149:156823d33999 1954 * stopped to disable the ADC.
<> 149:156823d33999 1955 * @param hadc: ADC handle
<> 149:156823d33999 1956 * @retval HAL status.
<> 149:156823d33999 1957 */
<> 149:156823d33999 1958 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
<> 149:156823d33999 1959 {
<> 149:156823d33999 1960 uint32_t tickstart = 0;
<> 149:156823d33999 1961
<> 149:156823d33999 1962 /* Verification if ADC is not already disabled */
<> 149:156823d33999 1963 if (ADC_IS_ENABLE(hadc) != RESET)
<> 149:156823d33999 1964 {
<> 149:156823d33999 1965 /* Disable the ADC peripheral */
<> 149:156823d33999 1966 __HAL_ADC_DISABLE(hadc);
<> 149:156823d33999 1967
<> 149:156823d33999 1968 /* Get tick count */
<> 149:156823d33999 1969 tickstart = HAL_GetTick();
<> 149:156823d33999 1970
<> 149:156823d33999 1971 /* Wait for ADC effectively disabled */
<> 149:156823d33999 1972 while(ADC_IS_ENABLE(hadc) != RESET)
<> 149:156823d33999 1973 {
<> 149:156823d33999 1974 if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
<> 149:156823d33999 1975 {
<> 149:156823d33999 1976 /* Update ADC state machine to error */
<> 149:156823d33999 1977 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
<> 149:156823d33999 1978
<> 149:156823d33999 1979 /* Set ADC error code to ADC IP internal error */
<> 149:156823d33999 1980 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
<> 149:156823d33999 1981
<> 149:156823d33999 1982 return HAL_ERROR;
<> 149:156823d33999 1983 }
<> 149:156823d33999 1984 }
<> 149:156823d33999 1985 }
<> 149:156823d33999 1986
<> 149:156823d33999 1987 /* Return HAL status */
<> 149:156823d33999 1988 return HAL_OK;
<> 149:156823d33999 1989 }
<> 149:156823d33999 1990
<> 149:156823d33999 1991 /**
<> 149:156823d33999 1992 * @brief DMA transfer complete callback.
<> 149:156823d33999 1993 * @param hdma: pointer to DMA handle.
<> 149:156823d33999 1994 * @retval None
<> 149:156823d33999 1995 */
<> 149:156823d33999 1996 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 1997 {
<> 149:156823d33999 1998 /* Retrieve ADC handle corresponding to current DMA handle */
<> 149:156823d33999 1999 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 149:156823d33999 2000
<> 149:156823d33999 2001 /* Update state machine on conversion status if not in error state */
<> 149:156823d33999 2002 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
<> 149:156823d33999 2003 {
<> 149:156823d33999 2004 /* Update ADC state machine */
<> 149:156823d33999 2005 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
<> 149:156823d33999 2006
<> 149:156823d33999 2007 /* Determine whether any further conversion upcoming on group regular */
<> 149:156823d33999 2008 /* by external trigger, continuous mode or scan sequence on going. */
<> 149:156823d33999 2009 /* Note: On STM32L1, there is no independent flag of end of sequence. */
<> 149:156823d33999 2010 /* The test of scan sequence on going is done either with scan */
<> 149:156823d33999 2011 /* sequence disabled or with end of conversion flag set to */
<> 149:156823d33999 2012 /* of end of sequence. */
<> 149:156823d33999 2013 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 149:156823d33999 2014 (hadc->Init.ContinuousConvMode == DISABLE) &&
<> 149:156823d33999 2015 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
<> 149:156823d33999 2016 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
<> 149:156823d33999 2017 {
<> 149:156823d33999 2018 /* Disable ADC end of single conversion interrupt on group regular */
<> 149:156823d33999 2019 /* Note: Overrun interrupt was enabled with EOC interrupt in */
<> 149:156823d33999 2020 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */
<> 149:156823d33999 2021 /* by overrun IRQ process below. */
<> 149:156823d33999 2022 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
<> 149:156823d33999 2023
<> 149:156823d33999 2024 /* Set ADC state */
<> 149:156823d33999 2025 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
<> 149:156823d33999 2026
<> 149:156823d33999 2027 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
<> 149:156823d33999 2028 {
<> 149:156823d33999 2029 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 149:156823d33999 2030 }
<> 149:156823d33999 2031 }
<> 149:156823d33999 2032
<> 149:156823d33999 2033 /* Conversion complete callback */
<> 149:156823d33999 2034 HAL_ADC_ConvCpltCallback(hadc);
<> 149:156823d33999 2035 }
<> 149:156823d33999 2036 else
<> 149:156823d33999 2037 {
<> 149:156823d33999 2038 /* Call DMA error callback */
<> 149:156823d33999 2039 hadc->DMA_Handle->XferErrorCallback(hdma);
<> 149:156823d33999 2040 }
<> 149:156823d33999 2041 }
<> 149:156823d33999 2042
<> 149:156823d33999 2043 /**
<> 149:156823d33999 2044 * @brief DMA half transfer complete callback.
<> 149:156823d33999 2045 * @param hdma: pointer to DMA handle.
<> 149:156823d33999 2046 * @retval None
<> 149:156823d33999 2047 */
<> 149:156823d33999 2048 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 2049 {
<> 149:156823d33999 2050 /* Retrieve ADC handle corresponding to current DMA handle */
<> 149:156823d33999 2051 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 149:156823d33999 2052
<> 149:156823d33999 2053 /* Half conversion callback */
<> 149:156823d33999 2054 HAL_ADC_ConvHalfCpltCallback(hadc);
<> 149:156823d33999 2055 }
<> 149:156823d33999 2056
<> 149:156823d33999 2057 /**
<> 149:156823d33999 2058 * @brief DMA error callback
<> 149:156823d33999 2059 * @param hdma: pointer to DMA handle.
<> 149:156823d33999 2060 * @retval None
<> 149:156823d33999 2061 */
<> 149:156823d33999 2062 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 2063 {
<> 149:156823d33999 2064 /* Retrieve ADC handle corresponding to current DMA handle */
<> 149:156823d33999 2065 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 149:156823d33999 2066
<> 149:156823d33999 2067 /* Set ADC state */
<> 149:156823d33999 2068 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
<> 149:156823d33999 2069
<> 149:156823d33999 2070 /* Set ADC error code to DMA error */
<> 149:156823d33999 2071 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
<> 149:156823d33999 2072
<> 149:156823d33999 2073 /* Error callback */
<> 149:156823d33999 2074 HAL_ADC_ErrorCallback(hadc);
<> 149:156823d33999 2075 }
<> 149:156823d33999 2076
<> 149:156823d33999 2077 /**
<> 149:156823d33999 2078 * @}
<> 149:156823d33999 2079 */
<> 149:156823d33999 2080
<> 149:156823d33999 2081 #endif /* HAL_ADC_MODULE_ENABLED */
<> 149:156823d33999 2082 /**
<> 149:156823d33999 2083 * @}
<> 149:156823d33999 2084 */
<> 149:156823d33999 2085
<> 149:156823d33999 2086 /**
<> 149:156823d33999 2087 * @}
<> 149:156823d33999 2088 */
<> 149:156823d33999 2089
<> 149:156823d33999 2090 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/