Michael Fischler
Bouncing Betty Halloween Prop. A prop skull mounted with an mbed microcontroller armed to scare anyone who comes close to it. This project uses an infrared sonar, speaker, and, shiftbrite LEDs.
Dependencies: mbed wave_player
PowerControl/EthernetPowerControl.cpp@0:92661f51fe68, 2011-10-27 (annotated)
- Committer:
- mafischl
- Date:
- Thu Oct 27 07:19:10 2011 +0000
- Revision:
- 0:92661f51fe68
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mafischl | 0:92661f51fe68 | 1 | #include "EthernetPowerControl.h" |
| mafischl | 0:92661f51fe68 | 2 | |
| mafischl | 0:92661f51fe68 | 3 | static void write_PHY (unsigned int PhyReg, unsigned short Value) { |
| mafischl | 0:92661f51fe68 | 4 | /* Write a data 'Value' to PHY register 'PhyReg'. */ |
| mafischl | 0:92661f51fe68 | 5 | unsigned int tout; |
| mafischl | 0:92661f51fe68 | 6 | /* Hardware MII Management for LPC176x devices. */ |
| mafischl | 0:92661f51fe68 | 7 | LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; |
| mafischl | 0:92661f51fe68 | 8 | LPC_EMAC->MWTD = Value; |
| mafischl | 0:92661f51fe68 | 9 | |
| mafischl | 0:92661f51fe68 | 10 | /* Wait utill operation completed */ |
| mafischl | 0:92661f51fe68 | 11 | for (tout = 0; tout < MII_WR_TOUT; tout++) { |
| mafischl | 0:92661f51fe68 | 12 | if ((LPC_EMAC->MIND & MIND_BUSY) == 0) { |
| mafischl | 0:92661f51fe68 | 13 | break; |
| mafischl | 0:92661f51fe68 | 14 | } |
| mafischl | 0:92661f51fe68 | 15 | } |
| mafischl | 0:92661f51fe68 | 16 | } |
| mafischl | 0:92661f51fe68 | 17 | |
| mafischl | 0:92661f51fe68 | 18 | static unsigned short read_PHY (unsigned int PhyReg) { |
| mafischl | 0:92661f51fe68 | 19 | /* Read a PHY register 'PhyReg'. */ |
| mafischl | 0:92661f51fe68 | 20 | unsigned int tout, val; |
| mafischl | 0:92661f51fe68 | 21 | |
| mafischl | 0:92661f51fe68 | 22 | LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; |
| mafischl | 0:92661f51fe68 | 23 | LPC_EMAC->MCMD = MCMD_READ; |
| mafischl | 0:92661f51fe68 | 24 | |
| mafischl | 0:92661f51fe68 | 25 | /* Wait until operation completed */ |
| mafischl | 0:92661f51fe68 | 26 | for (tout = 0; tout < MII_RD_TOUT; tout++) { |
| mafischl | 0:92661f51fe68 | 27 | if ((LPC_EMAC->MIND & MIND_BUSY) == 0) { |
| mafischl | 0:92661f51fe68 | 28 | break; |
| mafischl | 0:92661f51fe68 | 29 | } |
| mafischl | 0:92661f51fe68 | 30 | } |
| mafischl | 0:92661f51fe68 | 31 | LPC_EMAC->MCMD = 0; |
| mafischl | 0:92661f51fe68 | 32 | val = LPC_EMAC->MRDD; |
| mafischl | 0:92661f51fe68 | 33 | |
| mafischl | 0:92661f51fe68 | 34 | return (val); |
| mafischl | 0:92661f51fe68 | 35 | } |
| mafischl | 0:92661f51fe68 | 36 | |
| mafischl | 0:92661f51fe68 | 37 | void EMAC_Init() |
| mafischl | 0:92661f51fe68 | 38 | { |
| mafischl | 0:92661f51fe68 | 39 | unsigned int tout,regv; |
| mafischl | 0:92661f51fe68 | 40 | /* Power Up the EMAC controller. */ |
| mafischl | 0:92661f51fe68 | 41 | Peripheral_PowerUp(LPC1768_PCONP_PCENET); |
| mafischl | 0:92661f51fe68 | 42 | |
| mafischl | 0:92661f51fe68 | 43 | LPC_PINCON->PINSEL2 = 0x50150105; |
| mafischl | 0:92661f51fe68 | 44 | LPC_PINCON->PINSEL3 &= ~0x0000000F; |
| mafischl | 0:92661f51fe68 | 45 | LPC_PINCON->PINSEL3 |= 0x00000005; |
| mafischl | 0:92661f51fe68 | 46 | |
| mafischl | 0:92661f51fe68 | 47 | /* Reset all EMAC internal modules. */ |
| mafischl | 0:92661f51fe68 | 48 | LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | |
| mafischl | 0:92661f51fe68 | 49 | MAC1_SIM_RES | MAC1_SOFT_RES; |
| mafischl | 0:92661f51fe68 | 50 | LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; |
| mafischl | 0:92661f51fe68 | 51 | |
| mafischl | 0:92661f51fe68 | 52 | /* A short delay after reset. */ |
| mafischl | 0:92661f51fe68 | 53 | for (tout = 100; tout; tout--); |
| mafischl | 0:92661f51fe68 | 54 | |
| mafischl | 0:92661f51fe68 | 55 | /* Initialize MAC control registers. */ |
| mafischl | 0:92661f51fe68 | 56 | LPC_EMAC->MAC1 = MAC1_PASS_ALL; |
| mafischl | 0:92661f51fe68 | 57 | LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; |
| mafischl | 0:92661f51fe68 | 58 | LPC_EMAC->MAXF = ETH_MAX_FLEN; |
| mafischl | 0:92661f51fe68 | 59 | LPC_EMAC->CLRT = CLRT_DEF; |
| mafischl | 0:92661f51fe68 | 60 | LPC_EMAC->IPGR = IPGR_DEF; |
| mafischl | 0:92661f51fe68 | 61 | |
| mafischl | 0:92661f51fe68 | 62 | /* Enable Reduced MII interface. */ |
| mafischl | 0:92661f51fe68 | 63 | LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; |
| mafischl | 0:92661f51fe68 | 64 | |
| mafischl | 0:92661f51fe68 | 65 | /* Reset Reduced MII Logic. */ |
| mafischl | 0:92661f51fe68 | 66 | LPC_EMAC->SUPP = SUPP_RES_RMII; |
| mafischl | 0:92661f51fe68 | 67 | for (tout = 100; tout; tout--); |
| mafischl | 0:92661f51fe68 | 68 | LPC_EMAC->SUPP = 0; |
| mafischl | 0:92661f51fe68 | 69 | |
| mafischl | 0:92661f51fe68 | 70 | /* Put the DP83848C in reset mode */ |
| mafischl | 0:92661f51fe68 | 71 | write_PHY (PHY_REG_BMCR, 0x8000); |
| mafischl | 0:92661f51fe68 | 72 | |
| mafischl | 0:92661f51fe68 | 73 | /* Wait for hardware reset to end. */ |
| mafischl | 0:92661f51fe68 | 74 | for (tout = 0; tout < 0x100000; tout++) { |
| mafischl | 0:92661f51fe68 | 75 | regv = read_PHY (PHY_REG_BMCR); |
| mafischl | 0:92661f51fe68 | 76 | if (!(regv & 0x8000)) { |
| mafischl | 0:92661f51fe68 | 77 | /* Reset complete */ |
| mafischl | 0:92661f51fe68 | 78 | break; |
| mafischl | 0:92661f51fe68 | 79 | } |
| mafischl | 0:92661f51fe68 | 80 | } |
| mafischl | 0:92661f51fe68 | 81 | } |
| mafischl | 0:92661f51fe68 | 82 | |
| mafischl | 0:92661f51fe68 | 83 | |
| mafischl | 0:92661f51fe68 | 84 | void PHY_PowerDown() |
| mafischl | 0:92661f51fe68 | 85 | { |
| mafischl | 0:92661f51fe68 | 86 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| mafischl | 0:92661f51fe68 | 87 | EMAC_Init(); //init EMAC if it is not already init'd |
| mafischl | 0:92661f51fe68 | 88 | |
| mafischl | 0:92661f51fe68 | 89 | unsigned int regv; |
| mafischl | 0:92661f51fe68 | 90 | regv = read_PHY(PHY_REG_BMCR); |
| mafischl | 0:92661f51fe68 | 91 | write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN)); |
| mafischl | 0:92661f51fe68 | 92 | regv = read_PHY(PHY_REG_BMCR); |
| mafischl | 0:92661f51fe68 | 93 | |
| mafischl | 0:92661f51fe68 | 94 | //shouldn't need the EMAC now. |
| mafischl | 0:92661f51fe68 | 95 | Peripheral_PowerDown(LPC1768_PCONP_PCENET); |
| mafischl | 0:92661f51fe68 | 96 | |
| mafischl | 0:92661f51fe68 | 97 | //and turn off the PHY OSC |
| mafischl | 0:92661f51fe68 | 98 | LPC_GPIO1->FIODIR |= 0x8000000; |
| mafischl | 0:92661f51fe68 | 99 | LPC_GPIO1->FIOCLR = 0x8000000; |
| mafischl | 0:92661f51fe68 | 100 | } |
| mafischl | 0:92661f51fe68 | 101 | |
| mafischl | 0:92661f51fe68 | 102 | void PHY_PowerUp() |
| mafischl | 0:92661f51fe68 | 103 | { |
| mafischl | 0:92661f51fe68 | 104 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| mafischl | 0:92661f51fe68 | 105 | EMAC_Init(); //init EMAC if it is not already init'd |
| mafischl | 0:92661f51fe68 | 106 | |
| mafischl | 0:92661f51fe68 | 107 | LPC_GPIO1->FIODIR |= 0x8000000; |
| mafischl | 0:92661f51fe68 | 108 | LPC_GPIO1->FIOSET = 0x8000000; |
| mafischl | 0:92661f51fe68 | 109 | |
| mafischl | 0:92661f51fe68 | 110 | //wait for osc to be stable |
| mafischl | 0:92661f51fe68 | 111 | wait_ms(200); |
| mafischl | 0:92661f51fe68 | 112 | |
| mafischl | 0:92661f51fe68 | 113 | unsigned int regv; |
| mafischl | 0:92661f51fe68 | 114 | regv = read_PHY(PHY_REG_BMCR); |
| mafischl | 0:92661f51fe68 | 115 | write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN)); |
| mafischl | 0:92661f51fe68 | 116 | regv = read_PHY(PHY_REG_BMCR); |
| mafischl | 0:92661f51fe68 | 117 | } |
| mafischl | 0:92661f51fe68 | 118 | |
| mafischl | 0:92661f51fe68 | 119 | void PHY_EnergyDetect_Enable() |
| mafischl | 0:92661f51fe68 | 120 | { |
| mafischl | 0:92661f51fe68 | 121 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| mafischl | 0:92661f51fe68 | 122 | EMAC_Init(); //init EMAC if it is not already init'd |
| mafischl | 0:92661f51fe68 | 123 | |
| mafischl | 0:92661f51fe68 | 124 | unsigned int regv; |
| mafischl | 0:92661f51fe68 | 125 | regv = read_PHY(PHY_REG_EDCR); |
| mafischl | 0:92661f51fe68 | 126 | write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE)); |
| mafischl | 0:92661f51fe68 | 127 | regv = read_PHY(PHY_REG_EDCR); |
| mafischl | 0:92661f51fe68 | 128 | } |
| mafischl | 0:92661f51fe68 | 129 | |
| mafischl | 0:92661f51fe68 | 130 | void PHY_EnergyDetect_Disable() |
| mafischl | 0:92661f51fe68 | 131 | { |
| mafischl | 0:92661f51fe68 | 132 | if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) |
| mafischl | 0:92661f51fe68 | 133 | EMAC_Init(); //init EMAC if it is not already init'd |
| mafischl | 0:92661f51fe68 | 134 | unsigned int regv; |
| mafischl | 0:92661f51fe68 | 135 | regv = read_PHY(PHY_REG_EDCR); |
| mafischl | 0:92661f51fe68 | 136 | write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE)); |
| mafischl | 0:92661f51fe68 | 137 | regv = read_PHY(PHY_REG_EDCR); |
| mafischl | 0:92661f51fe68 | 138 | } |