lzbp li
++
Fork of
mbed-stm32l0/l1-src
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lzbp li
Revision 631:ff681937ffd8, committed 2015-09-28
- Comitter:
- mbed_official
- Date:
- Mon Sep 28 13:00:10 2015 +0100
- Parent:
- 630:825f75ca301e
- Child:
- 632:7687fb9c4f91
- Commit message:
- Synchronized with git revision 1be56c8134a3ed6004f149a84f658de45dda6a5c
Full URL: https://github.com/mbedmicro/mbed/commit/1be56c8134a3ed6004f149a84f658de45dda6a5c/
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/W7500.sct Mon Sep 28 13:00:10 2015 +0100
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00004000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/startup_W7500x.S Mon Sep 28 13:00:10 2015 +0100 @@ -0,0 +1,213 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_MICRO/sys.cpp Mon Sep 28 13:00:10 2015 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/W7500.sct Mon Sep 28 13:00:10 2015 +0100
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00004000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/startup_W7500x.S Mon Sep 28 13:00:10 2015 +0100 @@ -0,0 +1,186 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM0.s +; * @brief CMSIS Cortex-M0 Core Device Startup File for +; * Device CMSDK_CM0 +; * @version V3.01 +; * @date 06. March 2012 +; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER + +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler PROC + EXPORT SSP0_Handler [WEAK] + EXPORT SSP1_Handler [WEAK] + EXPORT UART0_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT UART2_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT PORT0_Handler [WEAK] + EXPORT PORT1_Handler [WEAK] + EXPORT PORT2_Handler [WEAK] + EXPORT PORT3_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT DUALTIMER0_Handler [WEAK] + EXPORT DUALTIMER1_Handler [WEAK] + EXPORT PWM0_Handler [WEAK] + EXPORT PWM1_Handler [WEAK] + EXPORT PWM2_Handler [WEAK] + EXPORT PWM3_Handler [WEAK] + EXPORT PWM4_Handler [WEAK] + EXPORT PWM5_Handler [WEAK] + EXPORT PWM6_Handler [WEAK] + EXPORT PWM7_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT WZTOE_Handler [WEAK] + EXPORT EXTI_Handler [WEAK] +SSP0_Handler +SSP1_Handler +UART0_Handler +UART1_Handler +UART2_Handler +I2C0_Handler +I2C1_Handler +PORT0_Handler +PORT1_Handler +PORT2_Handler +PORT3_Handler +DMA_Handler +DUALTIMER0_Handler +DUALTIMER1_Handler +PWM0_Handler +PWM1_Handler +PWM2_Handler +PWM3_Handler +PWM4_Handler +PWM5_Handler +PWM6_Handler +PWM7_Handler +RTC_Handler +ADC_Handler +WZTOE_Handler +EXTI_Handler + B . + ENDP + + + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_ARM_STD/sys.cpp Mon Sep 28 13:00:10 2015 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/W7500.ld Mon Sep 28 13:00:10 2015 +0100
@@ -0,0 +1,152 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/TOOLCHAIN_GCC_ARM/startup_W7500.S Mon Sep 28 13:00:10 2015 +0100 @@ -0,0 +1,259 @@ +/* File: startup_W7500.s + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.4 + * Date: 20 Dezember 2012 + * + */ +/* Copyright (c) 2011 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 + +/* +// <h> Stack Configuration +// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x200 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +// <h> Heap Configuration +// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// </h> +*/ + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + +/* Vector Table */ + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long SSP0_Handler /* 16+ 0: SSP 0 Handler */ + .long SSP1_Handler /* 16+ 1: SSP 1 Handler */ + .long UART0_Handler /* 16+ 2: UART 0 Handler */ + .long UART1_Handler /* 16+ 3: UART 1 Handler */ + .long UART2_Handler /* 16+ 4: UART 2 Handler */ + .long I2C0_Handler /* 16+ 5: I2C 0 Handler */ + .long I2C1_Handler /* 16+ 6: I2C 1 Handler */ + .long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */ + .long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */ + .long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */ + .long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */ + .long DMA_Handler /* 16+11: DMA Combined Handler */ + .long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */ + .long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */ + .long PWM0_Handler /* 16+ 14: PWM0 Handler */ + .long PWM1_Handler /* 16+ 15: PWM1 Handler */ + .long PWM2_Handler /* 16+ 16: PWM2 Handler */ + .long PWM3_Handler /* 16+ 17: PWM3 Handler */ + .long PWM4_Handler /* 16+ 18: PWM4 Handler */ + .long PWM5_Handler /* 16+ 19: PWM5 Handler */ + .long PWM6_Handler /* 16+ 20: PWM6 Handler */ + .long PWM7_Handler /* 16+ 21: PWM7 Handler */ + .long RTC_Handler /* 16+ 22: RTC Handler */ + .long ADC_Handler /* 16+ 23: ADC Handler */ + .long WZTOE_Handler /* 16+ 24: WZTOE Handler */ + .long EXTI_Handler /* 16+ 25: EXTI Handler */ + + .size __isr_vector, . - __isr_vector +/* Reset Handler */ + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + subs r2, r1 + ble .LC3 + + movs r0, 0 +.LC2: + str r0, [r1, r2] + subs r2, 4 + bge .LC2 +.LC3: +#endif /* __STARTUP_CLEAR_BSS */ + + /*bl _start*/ + bl main + + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* System Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + +/* IRQ Handlers */ + + def_default_handler SSP0_Handler + def_default_handler SSP1_Handler + def_default_handler UART0_Handler + def_default_handler UART1_Handler + def_default_handler UART2_Handler + def_default_handler I2C0_Handler + def_default_handler I2C1_Handler + def_default_handler PORT0_Handler + def_default_handler PORT1_Handler + def_default_handler PORT2_Handler + def_default_handler PORT3_Handler + + def_default_handler DMA_Handler + def_default_handler DUALTIMER0_Handler + def_default_handler DUALTIMER1_Handler + def_default_handler PWM0_Handler + def_default_handler PWM1_Handler + def_default_handler PWM2_Handler + def_default_handler PWM3_Handler + def_default_handler PWM4_Handler + def_default_handler PWM5_Handler + def_default_handler PWM6_Handler + def_default_handler PWM7_Handler + def_default_handler RTC_Handler + def_default_handler ADC_Handler + def_default_handler WZTOE_Handler + def_default_handler EXTI_Handler + + /* + def_default_handler Default_Handler + .weak DEF_IRQHandler + .set DEF_IRQHandler, Default_Handler + */ + + .end +
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h Mon Sep 28 10:45:10 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/PeripheralNames.h Mon Sep 28 13:00:10 2015 +0100
@@ -43,7 +43,8 @@
typedef enum {
UART_0 = (int)W7500x_UART0_BASE,
- UART_1 = (int)W7500x_UART1_BASE
+ UART_1 = (int)W7500x_UART1_BASE,
+ UART_2 = (int)W7500x_UART2_BASE
} UARTName;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PeripheralPins.c Mon Sep 28 13:00:10 2015 +0100
@@ -0,0 +1,132 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+
+
+//*** ADC ***
+const PinMap PinMap_ADC[] = {
+ {PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0
+ {PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1
+ {PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2
+ {PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3
+ {PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4
+ {PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5
+ {PC_9 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN6
+ {PC_8 , ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN7
+ {NC, NC, 0}
+};
+
+
+//*** SERIAL ***
+const PinMap PinMap_UART_TX[] = {
+ {PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PC_10, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+ {PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {PC_11, UART_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+const PinMap PinMap_I2C_SDA[] = {
+ {PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PA_6, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ {PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_8, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_4, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PA_5, I2C_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_SCLK[] = {
+ {PA_6 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_1 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_13, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_12, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ {PA_8 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_3 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_15, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_14, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ {PA_7 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_2 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_14, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_13, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ {PA_5 , SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PB_0 , SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_12, SPI_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_11, SPI_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , 0}
+};
+
+const PinMap PinMap_PWM[] = {
+ {PA_0 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_1 , PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PA_5 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_7 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_8 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_9 , PWM_6, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PA_10, PWM_7, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF3)},
+ {PC_0 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_2 , PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_4 , PWM_4, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_5 , PWM_5, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {PC_8 , PWM_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
+ {PC_10, PWM_2, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF2)},
+ {NC , NC , WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)}
+};
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/PinNames.h Mon Sep 28 13:00:10 2015 +0100
@@ -0,0 +1,230 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM
+#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE) << 8) | ((PUPD) << 4) | ((AFNUM) << 0)))
+#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F)
+#define WIZ_PIN_AFNUM(X) (((X) >> 0) & 0x0F)
+#define WIZ_PIN_MODE(X) (((X) >> 8) & 0x0F)
+#define WIZ_MODE_INPUT (0)
+#define WIZ_MODE_OUTPUT (1)
+#define WIZ_MODE_AF (2)
+
+#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */
+#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */
+#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */
+#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */
+
+
+#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D)
+#define WIZ_PIN_NUM(X) ((uint32_t)(X) & 0xF) // pin number
+#define WIZ_PIN_INDEX(X) (1 << ((uint32_t)(X) & 0xF)) // pin index : flag bit
+
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+
+typedef enum {
+ // W7500x PORT[5:4] + PIN[3:0])
+ PA_0 = 0x000,
+ PA_1 = 0x001,
+ PA_2 = 0x002,
+ PA_3 = 0x003,
+ PA_4 = 0x004,
+ PA_5 = 0x005,
+ PA_6 = 0x006,
+ PA_7 = 0x007,
+ PA_8 = 0x008,
+ PA_9 = 0x009,
+ PA_10 = 0x00A,
+ PA_11 = 0x00B,
+ PA_12 = 0x00C,
+ PA_13 = 0x00D,
+ PA_14 = 0x00E,
+ PA_15 = 0x00F,
+
+ PB_0 = 0x010,
+ PB_1 = 0x011,
+ PB_2 = 0x012,
+ PB_3 = 0x013,
+ PB_4 = 0x014,
+ PB_5 = 0x015,
+ PB_6 = 0x016,
+ PB_7 = 0x017,
+ PB_8 = 0x018,
+ PB_9 = 0x019,
+ PB_10 = 0x01A,
+ PB_11 = 0x01B,
+ PB_12 = 0x01C,
+ PB_13 = 0x01D,
+ PB_14 = 0x01E,
+ PB_15 = 0x01F,
+
+ PC_0 = 0x020,
+ PC_1 = 0x021,
+ PC_2 = 0x022,
+ PC_3 = 0x023,
+ PC_4 = 0x024,
+ PC_5 = 0x025,
+ PC_6 = 0x026,
+ PC_7 = 0x027,
+ PC_8 = 0x028,
+ PC_9 = 0x029,
+
+ PC_10 = 0x02A,
+ PC_11 = 0x02B,
+ PC_12 = 0x02C,
+ PC_13 = 0x02D,
+ PC_14 = 0x02E,
+ PC_15 = 0x02F,
+
+ PD_0 = 0x030,
+ PD_1 = 0x031,
+ PD_2 = 0x032,
+ PD_3 = 0x033,
+ PD_4 = 0x034,
+
+ PA_00 = PA_0,
+ PA_01 = PA_1,
+ PA_02 = PA_2,
+ PA_03 = PA_3,
+ PA_04 = PA_4,
+ PA_05 = PA_5,
+ PA_06 = PA_6,
+ PA_07 = PA_7,
+ PA_08 = PA_8,
+ PA_09 = PA_9,
+
+ PB_00 = PB_0,
+ PB_01 = PB_1,
+ PB_02 = PB_2,
+ PB_03 = PB_3,
+ PB_04 = PB_4,
+ PB_05 = PB_5,
+ PB_06 = PB_6,
+ PB_07 = PB_7,
+ PB_08 = PB_8,
+ PB_09 = PB_9,
+
+ PC_00 = PC_0,
+ PC_01 = PC_1,
+ PC_02 = PC_2,
+ PC_03 = PC_3,
+ PC_04 = PC_4,
+ PC_05 = PC_5,
+ PC_06 = PC_6,
+ PC_07 = PC_7,
+ PC_08 = PC_8,
+ PC_09 = PC_9,
+
+ PD_00 = PD_0,
+ PD_01 = PD_1,
+ PD_02 = PD_2,
+ PD_03 = PD_3,
+ PD_04 = PD_4,
+
+ // Arduino connector namings
+ A0 = PC_15, // AIN0
+ A1 = PC_14, // AIN1
+ A2 = PC_13, // AIN2
+ A3 = PC_12, // AIN3
+ A4 = PC_9, // AIN4
+ A5 = PC_8, // AIN5
+
+ D0 = PA_14,
+ D1 = PA_13,
+ D2 = PC_3,
+ D3 = PC_2,
+ D4 = PA_2,
+ D5 = PA_1,
+ D6 = PA_0,
+ D7 = PA_12,
+ D8 = PA_11,
+ D9 = PC_1,
+ D10 = PA_5,
+ D11 = PA_8,
+ D12 = PA_7,
+ D13 = PA_6,
+ D14 = PA_10,
+ D15 = PA_9,
+
+ // Generic signals namings
+ LED_RED = PC_0,
+ LED_GREEN = PC_4,
+ LED_BLUE = PC_5,
+
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+ LED4 = LED_BLUE,
+
+ LEDR = LED_RED,
+ LEDG = LED_GREEN,
+ LEDB = LED_BLUE,
+
+ USBTX = PC_10,
+ USBRX = PC_11,
+
+ //Use SPI1
+ SD_SEL = PB_0, // SPI1_CS
+ SD_CLK = PB_1, // SPI1_CLK
+ SD_MISO = PB_2, // MOSI1
+ SD_MOSI = PB_3, // MISO1
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 2,
+ PullDefault = PullNone
+} PinMode;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device.h Mon Sep 28 13:00:10 2015 +0100 @@ -0,0 +1,78 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 // Not present on this device + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_RTC 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SLEEP 0 + +#define DEVICE_ETHERNET 0 + + +//======================================= + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define STDIO_UART_TX PC_10 +#define STDIO_UART_RX PC_11 +#define STDIO_UART UART_2 + +#define DEVICE_ERROR_RED 0 + +#include "objects.h" + +#endif
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c Mon Sep 28 10:45:10 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c Mon Sep 28 13:00:10 2015 +0100
@@ -208,13 +208,24 @@
uint32_t S_UART_Init(uint32_t baud)
{
uint32_t tmpreg=0x00;
- uint32_t uartclock = 0x00, integer_baud = 0x00;
+
+ S_UART_SetBaud(baud);
- assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode));
+ tmpreg = UART2->CTRL;
+ tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
+ tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
+ UART2->CTRL = tmpreg;
+
+ return 0;
+}
+
+void S_UART_SetBaud(uint32_t baud)
+{
+ uint32_t uartclock = 0x00, integer_baud = 0x00;
if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK)
{
- uartclock = INTERN_XTAL;
+ uartclock = INTERN_XTAL;
}
else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK)
{
@@ -227,18 +238,11 @@
integer_baud = (uint32_t)(uartclock / baud);
UART2->BAUDDIV = integer_baud;
-
- tmpreg = UART2->CTRL;
- tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
- tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
- UART2->CTRL = tmpreg;
-
- return 0;
}
void S_UART_SendData(uint16_t Data)
{
- while(UART2->STATE & S_UART_STATE_TX_BUF_FULL);
+ while(UART2->STATE & S_UART_STATE_TX_BUF_FULL);
UART2->DATA = Data;
}
@@ -248,13 +252,13 @@
}
-FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG)
+FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_STATE)
{
FlagStatus bitstatus = RESET;
- assert_param(IS_S_UART_FLAG(S_UART_FLAG));
+ assert_param(IS_S_UART_STATE(S_UART_STATE));
- if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET)
+ if ((UART2->STATE & S_UART_STATE) != (FlagStatus)RESET)
{
bitstatus = SET;
}
@@ -266,28 +270,40 @@
return bitstatus;
}
-
-void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState)
+void S_UART_SetCTRL(uint16_t S_UART_CTRL, FunctionalState NewState)
{
- assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
-
if ( NewState != DISABLE )
{
- UART2->CTRL |= S_UART_IT;
+ UART2->CTRL |= S_UART_CTRL;
}
else
{
- UART2->CTRL &= ~(S_UART_IT);
+ UART2->CTRL &= ~(S_UART_CTRL);
}
}
-ITStatus S_UART_GetITStatus(uint16_t S_UART_IT)
+
+void S_UART_ITConfig(uint16_t S_UART_CTRL, FunctionalState NewState)
+{
+ assert_param(IS_S_UART_CTRL_FLAG(S_UART_CTRL));
+
+ if ( NewState != DISABLE )
+ {
+ UART2->CTRL |= S_UART_CTRL;
+ }
+ else
+ {
+ UART2->CTRL &= ~(S_UART_CTRL);
+ }
+}
+
+ITStatus S_UART_GetITStatus(uint16_t S_UART_INTSTATUS)
{
ITStatus bitstatus = RESET;
- assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
+ assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS));
- if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET)
+ if ((UART2->INT.STATUS & (S_UART_INTSTATUS)) != (uint16_t) RESET)
{
bitstatus = SET;
}
@@ -299,11 +315,11 @@
return bitstatus;
}
-void S_UART_ClearITPendingBit(uint16_t S_UART_IT)
+void S_UART_ClearITPendingBit(uint16_t S_UART_INTSTATUS)
{
- assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
+ assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS));
- UART2->INT.CLEAR |= (S_UART_IT >> 2);
+ UART2->INT.CLEAR |= (S_UART_INTSTATUS);
}
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h Mon Sep 28 10:45:10 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h Mon Sep 28 13:00:10 2015 +0100
@@ -224,12 +224,32 @@
/** @addtogroup S_UART_Flags
* @{
*/
-#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */
-#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */
-#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */
-#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */
-#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \
- ((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF))
+#define S_UART_STATE_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */
+#define S_UART_STATE_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */
+#define S_UART_STATE_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */
+#define S_UART_STATE_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */
+#define IS_S_UART_STATE(FLAG) (((FLAG) == S_UART_STATE_RXO) || ((FLAG) == S_UART_STATE_TXO) || \
+ ((FLAG) == S_UART_STATE_RXF) || ((FLAG) == S_UART_STATE_TXF))
+/**
+ * @}
+ */
+
+
+/** @addtogroup S_UART_CTRL_Flags
+ * @{
+ */
+
+#define S_UART_CTRL_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */
+#define S_UART_CTRL_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */
+#define S_UART_CTRL_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */
+#define S_UART_CTRL_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */
+#define S_UART_CTRL_RX ((uint16_t)0x01UL << 1) /*!< RX */
+#define S_UART_CTRL_TX ((uint16_t)0x01UL << 0) /*!< TX */
+
+
+#define IS_S_UART_CTRL_FLAG(FLAG) (((FLAG) == S_UART_CTRL_FLAG_RXOI) || ((FLAG) == S_UART_CTRL_FLAG_TXOI) || \
+ ((FLAG) == S_UART_CTRL_FLAG_RXI) || ((FLAG) == S_UART_CTRL_FLAG_TXI) || \
+ ((FLAG) == S_UART_CTRL_FLAG_RX) || ((FLAG) == S_UART_CTRL_FLAG_TX))
/**
* @}
*/
@@ -239,13 +259,12 @@
* @{
*/
-#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */
-#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */
-#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */
-#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */
-#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \
- ((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI))
-
+#define S_UART_INTSTATUS_RXOI ((uint16_t)0x01UL << 3) /*!< RX overrun interrupt */
+#define S_UART_INTSTATUS_TXOI ((uint16_t)0x01UL << 2) /*!< TX overrun interrupt */
+#define S_UART_INTSTATUS_RXI ((uint16_t)0x01UL << 1) /*!< RX interrupt */
+#define S_UART_INTSTATUS_TXI ((uint16_t)0x01UL << 0) /*!< TX interrupt */
+#define IS_S_UART_INTSTATUS(FLAG) (((FLAG) == S_UART_INTSTATUS_RXOI) || ((FLAG) == S_UART_INTSTATUS_TXOI) || \
+ ((FLAG) == S_UART_INTSTATUS_RXI) || ((FLAG) == S_UART_INTSTATUS_TXI))
/**
* @}
*/
@@ -263,21 +282,26 @@
ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT);
void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT);
-
-void S_UART_DeInit(void);
-uint32_t S_UART_Init(uint32_t baud);
-void S_UART_SendData(uint16_t Data);
-uint16_t S_UART_ReceiveData(void);
-
-
-
uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch);
void UartPuts (UART_TypeDef* UARTx, uint8_t *str);
uint8_t UartGetc (UART_TypeDef* UARTx);
-uint8_t S_UartPutc(uint8_t ch);
-void S_UartPuts(uint8_t *str);
-uint8_t S_UartGetc(void);
+void S_UART_DeInit (void);
+uint32_t S_UART_Init (uint32_t baud);
+void S_UART_SetBaud (uint32_t baud);
+void S_UART_SetCTRL (uint16_t S_UART_CTRL, FunctionalState NewState);
+void S_UART_SendData (uint16_t Data);
+uint16_t S_UART_ReceiveData(void);
+
+uint8_t S_UartPutc (uint8_t ch);
+void S_UartPuts (uint8_t *str);
+uint8_t S_UartGetc (void);
+
+FlagStatus S_UART_GetFlagStatus (uint16_t S_UART_STATE);
+void S_UART_ITConfig (uint16_t S_UART_CTRL, FunctionalState NewState);
+
+ITStatus S_UART_GetITStatus (uint16_t S_UART_IT);
+void S_UART_ClearITPendingBit(uint16_t S_UART_IT);
#ifdef __cplusplus
--- a/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c Mon Sep 28 10:45:10 2015 +0100
+++ b/targets/hal/TARGET_WIZNET/TARGET_W7500x/serial_api.c Mon Sep 28 13:00:10 2015 +0100
@@ -39,9 +39,9 @@
#include "PeripheralPins.h"
#include "W7500x_uart.h"
-#define UART_NUM (2)
+#define UART_NUM (3)
-static uint32_t serial_irq_ids[UART_NUM] = {0, 0};
+static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0};
static uart_irq_handler irq_handler;
@@ -55,23 +55,46 @@
static void init_uart(serial_t *obj)
{
- UART = (UART_TypeDef *)(obj->uart);
- UART_InitStructure.UART_BaudRate = obj->baudrate;
- UART_InitStructure.UART_WordLength = obj->databits;
- UART_InitStructure.UART_StopBits = obj->stopbits;
- UART_InitStructure.UART_Parity = obj->parity;
- UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
+ if(obj->index == 2) // For UART2, It is simple UART.
+ {
+ SystemCoreClockUpdate();
+ //S_UART_Init(obj->baudrate);
+ S_UART_SetCTRL((S_UART_CTRL_RX_EN|S_UART_CTRL_TX_EN), DISABLE);
+ S_UART_SetBaud(obj->baudrate);
+
+ if(obj->pin_rx == NC)
+ {
+ S_UART_SetCTRL(S_UART_CTRL_TX_EN, ENABLE);
+ }
+ else if(obj->pin_tx == NC)
+ {
+ S_UART_SetCTRL(S_UART_CTRL_RX_EN, ENABLE);
+ }
+ else
+ {
+ S_UART_SetCTRL((S_UART_CTRL_TX_EN|S_UART_CTRL_RX_EN),ENABLE);
+ }
+ }
+ else // For UART0 and UART1.
+ {
+ UART = (UART_TypeDef *)(obj->uart);
+ UART_InitStructure.UART_BaudRate = obj->baudrate;
+ UART_InitStructure.UART_WordLength = obj->databits;
+ UART_InitStructure.UART_StopBits = obj->stopbits;
+ UART_InitStructure.UART_Parity = obj->parity;
+ UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
- if (obj->pin_rx == NC) {
- UART_InitStructure.UART_Mode = UART_Mode_Tx;
- } else if (obj->pin_tx == NC) {
- UART_InitStructure.UART_Mode = UART_Mode_Rx;
- } else {
- UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx);
+ if (obj->pin_rx == NC) {
+ UART_InitStructure.UART_Mode = UART_Mode_Tx;
+ } else if (obj->pin_tx == NC) {
+ UART_InitStructure.UART_Mode = UART_Mode_Rx;
+ } else {
+ UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx);
+ }
+
+ UART_Init(UART,&UART_InitStructure);
}
-
- UART_Init(UART,&UART_InitStructure);
}
void serial_init(serial_t *obj, PinName tx, PinName rx)
@@ -94,6 +117,10 @@
obj->index = 1;
}
+ if (obj->uart == UART_2) {
+ obj->index = 2;
+ }
+
// Configure the UART pins
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
@@ -131,11 +158,8 @@
if (obj->uart == UART_1) {
}
-
-
- // Configure GPIOs
-// pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-// pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ if (obj->uart == UART_2) {
+ }
serial_irq_ids[obj->index] = 0;
}
@@ -195,6 +219,20 @@
}
}
+static void uart2_irq()
+{
+ if(serial_irq_ids[2] != 0){
+ if( S_UART_GetITStatus(S_UART_INTSTATUS_TXI) != RESET ){
+ S_UART_ClearITPendingBit(S_UART_INTSTATUS_TXI);
+ irq_handler(serial_irq_ids[2], TxIrq);
+ }
+ if( S_UART_GetITStatus(S_UART_INTSTATUS_RXI) != RESET ) {
+ S_UART_ClearITPendingBit(S_UART_INTSTATUS_RXI);
+ irq_handler(serial_irq_ids[2], RxIrq);
+ }
+ }
+}
+
#ifdef __cplusplus
extern "C"{
#endif
@@ -207,6 +245,11 @@
{
uart_irq(UART_1, 1);
}
+
+void UART2_Handler()
+{
+ uart2_irq();
+}
#ifdef __cplusplus
}
#endif
@@ -222,28 +265,49 @@
{
IRQn_Type irq_n = (IRQn_Type)0;
- UART = (UART_TypeDef *)(obj->uart);
- if (obj->uart == UART_0) {
- irq_n = UART0_IRQn;
- }
+ if (obj->uart == UART_2)
+ {
+ irq_n = UART2_IRQn;
- if (obj->uart == UART_1) {
- irq_n = UART1_IRQn;
+ if (enable){
+ if (irq == RxIrq){
+ S_UART_ITConfig(S_UART_CTRL_RXI,ENABLE);
+ } else {
+ S_UART_ITConfig(S_UART_CTRL_TXI,ENABLE);
+ }
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ S_UART_ITConfig((S_UART_CTRL_RXI|S_UART_CTRL_TXI),DISABLE);
+ NVIC_DisableIRQ(irq_n);
+ }
}
-
- if (enable) {
- if (irq == RxIrq) {
- UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE);
- } else { // TxIrq
- UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE);
+ else
+ {
+ UART = (UART_TypeDef *)(obj->uart);
+
+ if (obj->uart == UART_0) {
+ irq_n = UART0_IRQn;
}
- NVIC_ClearPendingIRQ(irq_n);
- NVIC_EnableIRQ(irq_n);
- } else { // disable
- UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE);
- NVIC_DisableIRQ(irq_n);
+ if (obj->uart == UART_1) {
+ irq_n = UART1_IRQn;
+ }
+
+ if (enable) {
+ if (irq == RxIrq) {
+ UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE);
+ } else { // TxIrq
+ UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE);
+ }
+
+ NVIC_ClearPendingIRQ(irq_n);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE);
+ NVIC_DisableIRQ(irq_n);
+ }
}
}
@@ -253,36 +317,74 @@
int serial_getc(serial_t *obj)
{
- UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
-// while(!serial_readable(obj));
- while(uart->FR & UART_FR_RXFE);
+ if (obj->uart == UART_2)
+ {
+ S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart);
- return (uart->DR & 0xFF);
+ while( (uart->STATE & S_UART_STATE_RX_BUF_FULL) == 0 );
+ return (uint16_t)(uart->DATA);
+ }
+ else
+ {
+ UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
+ while(uart->FR & UART_FR_RXFE);
+
+ return (uart->DR & 0xFF);
+ }
}
void serial_putc(serial_t *obj, int c)
{
- UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
+ if (obj->uart == UART_2)
+ {
+ S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart);
- uart->DR = (uint32_t)(c & (uint16_t)0xFF);
- while(uart->FR & UART_FR_BUSY);
+ while(uart->STATE & S_UART_STATE_TX_BUF_FULL);
+ uart->DATA = (uint32_t)(c & (uint16_t)0xFF);
+ }
+ else
+ {
+ UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
+
+ uart->DR = (uint32_t)(c & (uint16_t)0xFF);
+ while(uart->FR & UART_FR_BUSY);
+ }
}
int serial_readable(serial_t *obj)
{
int status;
- UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
- // Check if data is received
- status = ((uart->FR & UART_FR_RXFE) ? 0: 1);
+
+ if (obj->uart == UART_2)
+ {
+ S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart);
+ status = ((uart->STATE & S_UART_STATE_RX_BUF_FULL) ? 1 : 0);
+ }
+ else
+ {
+ UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
+ // Check if data is received
+ status = ((uart->FR & UART_FR_RXFE) ? 0: 1);
+ }
+
return status;
}
int serial_writable(serial_t *obj)
{
int status;
- UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
- // Check if data is transmitted
- status = ((uart->FR & UART_FR_BUSY) ? 0: 1);
+
+ if (obj->uart == UART_2)
+ {
+ S_UART_TypeDef *uart = (S_UART_TypeDef *)(obj->uart);
+ status = ((uart->STATE & S_UART_STATE_TX_BUF_FULL) ? 0 : 1);
+ }
+ else
+ {
+ UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
+ // Check if data is transmitted
+ status = ((uart->FR & UART_FR_BUSY) ? 0: 1);
+ }
return status;
}