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targets/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.s@482:d9a48e768ce0, 2015-02-27 (annotated)

Committer:
mbed_official
Date:
Fri Feb 27 10:00:08 2015 +0000
Revision:
482:d9a48e768ce0
Child:
502:542898c8d189
Synchronized with git revision 43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c



Full URL: https://github.com/mbedmicro/mbed/commit/43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c/



RZ/A1H - Modify to support GCC and Fix some bugs of driver.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 482:d9a48e768ce0 1 /* Copyright (c) 2009 - 2012 ARM LIMITED
mbed_official 482:d9a48e768ce0 2
mbed_official 482:d9a48e768ce0 3 All rights reserved.
mbed_official 482:d9a48e768ce0 4 Redistribution and use in source and binary forms, with or without
mbed_official 482:d9a48e768ce0 5 modification, are permitted provided that the following conditions are met:
mbed_official 482:d9a48e768ce0 6 - Redistributions of source code must retain the above copyright
mbed_official 482:d9a48e768ce0 7 notice, this list of conditions and the following disclaimer.
mbed_official 482:d9a48e768ce0 8 - Redistributions in binary form must reproduce the above copyright
mbed_official 482:d9a48e768ce0 9 notice, this list of conditions and the following disclaimer in the
mbed_official 482:d9a48e768ce0 10 documentation and/or other materials provided with the distribution.
mbed_official 482:d9a48e768ce0 11 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 482:d9a48e768ce0 12 to endorse or promote products derived from this software without
mbed_official 482:d9a48e768ce0 13 specific prior written permission.
mbed_official 482:d9a48e768ce0 14 *
mbed_official 482:d9a48e768ce0 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 482:d9a48e768ce0 16 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 482:d9a48e768ce0 17 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 482:d9a48e768ce0 18 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 482:d9a48e768ce0 19 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 482:d9a48e768ce0 20 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 482:d9a48e768ce0 21 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 482:d9a48e768ce0 22 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 482:d9a48e768ce0 23 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 482:d9a48e768ce0 24 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 482:d9a48e768ce0 25 POSSIBILITY OF SUCH DAMAGE.
mbed_official 482:d9a48e768ce0 26 ---------------------------------------------------------------------------*/
mbed_official 482:d9a48e768ce0 27
mbed_official 482:d9a48e768ce0 28 /*----------------------------------------------------------------------------
mbed_official 482:d9a48e768ce0 29 * Functions
mbed_official 482:d9a48e768ce0 30 *---------------------------------------------------------------------------*/
mbed_official 482:d9a48e768ce0 31 .text
mbed_official 482:d9a48e768ce0 32 .global __v7_all_cache
mbed_official 482:d9a48e768ce0 33 /*
mbed_official 482:d9a48e768ce0 34 * __STATIC_ASM void __v7_all_cache(uint32_t op) {
mbed_official 482:d9a48e768ce0 35 */
mbed_official 482:d9a48e768ce0 36 __v7_all_cache:
mbed_official 482:d9a48e768ce0 37 .arm
mbed_official 482:d9a48e768ce0 38
mbed_official 482:d9a48e768ce0 39 PUSH {R4-R11}
mbed_official 482:d9a48e768ce0 40
mbed_official 482:d9a48e768ce0 41 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
mbed_official 482:d9a48e768ce0 42 ANDS R3, R6, #0x07000000 // Extract coherency level
mbed_official 482:d9a48e768ce0 43 MOV R3, R3, LSR #23 // Total cache levels << 1
mbed_official 482:d9a48e768ce0 44 BEQ Finished // If 0, no need to clean
mbed_official 482:d9a48e768ce0 45
mbed_official 482:d9a48e768ce0 46 MOV R10, #0 // R10 holds current cache level << 1
mbed_official 482:d9a48e768ce0 47 Loop1: ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
mbed_official 482:d9a48e768ce0 48 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
mbed_official 482:d9a48e768ce0 49 AND R1, R1, #7 // Isolate those lower 3 bits
mbed_official 482:d9a48e768ce0 50 CMP R1, #2
mbed_official 482:d9a48e768ce0 51 BLT Skip // No cache or only instruction cache at this level
mbed_official 482:d9a48e768ce0 52
mbed_official 482:d9a48e768ce0 53 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
mbed_official 482:d9a48e768ce0 54 ISB // ISB to sync the change to the CacheSizeID reg
mbed_official 482:d9a48e768ce0 55 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
mbed_official 482:d9a48e768ce0 56 AND R2, R1, #7 // Extract the line length field
mbed_official 482:d9a48e768ce0 57 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
mbed_official 482:d9a48e768ce0 58 LDR R4, =0x3FF
mbed_official 482:d9a48e768ce0 59 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
mbed_official 482:d9a48e768ce0 60 CLZ R5, R4 // R5 is the bit position of the way size increment
mbed_official 482:d9a48e768ce0 61 LDR R7, =0x7FFF
mbed_official 482:d9a48e768ce0 62 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
mbed_official 482:d9a48e768ce0 63
mbed_official 482:d9a48e768ce0 64 Loop2: MOV R9, R4 // R9 working copy of the max way size (right aligned)
mbed_official 482:d9a48e768ce0 65
mbed_official 482:d9a48e768ce0 66 Loop3: ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
mbed_official 482:d9a48e768ce0 67 ORR R11, R11, R7, LSL R2 // Factor in the Set number
mbed_official 482:d9a48e768ce0 68 CMP R0, #0
mbed_official 482:d9a48e768ce0 69 BNE Dccsw
mbed_official 482:d9a48e768ce0 70 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
mbed_official 482:d9a48e768ce0 71 B cont
mbed_official 482:d9a48e768ce0 72 Dccsw: CMP R0, #1
mbed_official 482:d9a48e768ce0 73 BNE Dccisw
mbed_official 482:d9a48e768ce0 74 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
mbed_official 482:d9a48e768ce0 75 B cont
mbed_official 482:d9a48e768ce0 76 Dccisw: MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
mbed_official 482:d9a48e768ce0 77 cont: SUBS R9, R9, #1 // Decrement the Way number
mbed_official 482:d9a48e768ce0 78 BGE Loop3
mbed_official 482:d9a48e768ce0 79 SUBS R7, R7, #1 // Decrement the Set number
mbed_official 482:d9a48e768ce0 80 BGE Loop2
mbed_official 482:d9a48e768ce0 81 Skip: ADD R10, R10, #2 // increment the cache number
mbed_official 482:d9a48e768ce0 82 CMP R3, R10
mbed_official 482:d9a48e768ce0 83 BGT Loop1
mbed_official 482:d9a48e768ce0 84
mbed_official 482:d9a48e768ce0 85 Finished:
mbed_official 482:d9a48e768ce0 86 DSB
mbed_official 482:d9a48e768ce0 87 POP {R4-R11}
mbed_official 482:d9a48e768ce0 88 BX lr
mbed_official 482:d9a48e768ce0 89
mbed_official 482:d9a48e768ce0 90
mbed_official 482:d9a48e768ce0 91 .END
mbed_official 482:d9a48e768ce0 92 /*----------------------------------------------------------------------------
mbed_official 482:d9a48e768ce0 93 * end of file
mbed_official 482:d9a48e768ce0 94 *---------------------------------------------------------------------------*/