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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_lcd.h@525:c320967f86b9, 2015-04-28 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 28 11:45:12 2015 +0100
- Revision:
- 525:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553
Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/
Add in Silicon Labs targets with asynchronous API support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 525:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 2 | * @file efm32gg_lcd.h |
| mbed_official | 525:c320967f86b9 | 3 | * @brief EFM32GG_LCD register and bit field definitions |
| mbed_official | 525:c320967f86b9 | 4 | * @version 3.20.6 |
| mbed_official | 525:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 6 | * @section License |
| mbed_official | 525:c320967f86b9 | 7 | * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 525:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 9 | * |
| mbed_official | 525:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 525:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 525:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 525:c320967f86b9 | 13 | * |
| mbed_official | 525:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 525:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 525:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 525:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 525:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 525:c320967f86b9 | 19 | * |
| mbed_official | 525:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 525:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 525:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 525:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 525:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 525:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 525:c320967f86b9 | 26 | * |
| mbed_official | 525:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 525:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 525:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 525:c320967f86b9 | 30 | * |
| mbed_official | 525:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 33 | * @defgroup EFM32GG_LCD |
| mbed_official | 525:c320967f86b9 | 34 | * @{ |
| mbed_official | 525:c320967f86b9 | 35 | * @brief EFM32GG_LCD Register Declaration |
| mbed_official | 525:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 37 | typedef struct |
| mbed_official | 525:c320967f86b9 | 38 | { |
| mbed_official | 525:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 525:c320967f86b9 | 40 | __IO uint32_t DISPCTRL; /**< Display Control Register */ |
| mbed_official | 525:c320967f86b9 | 41 | __IO uint32_t SEGEN; /**< Segment Enable Register */ |
| mbed_official | 525:c320967f86b9 | 42 | __IO uint32_t BACTRL; /**< Blink and Animation Control Register */ |
| mbed_official | 525:c320967f86b9 | 43 | __I uint32_t STATUS; /**< Status Register */ |
| mbed_official | 525:c320967f86b9 | 44 | __IO uint32_t AREGA; /**< Animation Register A */ |
| mbed_official | 525:c320967f86b9 | 45 | __IO uint32_t AREGB; /**< Animation Register B */ |
| mbed_official | 525:c320967f86b9 | 46 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 525:c320967f86b9 | 47 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 525:c320967f86b9 | 48 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 525:c320967f86b9 | 49 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 525:c320967f86b9 | 50 | |
| mbed_official | 525:c320967f86b9 | 51 | uint32_t RESERVED0[5]; /**< Reserved for future use **/ |
| mbed_official | 525:c320967f86b9 | 52 | __IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */ |
| mbed_official | 525:c320967f86b9 | 53 | __IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */ |
| mbed_official | 525:c320967f86b9 | 54 | __IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */ |
| mbed_official | 525:c320967f86b9 | 55 | __IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */ |
| mbed_official | 525:c320967f86b9 | 56 | __IO uint32_t SEGD0H; /**< Segment Data High Register 0 */ |
| mbed_official | 525:c320967f86b9 | 57 | __IO uint32_t SEGD1H; /**< Segment Data High Register 1 */ |
| mbed_official | 525:c320967f86b9 | 58 | __IO uint32_t SEGD2H; /**< Segment Data High Register 2 */ |
| mbed_official | 525:c320967f86b9 | 59 | __IO uint32_t SEGD3H; /**< Segment Data High Register 3 */ |
| mbed_official | 525:c320967f86b9 | 60 | |
| mbed_official | 525:c320967f86b9 | 61 | __IO uint32_t FREEZE; /**< Freeze Register */ |
| mbed_official | 525:c320967f86b9 | 62 | __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| mbed_official | 525:c320967f86b9 | 63 | |
| mbed_official | 525:c320967f86b9 | 64 | uint32_t RESERVED1[19]; /**< Reserved for future use **/ |
| mbed_official | 525:c320967f86b9 | 65 | __IO uint32_t SEGD4H; /**< Segment Data High Register 4 */ |
| mbed_official | 525:c320967f86b9 | 66 | __IO uint32_t SEGD5H; /**< Segment Data High Register 5 */ |
| mbed_official | 525:c320967f86b9 | 67 | __IO uint32_t SEGD6H; /**< Segment Data High Register 6 */ |
| mbed_official | 525:c320967f86b9 | 68 | __IO uint32_t SEGD7H; /**< Segment Data High Register 7 */ |
| mbed_official | 525:c320967f86b9 | 69 | uint32_t RESERVED2[2]; /**< Reserved for future use **/ |
| mbed_official | 525:c320967f86b9 | 70 | __IO uint32_t SEGD4L; /**< Segment Data Low Register 4 */ |
| mbed_official | 525:c320967f86b9 | 71 | __IO uint32_t SEGD5L; /**< Segment Data Low Register 5 */ |
| mbed_official | 525:c320967f86b9 | 72 | __IO uint32_t SEGD6L; /**< Segment Data Low Register 6 */ |
| mbed_official | 525:c320967f86b9 | 73 | __IO uint32_t SEGD7L; /**< Segment Data Low Register 7 */ |
| mbed_official | 525:c320967f86b9 | 74 | } LCD_TypeDef; /** @} */ |
| mbed_official | 525:c320967f86b9 | 75 | |
| mbed_official | 525:c320967f86b9 | 76 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 77 | * @defgroup EFM32GG_LCD_BitFields |
| mbed_official | 525:c320967f86b9 | 78 | * @{ |
| mbed_official | 525:c320967f86b9 | 79 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 80 | |
| mbed_official | 525:c320967f86b9 | 81 | /* Bit fields for LCD CTRL */ |
| mbed_official | 525:c320967f86b9 | 82 | #define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 83 | #define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 84 | #define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */ |
| mbed_official | 525:c320967f86b9 | 85 | #define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */ |
| mbed_official | 525:c320967f86b9 | 86 | #define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ |
| mbed_official | 525:c320967f86b9 | 87 | #define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 88 | #define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 89 | #define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ |
| mbed_official | 525:c320967f86b9 | 90 | #define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ |
| mbed_official | 525:c320967f86b9 | 91 | #define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 92 | #define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 93 | #define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 94 | #define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 95 | #define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 96 | #define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 97 | #define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 98 | #define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 99 | #define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */ |
| mbed_official | 525:c320967f86b9 | 100 | #define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */ |
| mbed_official | 525:c320967f86b9 | 101 | #define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */ |
| mbed_official | 525:c320967f86b9 | 102 | #define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 103 | #define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 104 | |
| mbed_official | 525:c320967f86b9 | 105 | /* Bit fields for LCD DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 106 | #define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 107 | #define _LCD_DISPCTRL_MASK 0x005D9F1FUL /**< Mask for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 108 | #define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ |
| mbed_official | 525:c320967f86b9 | 109 | #define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */ |
| mbed_official | 525:c320967f86b9 | 110 | #define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 111 | #define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 112 | #define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 113 | #define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 114 | #define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 115 | #define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 116 | #define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 117 | #define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 118 | #define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 119 | #define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 120 | #define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */ |
| mbed_official | 525:c320967f86b9 | 121 | #define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */ |
| mbed_official | 525:c320967f86b9 | 122 | #define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 123 | #define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 124 | #define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 125 | #define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 126 | #define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 127 | #define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 128 | #define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 129 | #define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 130 | #define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 131 | #define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 2) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 132 | #define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ |
| mbed_official | 525:c320967f86b9 | 133 | #define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ |
| mbed_official | 525:c320967f86b9 | 134 | #define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ |
| mbed_official | 525:c320967f86b9 | 135 | #define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 136 | #define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 137 | #define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 138 | #define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 139 | #define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 140 | #define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 141 | #define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */ |
| mbed_official | 525:c320967f86b9 | 142 | #define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */ |
| mbed_official | 525:c320967f86b9 | 143 | #define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 144 | #define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 145 | #define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 146 | #define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 147 | #define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 148 | #define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 149 | #define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */ |
| mbed_official | 525:c320967f86b9 | 150 | #define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */ |
| mbed_official | 525:c320967f86b9 | 151 | #define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */ |
| mbed_official | 525:c320967f86b9 | 152 | #define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 153 | #define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 154 | #define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 155 | #define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 156 | #define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 157 | #define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 158 | #define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */ |
| mbed_official | 525:c320967f86b9 | 159 | #define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */ |
| mbed_official | 525:c320967f86b9 | 160 | #define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */ |
| mbed_official | 525:c320967f86b9 | 161 | #define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 162 | #define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 163 | #define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 164 | #define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 165 | #define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 166 | #define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 167 | #define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */ |
| mbed_official | 525:c320967f86b9 | 168 | #define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */ |
| mbed_official | 525:c320967f86b9 | 169 | #define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 170 | #define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 171 | #define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 172 | #define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 173 | #define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 174 | #define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 175 | #define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 176 | #define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 177 | #define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 178 | #define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 179 | #define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 180 | #define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 181 | #define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 182 | #define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 183 | #define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 184 | #define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 185 | #define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 186 | #define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 187 | #define LCD_DISPCTRL_MUXE (0x1UL << 22) /**< Extended Mux Configuration */ |
| mbed_official | 525:c320967f86b9 | 188 | #define _LCD_DISPCTRL_MUXE_SHIFT 22 /**< Shift value for LCD_MUXE */ |
| mbed_official | 525:c320967f86b9 | 189 | #define _LCD_DISPCTRL_MUXE_MASK 0x400000UL /**< Bit mask for LCD_MUXE */ |
| mbed_official | 525:c320967f86b9 | 190 | #define _LCD_DISPCTRL_MUXE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 191 | #define _LCD_DISPCTRL_MUXE_MUX 0x00000000UL /**< Mode MUX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 192 | #define _LCD_DISPCTRL_MUXE_MUXE 0x00000001UL /**< Mode MUXE for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 193 | #define LCD_DISPCTRL_MUXE_DEFAULT (_LCD_DISPCTRL_MUXE_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 194 | #define LCD_DISPCTRL_MUXE_MUX (_LCD_DISPCTRL_MUXE_MUX << 22) /**< Shifted mode MUX for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 195 | #define LCD_DISPCTRL_MUXE_MUXE (_LCD_DISPCTRL_MUXE_MUXE << 22) /**< Shifted mode MUXE for LCD_DISPCTRL */ |
| mbed_official | 525:c320967f86b9 | 196 | |
| mbed_official | 525:c320967f86b9 | 197 | /* Bit fields for LCD SEGEN */ |
| mbed_official | 525:c320967f86b9 | 198 | #define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */ |
| mbed_official | 525:c320967f86b9 | 199 | #define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */ |
| mbed_official | 525:c320967f86b9 | 200 | #define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */ |
| mbed_official | 525:c320967f86b9 | 201 | #define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */ |
| mbed_official | 525:c320967f86b9 | 202 | #define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */ |
| mbed_official | 525:c320967f86b9 | 203 | #define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */ |
| mbed_official | 525:c320967f86b9 | 204 | |
| mbed_official | 525:c320967f86b9 | 205 | /* Bit fields for LCD BACTRL */ |
| mbed_official | 525:c320967f86b9 | 206 | #define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 207 | #define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 208 | #define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ |
| mbed_official | 525:c320967f86b9 | 209 | #define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ |
| mbed_official | 525:c320967f86b9 | 210 | #define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ |
| mbed_official | 525:c320967f86b9 | 211 | #define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 212 | #define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 213 | #define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ |
| mbed_official | 525:c320967f86b9 | 214 | #define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ |
| mbed_official | 525:c320967f86b9 | 215 | #define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ |
| mbed_official | 525:c320967f86b9 | 216 | #define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 217 | #define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 218 | #define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ |
| mbed_official | 525:c320967f86b9 | 219 | #define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ |
| mbed_official | 525:c320967f86b9 | 220 | #define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ |
| mbed_official | 525:c320967f86b9 | 221 | #define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 222 | #define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 223 | #define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ |
| mbed_official | 525:c320967f86b9 | 224 | #define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ |
| mbed_official | 525:c320967f86b9 | 225 | #define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 226 | #define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 227 | #define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 228 | #define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 229 | #define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 230 | #define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 231 | #define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 232 | #define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 233 | #define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ |
| mbed_official | 525:c320967f86b9 | 234 | #define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ |
| mbed_official | 525:c320967f86b9 | 235 | #define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 236 | #define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 237 | #define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 238 | #define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 239 | #define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 240 | #define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 241 | #define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 242 | #define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 243 | #define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ |
| mbed_official | 525:c320967f86b9 | 244 | #define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ |
| mbed_official | 525:c320967f86b9 | 245 | #define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ |
| mbed_official | 525:c320967f86b9 | 246 | #define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 247 | #define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 248 | #define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 249 | #define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 250 | #define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 251 | #define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 252 | #define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ |
| mbed_official | 525:c320967f86b9 | 253 | #define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ |
| mbed_official | 525:c320967f86b9 | 254 | #define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ |
| mbed_official | 525:c320967f86b9 | 255 | #define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 256 | #define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 257 | #define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ |
| mbed_official | 525:c320967f86b9 | 258 | #define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ |
| mbed_official | 525:c320967f86b9 | 259 | #define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 260 | #define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 261 | #define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 262 | #define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 263 | #define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 264 | #define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 265 | #define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 266 | #define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 267 | #define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 268 | #define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 269 | #define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ |
| mbed_official | 525:c320967f86b9 | 270 | #define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ |
| mbed_official | 525:c320967f86b9 | 271 | #define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 272 | #define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 273 | #define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */ |
| mbed_official | 525:c320967f86b9 | 274 | #define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */ |
| mbed_official | 525:c320967f86b9 | 275 | #define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */ |
| mbed_official | 525:c320967f86b9 | 276 | #define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 277 | #define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 278 | #define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 279 | #define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 280 | #define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 281 | #define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 282 | |
| mbed_official | 525:c320967f86b9 | 283 | /* Bit fields for LCD STATUS */ |
| mbed_official | 525:c320967f86b9 | 284 | #define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ |
| mbed_official | 525:c320967f86b9 | 285 | #define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */ |
| mbed_official | 525:c320967f86b9 | 286 | #define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ |
| mbed_official | 525:c320967f86b9 | 287 | #define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ |
| mbed_official | 525:c320967f86b9 | 288 | #define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ |
| mbed_official | 525:c320967f86b9 | 289 | #define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ |
| mbed_official | 525:c320967f86b9 | 290 | #define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ |
| mbed_official | 525:c320967f86b9 | 291 | #define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ |
| mbed_official | 525:c320967f86b9 | 292 | #define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ |
| mbed_official | 525:c320967f86b9 | 293 | #define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ |
| mbed_official | 525:c320967f86b9 | 294 | #define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ |
| mbed_official | 525:c320967f86b9 | 295 | |
| mbed_official | 525:c320967f86b9 | 296 | /* Bit fields for LCD AREGA */ |
| mbed_official | 525:c320967f86b9 | 297 | #define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 298 | #define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 299 | #define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 300 | #define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 301 | #define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 302 | #define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 303 | |
| mbed_official | 525:c320967f86b9 | 304 | /* Bit fields for LCD AREGB */ |
| mbed_official | 525:c320967f86b9 | 305 | #define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 306 | #define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 307 | #define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 308 | #define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 309 | #define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 310 | #define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 311 | |
| mbed_official | 525:c320967f86b9 | 312 | /* Bit fields for LCD IF */ |
| mbed_official | 525:c320967f86b9 | 313 | #define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ |
| mbed_official | 525:c320967f86b9 | 314 | #define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */ |
| mbed_official | 525:c320967f86b9 | 315 | #define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 316 | #define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 317 | #define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 318 | #define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ |
| mbed_official | 525:c320967f86b9 | 319 | #define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ |
| mbed_official | 525:c320967f86b9 | 320 | |
| mbed_official | 525:c320967f86b9 | 321 | /* Bit fields for LCD IFS */ |
| mbed_official | 525:c320967f86b9 | 322 | #define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */ |
| mbed_official | 525:c320967f86b9 | 323 | #define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */ |
| mbed_official | 525:c320967f86b9 | 324 | #define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */ |
| mbed_official | 525:c320967f86b9 | 325 | #define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 326 | #define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 327 | #define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */ |
| mbed_official | 525:c320967f86b9 | 328 | #define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */ |
| mbed_official | 525:c320967f86b9 | 329 | |
| mbed_official | 525:c320967f86b9 | 330 | /* Bit fields for LCD IFC */ |
| mbed_official | 525:c320967f86b9 | 331 | #define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */ |
| mbed_official | 525:c320967f86b9 | 332 | #define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */ |
| mbed_official | 525:c320967f86b9 | 333 | #define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */ |
| mbed_official | 525:c320967f86b9 | 334 | #define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 335 | #define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 336 | #define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */ |
| mbed_official | 525:c320967f86b9 | 337 | #define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */ |
| mbed_official | 525:c320967f86b9 | 338 | |
| mbed_official | 525:c320967f86b9 | 339 | /* Bit fields for LCD IEN */ |
| mbed_official | 525:c320967f86b9 | 340 | #define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ |
| mbed_official | 525:c320967f86b9 | 341 | #define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */ |
| mbed_official | 525:c320967f86b9 | 342 | #define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 343 | #define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 344 | #define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ |
| mbed_official | 525:c320967f86b9 | 345 | #define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ |
| mbed_official | 525:c320967f86b9 | 346 | #define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ |
| mbed_official | 525:c320967f86b9 | 347 | |
| mbed_official | 525:c320967f86b9 | 348 | /* Bit fields for LCD SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 349 | #define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 350 | #define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 351 | #define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 352 | #define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 353 | #define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 354 | #define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 355 | |
| mbed_official | 525:c320967f86b9 | 356 | /* Bit fields for LCD SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 357 | #define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 358 | #define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 359 | #define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 360 | #define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 361 | #define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 362 | #define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 363 | |
| mbed_official | 525:c320967f86b9 | 364 | /* Bit fields for LCD SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 365 | #define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 366 | #define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 367 | #define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 368 | #define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 369 | #define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 370 | #define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 371 | |
| mbed_official | 525:c320967f86b9 | 372 | /* Bit fields for LCD SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 373 | #define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 374 | #define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 375 | #define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 376 | #define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 377 | #define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 378 | #define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 379 | |
| mbed_official | 525:c320967f86b9 | 380 | /* Bit fields for LCD SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 381 | #define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 382 | #define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 383 | #define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 384 | #define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 385 | #define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 386 | #define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 387 | |
| mbed_official | 525:c320967f86b9 | 388 | /* Bit fields for LCD SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 389 | #define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 390 | #define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 391 | #define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 392 | #define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 393 | #define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 394 | #define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 395 | |
| mbed_official | 525:c320967f86b9 | 396 | /* Bit fields for LCD SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 397 | #define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 398 | #define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 399 | #define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 400 | #define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 401 | #define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 402 | #define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 403 | |
| mbed_official | 525:c320967f86b9 | 404 | /* Bit fields for LCD SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 405 | #define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 406 | #define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 407 | #define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 408 | #define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 409 | #define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 410 | #define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 411 | |
| mbed_official | 525:c320967f86b9 | 412 | /* Bit fields for LCD FREEZE */ |
| mbed_official | 525:c320967f86b9 | 413 | #define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 414 | #define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 415 | #define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
| mbed_official | 525:c320967f86b9 | 416 | #define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */ |
| mbed_official | 525:c320967f86b9 | 417 | #define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */ |
| mbed_official | 525:c320967f86b9 | 418 | #define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 419 | #define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 420 | #define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 421 | #define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 422 | #define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 423 | #define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */ |
| mbed_official | 525:c320967f86b9 | 424 | |
| mbed_official | 525:c320967f86b9 | 425 | /* Bit fields for LCD SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 426 | #define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 427 | #define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 428 | #define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ |
| mbed_official | 525:c320967f86b9 | 429 | #define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 430 | #define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */ |
| mbed_official | 525:c320967f86b9 | 431 | #define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 432 | #define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 433 | #define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */ |
| mbed_official | 525:c320967f86b9 | 434 | #define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 435 | #define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */ |
| mbed_official | 525:c320967f86b9 | 436 | #define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 437 | #define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 438 | #define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */ |
| mbed_official | 525:c320967f86b9 | 439 | #define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 440 | #define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */ |
| mbed_official | 525:c320967f86b9 | 441 | #define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 442 | #define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 443 | #define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */ |
| mbed_official | 525:c320967f86b9 | 444 | #define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 445 | #define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */ |
| mbed_official | 525:c320967f86b9 | 446 | #define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 447 | #define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 448 | #define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 449 | #define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 450 | #define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */ |
| mbed_official | 525:c320967f86b9 | 451 | #define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 452 | #define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 453 | #define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 454 | #define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 455 | #define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */ |
| mbed_official | 525:c320967f86b9 | 456 | #define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 457 | #define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 458 | #define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 459 | #define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 460 | #define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */ |
| mbed_official | 525:c320967f86b9 | 461 | #define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 462 | #define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 463 | #define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 464 | #define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 465 | #define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */ |
| mbed_official | 525:c320967f86b9 | 466 | #define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 467 | #define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 468 | #define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 469 | #define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 470 | #define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */ |
| mbed_official | 525:c320967f86b9 | 471 | #define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 472 | #define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 473 | #define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 474 | #define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 475 | #define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */ |
| mbed_official | 525:c320967f86b9 | 476 | #define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 477 | #define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 478 | #define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 479 | #define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 480 | #define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */ |
| mbed_official | 525:c320967f86b9 | 481 | #define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 482 | #define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 483 | #define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 484 | #define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 485 | #define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */ |
| mbed_official | 525:c320967f86b9 | 486 | #define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 487 | #define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 488 | #define LCD_SYNCBUSY_SEGD4H (0x1UL << 12) /**< SEGD4H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 489 | #define _LCD_SYNCBUSY_SEGD4H_SHIFT 12 /**< Shift value for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 490 | #define _LCD_SYNCBUSY_SEGD4H_MASK 0x1000UL /**< Bit mask for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 491 | #define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 492 | #define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 493 | #define LCD_SYNCBUSY_SEGD5H (0x1UL << 13) /**< SEGD5H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 494 | #define _LCD_SYNCBUSY_SEGD5H_SHIFT 13 /**< Shift value for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 495 | #define _LCD_SYNCBUSY_SEGD5H_MASK 0x2000UL /**< Bit mask for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 496 | #define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 497 | #define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 498 | #define LCD_SYNCBUSY_SEGD6H (0x1UL << 14) /**< SEGD6H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 499 | #define _LCD_SYNCBUSY_SEGD6H_SHIFT 14 /**< Shift value for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 500 | #define _LCD_SYNCBUSY_SEGD6H_MASK 0x4000UL /**< Bit mask for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 501 | #define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 502 | #define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 503 | #define LCD_SYNCBUSY_SEGD7H (0x1UL << 15) /**< SEGD7H Register Busy */ |
| mbed_official | 525:c320967f86b9 | 504 | #define _LCD_SYNCBUSY_SEGD7H_SHIFT 15 /**< Shift value for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 505 | #define _LCD_SYNCBUSY_SEGD7H_MASK 0x8000UL /**< Bit mask for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 506 | #define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 507 | #define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 508 | #define LCD_SYNCBUSY_SEGD4L (0x1UL << 16) /**< SEGD4L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 509 | #define _LCD_SYNCBUSY_SEGD4L_SHIFT 16 /**< Shift value for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 510 | #define _LCD_SYNCBUSY_SEGD4L_MASK 0x10000UL /**< Bit mask for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 511 | #define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 512 | #define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 513 | #define LCD_SYNCBUSY_SEGD5L (0x1UL << 17) /**< SEGD5L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 514 | #define _LCD_SYNCBUSY_SEGD5L_SHIFT 17 /**< Shift value for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 515 | #define _LCD_SYNCBUSY_SEGD5L_MASK 0x20000UL /**< Bit mask for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 516 | #define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 517 | #define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 518 | #define LCD_SYNCBUSY_SEGD6L (0x1UL << 18) /**< SEGD6L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 519 | #define _LCD_SYNCBUSY_SEGD6L_SHIFT 18 /**< Shift value for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 520 | #define _LCD_SYNCBUSY_SEGD6L_MASK 0x40000UL /**< Bit mask for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 521 | #define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 522 | #define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 523 | #define LCD_SYNCBUSY_SEGD7L (0x1UL << 19) /**< SEGD7L Register Busy */ |
| mbed_official | 525:c320967f86b9 | 524 | #define _LCD_SYNCBUSY_SEGD7L_SHIFT 19 /**< Shift value for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 525 | #define _LCD_SYNCBUSY_SEGD7L_MASK 0x80000UL /**< Bit mask for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 526 | #define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 527 | #define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */ |
| mbed_official | 525:c320967f86b9 | 528 | |
| mbed_official | 525:c320967f86b9 | 529 | /* Bit fields for LCD SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 530 | #define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 531 | #define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 532 | #define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 533 | #define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 534 | #define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 535 | #define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */ |
| mbed_official | 525:c320967f86b9 | 536 | |
| mbed_official | 525:c320967f86b9 | 537 | /* Bit fields for LCD SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 538 | #define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 539 | #define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 540 | #define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 541 | #define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 542 | #define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 543 | #define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */ |
| mbed_official | 525:c320967f86b9 | 544 | |
| mbed_official | 525:c320967f86b9 | 545 | /* Bit fields for LCD SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 546 | #define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 547 | #define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 548 | #define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 549 | #define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 550 | #define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 551 | #define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */ |
| mbed_official | 525:c320967f86b9 | 552 | |
| mbed_official | 525:c320967f86b9 | 553 | /* Bit fields for LCD SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 554 | #define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 555 | #define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 556 | #define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 557 | #define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 558 | #define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 559 | #define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */ |
| mbed_official | 525:c320967f86b9 | 560 | |
| mbed_official | 525:c320967f86b9 | 561 | /* Bit fields for LCD SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 562 | #define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 563 | #define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 564 | #define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 565 | #define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 566 | #define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 567 | #define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */ |
| mbed_official | 525:c320967f86b9 | 568 | |
| mbed_official | 525:c320967f86b9 | 569 | /* Bit fields for LCD SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 570 | #define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 571 | #define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 572 | #define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 573 | #define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 574 | #define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 575 | #define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */ |
| mbed_official | 525:c320967f86b9 | 576 | |
| mbed_official | 525:c320967f86b9 | 577 | /* Bit fields for LCD SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 578 | #define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 579 | #define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 580 | #define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 581 | #define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 582 | #define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 583 | #define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */ |
| mbed_official | 525:c320967f86b9 | 584 | |
| mbed_official | 525:c320967f86b9 | 585 | /* Bit fields for LCD SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 586 | #define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 587 | #define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 588 | #define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 589 | #define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 590 | #define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 591 | #define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */ |
| mbed_official | 525:c320967f86b9 | 592 | |
| mbed_official | 525:c320967f86b9 | 593 | /** @} End of group EFM32GG_LCD */ |
| mbed_official | 525:c320967f86b9 | 594 | |
| mbed_official | 525:c320967f86b9 | 595 |