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targets/hal/TARGET_NXP/TARGET_LPC11U6X/gpio_irq_api.c@636:b0d178e9fa10, 2016-07-07 (annotated)

Committer:
lzbpli
Date:
Thu Jul 07 06:48:59 2016 +0000
Revision:
636:b0d178e9fa10
Parent:
285:31249416b6f9 
l053

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 174:8bb9f3a33240 1 /* mbed Microcontroller Library
mbed_official 174:8bb9f3a33240 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 174:8bb9f3a33240 3 *
mbed_official 174:8bb9f3a33240 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 174:8bb9f3a33240 5 * you may not use this file except in compliance with the License.
mbed_official 174:8bb9f3a33240 6 * You may obtain a copy of the License at
mbed_official 174:8bb9f3a33240 7 *
mbed_official 174:8bb9f3a33240 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 174:8bb9f3a33240 9 *
mbed_official 174:8bb9f3a33240 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 174:8bb9f3a33240 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 174:8bb9f3a33240 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 174:8bb9f3a33240 13 * See the License for the specific language governing permissions and
mbed_official 174:8bb9f3a33240 14 * limitations under the License.
mbed_official 174:8bb9f3a33240 15 */
mbed_official 174:8bb9f3a33240 16 #include <stddef.h>
mbed_official 174:8bb9f3a33240 17
mbed_official 174:8bb9f3a33240 18 #include "cmsis.h"
mbed_official 174:8bb9f3a33240 19 #include "gpio_irq_api.h"
mbed_official 285:31249416b6f9 20 #include "mbed_error.h"
mbed_official 174:8bb9f3a33240 21
mbed_official 174:8bb9f3a33240 22 #if DEVICE_INTERRUPTIN
mbed_official 174:8bb9f3a33240 23
mbed_official 174:8bb9f3a33240 24 #define CHANNEL_NUM 8
mbed_official 174:8bb9f3a33240 25 #define LPC_GPIO_X LPC_PINT
mbed_official 174:8bb9f3a33240 26 #define PININT_IRQ PIN_INT0_IRQn
mbed_official 174:8bb9f3a33240 27
mbed_official 174:8bb9f3a33240 28 static uint32_t channel_ids[CHANNEL_NUM] = {0};
mbed_official 174:8bb9f3a33240 29 static gpio_irq_handler irq_handler;
mbed_official 174:8bb9f3a33240 30
mbed_official 174:8bb9f3a33240 31 static inline void handle_interrupt_in(uint32_t channel) {
mbed_official 174:8bb9f3a33240 32 uint32_t ch_bit = (1 << channel);
mbed_official 174:8bb9f3a33240 33 // Return immediately if:
mbed_official 174:8bb9f3a33240 34 // * The interrupt was already served
mbed_official 174:8bb9f3a33240 35 // * There is no user handler
mbed_official 174:8bb9f3a33240 36 // * It is a level interrupt, not an edge interrupt
mbed_official 174:8bb9f3a33240 37 if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
mbed_official 174:8bb9f3a33240 38 (channel_ids[channel] == 0 ) ||
mbed_official 174:8bb9f3a33240 39 (LPC_GPIO_X->ISEL & ch_bit ) ) return;
mbed_official 174:8bb9f3a33240 40
mbed_official 174:8bb9f3a33240 41 if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
mbed_official 174:8bb9f3a33240 42 irq_handler(channel_ids[channel], IRQ_RISE);
mbed_official 174:8bb9f3a33240 43 LPC_GPIO_X->RISE = ch_bit;
mbed_official 174:8bb9f3a33240 44 }
mbed_official 174:8bb9f3a33240 45 if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
mbed_official 174:8bb9f3a33240 46 irq_handler(channel_ids[channel], IRQ_FALL);
mbed_official 174:8bb9f3a33240 47 LPC_GPIO_X->FALL = ch_bit;
mbed_official 174:8bb9f3a33240 48 }
mbed_official 174:8bb9f3a33240 49 LPC_GPIO_X->IST = ch_bit;
mbed_official 174:8bb9f3a33240 50 }
mbed_official 174:8bb9f3a33240 51
mbed_official 174:8bb9f3a33240 52 void gpio_irq0(void) {handle_interrupt_in(0);}
mbed_official 174:8bb9f3a33240 53 void gpio_irq1(void) {handle_interrupt_in(1);}
mbed_official 174:8bb9f3a33240 54 void gpio_irq2(void) {handle_interrupt_in(2);}
mbed_official 174:8bb9f3a33240 55 void gpio_irq3(void) {handle_interrupt_in(3);}
mbed_official 174:8bb9f3a33240 56 void gpio_irq4(void) {handle_interrupt_in(4);}
mbed_official 174:8bb9f3a33240 57 void gpio_irq5(void) {handle_interrupt_in(5);}
mbed_official 174:8bb9f3a33240 58 void gpio_irq6(void) {handle_interrupt_in(6);}
mbed_official 174:8bb9f3a33240 59 void gpio_irq7(void) {handle_interrupt_in(7);}
mbed_official 174:8bb9f3a33240 60
mbed_official 174:8bb9f3a33240 61 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
mbed_official 174:8bb9f3a33240 62 // PINT only supprt PIO0_*, PIO1_* and from PIO2_0 to PIO0_7 interrupt
mbed_official 174:8bb9f3a33240 63 if (pin >= P2_8) return -1;
mbed_official 174:8bb9f3a33240 64
mbed_official 174:8bb9f3a33240 65 irq_handler = handler;
mbed_official 174:8bb9f3a33240 66
mbed_official 174:8bb9f3a33240 67 int found_free_channel = 0;
mbed_official 174:8bb9f3a33240 68 int i = 0;
mbed_official 174:8bb9f3a33240 69 for (i=0; i<CHANNEL_NUM; i++) {
mbed_official 174:8bb9f3a33240 70 if (channel_ids[i] == 0) {
mbed_official 174:8bb9f3a33240 71 channel_ids[i] = id;
mbed_official 174:8bb9f3a33240 72 obj->ch = i;
mbed_official 174:8bb9f3a33240 73 found_free_channel = 1;
mbed_official 174:8bb9f3a33240 74 break;
mbed_official 174:8bb9f3a33240 75 }
mbed_official 174:8bb9f3a33240 76 }
mbed_official 174:8bb9f3a33240 77 if (!found_free_channel) return -1;
mbed_official 174:8bb9f3a33240 78
mbed_official 174:8bb9f3a33240 79 /* Enable AHB clock to the PIN, GPIO and IOCON domain. */
mbed_official 174:8bb9f3a33240 80 LPC_SYSCON->SYSAHBCLKCTRL |= ((1 << 19) | (1 << 16) | (1 << 7));
mbed_official 174:8bb9f3a33240 81
mbed_official 174:8bb9f3a33240 82 LPC_SYSCON->PINTSEL[obj->ch] = ((((pin >> PORT_SHIFT) & 0x3) * 24) + ((pin >> PIN_SHIFT) & 0x1F));
mbed_official 174:8bb9f3a33240 83
mbed_official 174:8bb9f3a33240 84 // Interrupt Wake-Up Enable
mbed_official 174:8bb9f3a33240 85 LPC_SYSCON->STARTERP0 |= (1 << obj->ch);
mbed_official 174:8bb9f3a33240 86
mbed_official 174:8bb9f3a33240 87 LPC_GPIO_PORT->DIR[(pin >> PORT_SHIFT) & 0x3] &= ~(1 << ((pin >> PIN_SHIFT) & 0x1F));
mbed_official 174:8bb9f3a33240 88
mbed_official 174:8bb9f3a33240 89 void (*channels_irq)(void) = NULL;
mbed_official 174:8bb9f3a33240 90 switch (obj->ch) {
mbed_official 174:8bb9f3a33240 91 case 0: channels_irq = &gpio_irq0; break;
mbed_official 174:8bb9f3a33240 92 case 1: channels_irq = &gpio_irq1; break;
mbed_official 174:8bb9f3a33240 93 case 2: channels_irq = &gpio_irq2; break;
mbed_official 174:8bb9f3a33240 94 case 3: channels_irq = &gpio_irq3; break;
mbed_official 174:8bb9f3a33240 95 case 4: channels_irq = &gpio_irq4; break;
mbed_official 174:8bb9f3a33240 96 case 5: channels_irq = &gpio_irq5; break;
mbed_official 174:8bb9f3a33240 97 case 6: channels_irq = &gpio_irq6; break;
mbed_official 174:8bb9f3a33240 98 case 7: channels_irq = &gpio_irq7; break;
mbed_official 174:8bb9f3a33240 99 }
mbed_official 174:8bb9f3a33240 100 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
mbed_official 174:8bb9f3a33240 101 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 174:8bb9f3a33240 102
mbed_official 174:8bb9f3a33240 103 return 0;
mbed_official 174:8bb9f3a33240 104 }
mbed_official 174:8bb9f3a33240 105
mbed_official 174:8bb9f3a33240 106 void gpio_irq_free(gpio_irq_t *obj) {
mbed_official 174:8bb9f3a33240 107 channel_ids[obj->ch] = 0;
mbed_official 174:8bb9f3a33240 108 LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
mbed_official 174:8bb9f3a33240 109 }
mbed_official 174:8bb9f3a33240 110
mbed_official 174:8bb9f3a33240 111 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
mbed_official 174:8bb9f3a33240 112 unsigned int ch_bit = (1 << obj->ch);
mbed_official 174:8bb9f3a33240 113
mbed_official 174:8bb9f3a33240 114 // Clear interrupt
mbed_official 174:8bb9f3a33240 115 if (!(LPC_GPIO_X->ISEL & ch_bit))
mbed_official 174:8bb9f3a33240 116 LPC_GPIO_X->IST = ch_bit;
mbed_official 174:8bb9f3a33240 117
mbed_official 174:8bb9f3a33240 118 // Edge trigger
mbed_official 174:8bb9f3a33240 119 LPC_GPIO_X->ISEL &= ~ch_bit;
mbed_official 174:8bb9f3a33240 120 if (event == IRQ_RISE) {
mbed_official 174:8bb9f3a33240 121 if (enable) {
mbed_official 174:8bb9f3a33240 122 LPC_GPIO_X->IENR |= ch_bit;
mbed_official 174:8bb9f3a33240 123 } else {
mbed_official 174:8bb9f3a33240 124 LPC_GPIO_X->IENR &= ~ch_bit;
mbed_official 174:8bb9f3a33240 125 }
mbed_official 174:8bb9f3a33240 126 } else {
mbed_official 174:8bb9f3a33240 127 if (enable) {
mbed_official 174:8bb9f3a33240 128 LPC_GPIO_X->IENF |= ch_bit;
mbed_official 174:8bb9f3a33240 129 } else {
mbed_official 174:8bb9f3a33240 130 LPC_GPIO_X->IENF &= ~ch_bit;
mbed_official 174:8bb9f3a33240 131 }
mbed_official 174:8bb9f3a33240 132 }
mbed_official 174:8bb9f3a33240 133 }
mbed_official 174:8bb9f3a33240 134
mbed_official 174:8bb9f3a33240 135 void gpio_irq_enable(gpio_irq_t *obj) {
mbed_official 174:8bb9f3a33240 136 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 174:8bb9f3a33240 137 }
mbed_official 174:8bb9f3a33240 138
mbed_official 174:8bb9f3a33240 139 void gpio_irq_disable(gpio_irq_t *obj) {
mbed_official 174:8bb9f3a33240 140 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
mbed_official 174:8bb9f3a33240 141 }
mbed_official 174:8bb9f3a33240 142
mbed_official 174:8bb9f3a33240 143 #endif