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targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/system_LPC8xx.c@636:b0d178e9fa10, 2016-07-07 (annotated)

Committer:
lzbpli
Date:
Thu Jul 07 06:48:59 2016 +0000
Revision:
636:b0d178e9fa10
Parent:
365:7ced7d9d5ffe 
l053

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 337:6ed01c00b962 1 /******************************************************************************
mbed_official 337:6ed01c00b962 2 * @file: system_LPC8xx.c
mbed_official 337:6ed01c00b962 3 * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
mbed_official 337:6ed01c00b962 4 * for the NXP LPC8xx Device Series
mbed_official 337:6ed01c00b962 5 * @version: V1.0
mbed_official 337:6ed01c00b962 6 * @date: 16. Aug. 2012
mbed_official 337:6ed01c00b962 7 *----------------------------------------------------------------------------
mbed_official 337:6ed01c00b962 8 *
mbed_official 337:6ed01c00b962 9 * Copyright (C) 2012 ARM Limited. All rights reserved.
mbed_official 337:6ed01c00b962 10 *
mbed_official 337:6ed01c00b962 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
mbed_official 337:6ed01c00b962 12 * processor based microcontrollers. This file can be freely distributed
mbed_official 337:6ed01c00b962 13 * within development tools that are supporting such ARM based processors.
mbed_official 337:6ed01c00b962 14 *
mbed_official 337:6ed01c00b962 15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mbed_official 337:6ed01c00b962 16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mbed_official 337:6ed01c00b962 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mbed_official 337:6ed01c00b962 18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mbed_official 337:6ed01c00b962 19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mbed_official 337:6ed01c00b962 20 *
mbed_official 337:6ed01c00b962 21 ******************************************************************************/
mbed_official 337:6ed01c00b962 22 #include <stdint.h>
mbed_official 337:6ed01c00b962 23 #include "LPC82x.h"
mbed_official 337:6ed01c00b962 24
mbed_official 337:6ed01c00b962 25 /*
mbed_official 337:6ed01c00b962 26 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
mbed_official 337:6ed01c00b962 27 */
mbed_official 337:6ed01c00b962 28
mbed_official 337:6ed01c00b962 29 /*--------------------- Clock Configuration ----------------------------------*/
mbed_official 337:6ed01c00b962 30 //
mbed_official 337:6ed01c00b962 31 // <e> Clock Configuration
mbed_official 337:6ed01c00b962 32 #define CLOCK_SETUP 1
mbed_official 337:6ed01c00b962 33 // <h> System Oscillator Control Register (SYSOSCCTRL)
mbed_official 337:6ed01c00b962 34 // <o.0> BYPASS: System Oscillator Bypass Enable
mbed_official 337:6ed01c00b962 35 // <i> If enabled then PLL input (sys_osc_clk) is fed
mbed_official 337:6ed01c00b962 36 // <i> directly from XTALIN and XTALOUT pins.
mbed_official 337:6ed01c00b962 37 // <o.1> FREQRANGE: System Oscillator Frequency Range
mbed_official 337:6ed01c00b962 38 // <i> Determines frequency range for Low-power oscillator.
mbed_official 337:6ed01c00b962 39 // <0=> 1 - 20 MHz
mbed_official 337:6ed01c00b962 40 // <1=> 15 - 25 MHz
mbed_official 337:6ed01c00b962 41 // </h>
mbed_official 337:6ed01c00b962 42 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
mbed_official 337:6ed01c00b962 43 //
mbed_official 337:6ed01c00b962 44 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
mbed_official 337:6ed01c00b962 45 // <o.0..4> DIVSEL: Select Divider for Fclkana
mbed_official 337:6ed01c00b962 46 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
mbed_official 337:6ed01c00b962 47 // <0-31>
mbed_official 337:6ed01c00b962 48 // <o.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
mbed_official 337:6ed01c00b962 49 // <0=> Undefined
mbed_official 337:6ed01c00b962 50 // <1=> 0.6 MHz
mbed_official 337:6ed01c00b962 51 // <2=> 1.05 MHz
mbed_official 337:6ed01c00b962 52 // <3=> 1.4 MHz
mbed_official 337:6ed01c00b962 53 // <4=> 1.75 MHz
mbed_official 337:6ed01c00b962 54 // <5=> 2.1 MHz
mbed_official 337:6ed01c00b962 55 // <6=> 2.4 MHz
mbed_official 337:6ed01c00b962 56 // <7=> 2.7 MHz
mbed_official 337:6ed01c00b962 57 // <8=> 3.0 MHz
mbed_official 337:6ed01c00b962 58 // <9=> 3.25 MHz
mbed_official 337:6ed01c00b962 59 // <10=> 3.5 MHz
mbed_official 337:6ed01c00b962 60 // <11=> 3.75 MHz
mbed_official 337:6ed01c00b962 61 // <12=> 4.0 MHz
mbed_official 337:6ed01c00b962 62 // <13=> 4.2 MHz
mbed_official 337:6ed01c00b962 63 // <14=> 4.4 MHz
mbed_official 337:6ed01c00b962 64 // <15=> 4.6 MHz
mbed_official 337:6ed01c00b962 65 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
mbed_official 337:6ed01c00b962 66 // </h>
mbed_official 337:6ed01c00b962 67 // <h> System PLL Control Register (SYSPLLCTRL)
mbed_official 337:6ed01c00b962 68 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
mbed_official 337:6ed01c00b962 69 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
mbed_official 337:6ed01c00b962 70 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
mbed_official 337:6ed01c00b962 71 // <o.0..4> MSEL: Feedback Divider Selection
mbed_official 337:6ed01c00b962 72 // <i> M = MSEL + 1
mbed_official 337:6ed01c00b962 73 // <0-31>
mbed_official 337:6ed01c00b962 74 // <o.5..6> PSEL: Post Divider Selection
mbed_official 337:6ed01c00b962 75 // <0=> P = 1
mbed_official 337:6ed01c00b962 76 // <1=> P = 2
mbed_official 337:6ed01c00b962 77 // <2=> P = 4
mbed_official 337:6ed01c00b962 78 // <3=> P = 8
mbed_official 337:6ed01c00b962 79 // </h>
mbed_official 337:6ed01c00b962 80 #define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000
mbed_official 337:6ed01c00b962 81 //
mbed_official 337:6ed01c00b962 82 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
mbed_official 337:6ed01c00b962 83 // <o.0..1> SEL: System PLL Clock Source
mbed_official 337:6ed01c00b962 84 // <0=> IRC
mbed_official 337:6ed01c00b962 85 // <1=> Crystal Oscillator
mbed_official 337:6ed01c00b962 86 // <2=> Reserved
mbed_official 337:6ed01c00b962 87 // <3=> CLKIN. External clock input.
mbed_official 337:6ed01c00b962 88 // </h>
mbed_official 337:6ed01c00b962 89 #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
mbed_official 337:6ed01c00b962 90 //
mbed_official 337:6ed01c00b962 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
mbed_official 337:6ed01c00b962 92 // <o.0..1> SEL: Clock Source for Main Clock
mbed_official 337:6ed01c00b962 93 // <0=> IRC Oscillator
mbed_official 337:6ed01c00b962 94 // <1=> PLL input
mbed_official 337:6ed01c00b962 95 // <2=> Watchdog Oscillator
mbed_official 337:6ed01c00b962 96 // <3=> PLL output
mbed_official 337:6ed01c00b962 97 // </h>
mbed_official 337:6ed01c00b962 98 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
mbed_official 337:6ed01c00b962 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
mbed_official 337:6ed01c00b962 100 // <o.0..7> DIV: System AHB Clock Divider
mbed_official 337:6ed01c00b962 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
mbed_official 337:6ed01c00b962 102 // <i> 0 = is disabled
mbed_official 337:6ed01c00b962 103 // <0-255>
mbed_official 337:6ed01c00b962 104 // </h>
mbed_official 337:6ed01c00b962 105 #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001
mbed_official 337:6ed01c00b962 106 // </e>
mbed_official 337:6ed01c00b962 107
mbed_official 337:6ed01c00b962 108 //#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
mbed_official 337:6ed01c00b962 109
mbed_official 337:6ed01c00b962 110 /*
mbed_official 337:6ed01c00b962 111 #if (CLOCK_SETUP == 0)
mbed_official 337:6ed01c00b962 112 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
mbed_official 337:6ed01c00b962 113 #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000
mbed_official 337:6ed01c00b962 114 #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
mbed_official 337:6ed01c00b962 115 #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000
mbed_official 337:6ed01c00b962 116 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
mbed_official 337:6ed01c00b962 117 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
mbed_official 337:6ed01c00b962 118 #elif (CLOCK_SETUP == 2)
mbed_official 337:6ed01c00b962 119 // #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
mbed_official 337:6ed01c00b962 120 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
mbed_official 337:6ed01c00b962 121 #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
mbed_official 337:6ed01c00b962 122 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
mbed_official 337:6ed01c00b962 123 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
mbed_official 337:6ed01c00b962 124 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
mbed_official 337:6ed01c00b962 125 #endif
mbed_official 337:6ed01c00b962 126 */
mbed_official 337:6ed01c00b962 127
mbed_official 337:6ed01c00b962 128 /*
mbed_official 337:6ed01c00b962 129 //-------- <<< end of configuration section >>> ------------------------------
mbed_official 337:6ed01c00b962 130 */
mbed_official 337:6ed01c00b962 131
mbed_official 337:6ed01c00b962 132 /*----------------------------------------------------------------------------
mbed_official 337:6ed01c00b962 133 Check the register settings
mbed_official 337:6ed01c00b962 134 *----------------------------------------------------------------------------*/
mbed_official 337:6ed01c00b962 135 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
mbed_official 337:6ed01c00b962 136 #define CHECK_RSVD(val, mask) (val & mask)
mbed_official 337:6ed01c00b962 137
mbed_official 337:6ed01c00b962 138 /* Clock Configuration -------------------------------------------------------*/
mbed_official 337:6ed01c00b962 139 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
mbed_official 337:6ed01c00b962 140 #error "SYSOSCCTRL: Invalid values of reserved bits!"
mbed_official 337:6ed01c00b962 141 #endif
mbed_official 337:6ed01c00b962 142
mbed_official 337:6ed01c00b962 143 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
mbed_official 337:6ed01c00b962 144 #error "WDTOSCCTRL: Invalid values of reserved bits!"
mbed_official 337:6ed01c00b962 145 #endif
mbed_official 337:6ed01c00b962 146
mbed_official 337:6ed01c00b962 147 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
mbed_official 337:6ed01c00b962 148 #error "SYSPLLCLKSEL: Value out of range!"
mbed_official 337:6ed01c00b962 149 #endif
mbed_official 337:6ed01c00b962 150
mbed_official 337:6ed01c00b962 151 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
mbed_official 337:6ed01c00b962 152 #error "SYSPLLCTRL: Invalid values of reserved bits!"
mbed_official 337:6ed01c00b962 153 #endif
mbed_official 337:6ed01c00b962 154
mbed_official 337:6ed01c00b962 155 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
mbed_official 337:6ed01c00b962 156 #error "MAINCLKSEL: Invalid values of reserved bits!"
mbed_official 337:6ed01c00b962 157 #endif
mbed_official 337:6ed01c00b962 158
mbed_official 337:6ed01c00b962 159 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
mbed_official 337:6ed01c00b962 160 #error "SYSAHBCLKDIV: Value out of range!"
mbed_official 337:6ed01c00b962 161 #endif
mbed_official 337:6ed01c00b962 162
mbed_official 337:6ed01c00b962 163
mbed_official 337:6ed01c00b962 164 /*----------------------------------------------------------------------------
mbed_official 337:6ed01c00b962 165 DEFINES
mbed_official 337:6ed01c00b962 166 *----------------------------------------------------------------------------*/
mbed_official 337:6ed01c00b962 167
mbed_official 337:6ed01c00b962 168 /*----------------------------------------------------------------------------
mbed_official 337:6ed01c00b962 169 Define clocks
mbed_official 337:6ed01c00b962 170 *----------------------------------------------------------------------------*/
mbed_official 337:6ed01c00b962 171 #define __XTAL (12000000UL) /* Oscillator frequency */
mbed_official 337:6ed01c00b962 172 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
mbed_official 337:6ed01c00b962 173 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
mbed_official 337:6ed01c00b962 174 #define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
mbed_official 337:6ed01c00b962 175
mbed_official 337:6ed01c00b962 176
mbed_official 337:6ed01c00b962 177 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
mbed_official 337:6ed01c00b962 178 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
mbed_official 337:6ed01c00b962 179
mbed_official 337:6ed01c00b962 180 #if (CLOCK_SETUP) /* Clock Setup */
mbed_official 337:6ed01c00b962 181 #if (__FREQSEL == 0)
mbed_official 337:6ed01c00b962 182 #define __WDT_OSC_CLK ( 0) /* undefined */
mbed_official 337:6ed01c00b962 183 #elif (__FREQSEL == 1)
mbed_official 337:6ed01c00b962 184 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
mbed_official 337:6ed01c00b962 185 #elif (__FREQSEL == 2)
mbed_official 337:6ed01c00b962 186 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
mbed_official 337:6ed01c00b962 187 #elif (__FREQSEL == 3)
mbed_official 337:6ed01c00b962 188 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
mbed_official 337:6ed01c00b962 189 #elif (__FREQSEL == 4)
mbed_official 337:6ed01c00b962 190 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
mbed_official 337:6ed01c00b962 191 #elif (__FREQSEL == 5)
mbed_official 337:6ed01c00b962 192 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
mbed_official 337:6ed01c00b962 193 #elif (__FREQSEL == 6)
mbed_official 337:6ed01c00b962 194 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
mbed_official 337:6ed01c00b962 195 #elif (__FREQSEL == 7)
mbed_official 337:6ed01c00b962 196 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
mbed_official 337:6ed01c00b962 197 #elif (__FREQSEL == 8)
mbed_official 337:6ed01c00b962 198 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
mbed_official 337:6ed01c00b962 199 #elif (__FREQSEL == 9)
mbed_official 337:6ed01c00b962 200 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
mbed_official 337:6ed01c00b962 201 #elif (__FREQSEL == 10)
mbed_official 337:6ed01c00b962 202 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
mbed_official 337:6ed01c00b962 203 #elif (__FREQSEL == 11)
mbed_official 337:6ed01c00b962 204 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
mbed_official 337:6ed01c00b962 205 #elif (__FREQSEL == 12)
mbed_official 337:6ed01c00b962 206 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
mbed_official 337:6ed01c00b962 207 #elif (__FREQSEL == 13)
mbed_official 337:6ed01c00b962 208 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
mbed_official 337:6ed01c00b962 209 #elif (__FREQSEL == 14)
mbed_official 337:6ed01c00b962 210 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
mbed_official 337:6ed01c00b962 211 #else
mbed_official 337:6ed01c00b962 212 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
mbed_official 337:6ed01c00b962 213 #endif
mbed_official 337:6ed01c00b962 214
mbed_official 337:6ed01c00b962 215 /* sys_pllclkin calculation */
mbed_official 337:6ed01c00b962 216 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
mbed_official 337:6ed01c00b962 217 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
mbed_official 337:6ed01c00b962 218 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
mbed_official 337:6ed01c00b962 219 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
mbed_official 337:6ed01c00b962 220 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
mbed_official 337:6ed01c00b962 221 #define __SYS_PLLCLKIN (__CLKIN_CLK)
mbed_official 337:6ed01c00b962 222 #else
mbed_official 337:6ed01c00b962 223 #define __SYS_PLLCLKIN (0)
mbed_official 337:6ed01c00b962 224 #endif
mbed_official 337:6ed01c00b962 225
mbed_official 337:6ed01c00b962 226 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
mbed_official 337:6ed01c00b962 227
mbed_official 337:6ed01c00b962 228 /* main clock calculation */
mbed_official 337:6ed01c00b962 229 #if ((MAINCLKSEL_Val & 0x03) == 0)
mbed_official 337:6ed01c00b962 230 #define __MAIN_CLOCK (__IRC_OSC_CLK)
mbed_official 337:6ed01c00b962 231 #elif ((MAINCLKSEL_Val & 0x03) == 1)
mbed_official 337:6ed01c00b962 232 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
mbed_official 337:6ed01c00b962 233 #elif ((MAINCLKSEL_Val & 0x03) == 2)
mbed_official 337:6ed01c00b962 234 #if (__FREQSEL == 0)
mbed_official 337:6ed01c00b962 235 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
mbed_official 337:6ed01c00b962 236 #else
mbed_official 337:6ed01c00b962 237 #define __MAIN_CLOCK (__WDT_OSC_CLK)
mbed_official 337:6ed01c00b962 238 #endif
mbed_official 337:6ed01c00b962 239 #elif ((MAINCLKSEL_Val & 0x03) == 3)
mbed_official 337:6ed01c00b962 240 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
mbed_official 337:6ed01c00b962 241 #else
mbed_official 337:6ed01c00b962 242 #define __MAIN_CLOCK (0)
mbed_official 337:6ed01c00b962 243 #endif
mbed_official 337:6ed01c00b962 244
mbed_official 337:6ed01c00b962 245 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
mbed_official 337:6ed01c00b962 246
mbed_official 337:6ed01c00b962 247 #else
mbed_official 337:6ed01c00b962 248 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
mbed_official 337:6ed01c00b962 249 #endif // CLOCK_SETUP
mbed_official 337:6ed01c00b962 250
mbed_official 337:6ed01c00b962 251
mbed_official 337:6ed01c00b962 252 /*----------------------------------------------------------------------------
mbed_official 337:6ed01c00b962 253 Clock Variable definitions
mbed_official 337:6ed01c00b962 254 *----------------------------------------------------------------------------*/
mbed_official 337:6ed01c00b962 255 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
mbed_official 337:6ed01c00b962 256 uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
mbed_official 337:6ed01c00b962 257
mbed_official 337:6ed01c00b962 258 /*----------------------------------------------------------------------------
mbed_official 337:6ed01c00b962 259 Clock functions
mbed_official 337:6ed01c00b962 260 *----------------------------------------------------------------------------*/
mbed_official 337:6ed01c00b962 261 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
mbed_official 337:6ed01c00b962 262 {
mbed_official 337:6ed01c00b962 263 uint32_t wdt_osc = 0;
mbed_official 337:6ed01c00b962 264
mbed_official 337:6ed01c00b962 265 /* Determine clock frequency according to clock register values */
mbed_official 337:6ed01c00b962 266 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
mbed_official 337:6ed01c00b962 267 case 0: wdt_osc = 0; break;
mbed_official 337:6ed01c00b962 268 case 1: wdt_osc = 500000; break;
mbed_official 337:6ed01c00b962 269 case 2: wdt_osc = 800000; break;
mbed_official 337:6ed01c00b962 270 case 3: wdt_osc = 1100000; break;
mbed_official 337:6ed01c00b962 271 case 4: wdt_osc = 1400000; break;
mbed_official 337:6ed01c00b962 272 case 5: wdt_osc = 1600000; break;
mbed_official 337:6ed01c00b962 273 case 6: wdt_osc = 1800000; break;
mbed_official 337:6ed01c00b962 274 case 7: wdt_osc = 2000000; break;
mbed_official 337:6ed01c00b962 275 case 8: wdt_osc = 2200000; break;
mbed_official 337:6ed01c00b962 276 case 9: wdt_osc = 2400000; break;
mbed_official 337:6ed01c00b962 277 case 10: wdt_osc = 2600000; break;
mbed_official 337:6ed01c00b962 278 case 11: wdt_osc = 2700000; break;
mbed_official 337:6ed01c00b962 279 case 12: wdt_osc = 2900000; break;
mbed_official 337:6ed01c00b962 280 case 13: wdt_osc = 3100000; break;
mbed_official 337:6ed01c00b962 281 case 14: wdt_osc = 3200000; break;
mbed_official 337:6ed01c00b962 282 case 15: wdt_osc = 3400000; break;
mbed_official 337:6ed01c00b962 283 }
mbed_official 337:6ed01c00b962 284 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
mbed_official 337:6ed01c00b962 285
mbed_official 337:6ed01c00b962 286 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
mbed_official 337:6ed01c00b962 287 case 0: /* Internal RC oscillator */
mbed_official 337:6ed01c00b962 288 SystemCoreClock = __IRC_OSC_CLK;
mbed_official 337:6ed01c00b962 289 break;
mbed_official 337:6ed01c00b962 290 case 1: /* Input Clock to System PLL */
mbed_official 337:6ed01c00b962 291 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
mbed_official 337:6ed01c00b962 292 case 0: /* Internal RC oscillator */
mbed_official 337:6ed01c00b962 293 SystemCoreClock = __IRC_OSC_CLK;
mbed_official 337:6ed01c00b962 294 break;
mbed_official 337:6ed01c00b962 295 case 1: /* System oscillator */
mbed_official 337:6ed01c00b962 296 SystemCoreClock = __SYS_OSC_CLK;
mbed_official 337:6ed01c00b962 297 break;
mbed_official 337:6ed01c00b962 298 case 2: /* Reserved */
mbed_official 337:6ed01c00b962 299 SystemCoreClock = 0;
mbed_official 337:6ed01c00b962 300 break;
mbed_official 337:6ed01c00b962 301 case 3: /* CLKIN pin */
mbed_official 337:6ed01c00b962 302 SystemCoreClock = __CLKIN_CLK;
mbed_official 337:6ed01c00b962 303 break;
mbed_official 337:6ed01c00b962 304 }
mbed_official 337:6ed01c00b962 305 break;
mbed_official 337:6ed01c00b962 306 case 2: /* WDT Oscillator */
mbed_official 337:6ed01c00b962 307 SystemCoreClock = wdt_osc;
mbed_official 337:6ed01c00b962 308 break;
mbed_official 337:6ed01c00b962 309 case 3: /* System PLL Clock Out */
mbed_official 337:6ed01c00b962 310 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
mbed_official 337:6ed01c00b962 311 case 0: /* Internal RC oscillator */
mbed_official 337:6ed01c00b962 312 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
mbed_official 337:6ed01c00b962 313 break;
mbed_official 337:6ed01c00b962 314 case 1: /* System oscillator */
mbed_official 337:6ed01c00b962 315 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
mbed_official 337:6ed01c00b962 316 break;
mbed_official 337:6ed01c00b962 317 case 2: /* Reserved */
mbed_official 337:6ed01c00b962 318 SystemCoreClock = 0;
mbed_official 337:6ed01c00b962 319 break;
mbed_official 337:6ed01c00b962 320 case 3: /* CLKIN pin */
mbed_official 337:6ed01c00b962 321 SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
mbed_official 337:6ed01c00b962 322 break;
mbed_official 337:6ed01c00b962 323 }
mbed_official 337:6ed01c00b962 324 break;
mbed_official 337:6ed01c00b962 325 }
mbed_official 337:6ed01c00b962 326
mbed_official 337:6ed01c00b962 327 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
mbed_official 337:6ed01c00b962 328
mbed_official 337:6ed01c00b962 329 }
mbed_official 337:6ed01c00b962 330
mbed_official 337:6ed01c00b962 331 /**
mbed_official 337:6ed01c00b962 332 * Initialize the system
mbed_official 337:6ed01c00b962 333 *
mbed_official 337:6ed01c00b962 334 * @param none
mbed_official 337:6ed01c00b962 335 * @return none
mbed_official 337:6ed01c00b962 336 *
mbed_official 337:6ed01c00b962 337 * @brief Setup the microcontroller system.
mbed_official 337:6ed01c00b962 338 * Initialize the System.
mbed_official 337:6ed01c00b962 339 */
mbed_official 337:6ed01c00b962 340 void SystemInit (void) {
mbed_official 337:6ed01c00b962 341
mbed_official 337:6ed01c00b962 342 /* System clock to the IOCON & the SWM need to be enabled or
mbed_official 337:6ed01c00b962 343 most of the I/O related peripherals won't work. */
mbed_official 337:6ed01c00b962 344 LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
mbed_official 337:6ed01c00b962 345
mbed_official 337:6ed01c00b962 346 #if (CLOCK_SETUP) /* Clock Setup */
mbed_official 337:6ed01c00b962 347
mbed_official 337:6ed01c00b962 348 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
mbed_official 365:7ced7d9d5ffe 349 volatile uint32_t i;
mbed_official 337:6ed01c00b962 350 LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
mbed_official 337:6ed01c00b962 351 LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
mbed_official 337:6ed01c00b962 352 LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */
mbed_official 337:6ed01c00b962 353 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
mbed_official 337:6ed01c00b962 354 for (i = 0; i < 200; i++) __NOP();
mbed_official 337:6ed01c00b962 355 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
mbed_official 337:6ed01c00b962 356 #endif
mbed_official 337:6ed01c00b962 357
mbed_official 337:6ed01c00b962 358 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
mbed_official 337:6ed01c00b962 359 LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
mbed_official 337:6ed01c00b962 360 LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */
mbed_official 337:6ed01c00b962 361 for (i = 0; i < 200; i++) __NOP();
mbed_official 337:6ed01c00b962 362 #endif
mbed_official 337:6ed01c00b962 363
mbed_official 337:6ed01c00b962 364 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */
mbed_official 337:6ed01c00b962 365 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
mbed_official 337:6ed01c00b962 366 LPC_SYSCON->SYSPLLCLKUEN = 0;
mbed_official 337:6ed01c00b962 367 LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */
mbed_official 337:6ed01c00b962 368 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
mbed_official 337:6ed01c00b962 369
mbed_official 337:6ed01c00b962 370 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
mbed_official 337:6ed01c00b962 371 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
mbed_official 337:6ed01c00b962 372 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
mbed_official 337:6ed01c00b962 373 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
mbed_official 337:6ed01c00b962 374 #endif
mbed_official 337:6ed01c00b962 375
mbed_official 337:6ed01c00b962 376 #if (((MAINCLKSEL_Val & 0x03) == 2) )
mbed_official 337:6ed01c00b962 377 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
mbed_official 337:6ed01c00b962 378 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
mbed_official 337:6ed01c00b962 379 for (i = 0; i < 200; i++) __NOP();
mbed_official 337:6ed01c00b962 380 #endif
mbed_official 337:6ed01c00b962 381
mbed_official 337:6ed01c00b962 382 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
mbed_official 337:6ed01c00b962 383 LPC_SYSCON->MAINCLKUEN = 0;
mbed_official 337:6ed01c00b962 384 LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */
mbed_official 337:6ed01c00b962 385 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
mbed_official 337:6ed01c00b962 386
mbed_official 337:6ed01c00b962 387 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
mbed_official 337:6ed01c00b962 388 #endif
mbed_official 337:6ed01c00b962 389 }