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targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c@636:b0d178e9fa10, 2016-07-07 (annotated)
- Committer:
- lzbpli
- Date:
- Thu Jul 07 06:48:59 2016 +0000
- Revision:
- 636:b0d178e9fa10
- Parent:
- 103:9b881da47c92
l053
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 103:9b881da47c92 | 1 | /**************************************************************************//** |
| mbed_official | 103:9b881da47c92 | 2 | * @file system_LPC15xx.c |
| mbed_official | 103:9b881da47c92 | 3 | * @brief CMSIS Cortex-M3 Device System Source File for |
| mbed_official | 103:9b881da47c92 | 4 | * NXP LPC15xx Device Series |
| mbed_official | 103:9b881da47c92 | 5 | * @version V1.00 |
| mbed_official | 103:9b881da47c92 | 6 | * @date 19. July 2013 |
| mbed_official | 103:9b881da47c92 | 7 | * |
| mbed_official | 103:9b881da47c92 | 8 | * @note |
| mbed_official | 103:9b881da47c92 | 9 | * Copyright (C) 2013 ARM Limited. All rights reserved. |
| mbed_official | 103:9b881da47c92 | 10 | * |
| mbed_official | 103:9b881da47c92 | 11 | * @par |
| mbed_official | 103:9b881da47c92 | 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| mbed_official | 103:9b881da47c92 | 13 | * processor based microcontrollers. This file can be freely distributed |
| mbed_official | 103:9b881da47c92 | 14 | * within development tools that are supporting such ARM based processors. |
| mbed_official | 103:9b881da47c92 | 15 | * |
| mbed_official | 103:9b881da47c92 | 16 | * @par |
| mbed_official | 103:9b881da47c92 | 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| mbed_official | 103:9b881da47c92 | 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| mbed_official | 103:9b881da47c92 | 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| mbed_official | 103:9b881da47c92 | 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| mbed_official | 103:9b881da47c92 | 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| mbed_official | 103:9b881da47c92 | 22 | * |
| mbed_official | 103:9b881da47c92 | 23 | ******************************************************************************/ |
| mbed_official | 103:9b881da47c92 | 24 | |
| mbed_official | 103:9b881da47c92 | 25 | |
| mbed_official | 103:9b881da47c92 | 26 | #include <stdint.h> |
| mbed_official | 103:9b881da47c92 | 27 | #include "LPC15xx.h" |
| mbed_official | 103:9b881da47c92 | 28 | |
| mbed_official | 103:9b881da47c92 | 29 | /* |
| mbed_official | 103:9b881da47c92 | 30 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| mbed_official | 103:9b881da47c92 | 31 | */ |
| mbed_official | 103:9b881da47c92 | 32 | |
| mbed_official | 103:9b881da47c92 | 33 | /*- SystemCoreClock Configuration -------------------------------------------*/ |
| mbed_official | 103:9b881da47c92 | 34 | // <e0> SystemCoreClock Configuration |
| mbed_official | 103:9b881da47c92 | 35 | #define CLOCK_SETUP 1 |
| mbed_official | 103:9b881da47c92 | 36 | // |
| mbed_official | 103:9b881da47c92 | 37 | // <h> System Oscillator Control (SYSOSCCTRL) |
| mbed_official | 103:9b881da47c92 | 38 | // <o.0> BYPASS: System Oscillator Bypass Enable |
| mbed_official | 103:9b881da47c92 | 39 | // <i> If enabled then PLL input (sys_osc_clk) is fed |
| mbed_official | 103:9b881da47c92 | 40 | // <i> directly from XTALIN and XTALOUT pins. |
| mbed_official | 103:9b881da47c92 | 41 | // <o.1> FREQRANGE: System Oscillator Frequency Range |
| mbed_official | 103:9b881da47c92 | 42 | // <i> Determines frequency range for Low-power oscillator. |
| mbed_official | 103:9b881da47c92 | 43 | // <0=> 1 - 20 MHz |
| mbed_official | 103:9b881da47c92 | 44 | // <1=> 15 - 25 MHz |
| mbed_official | 103:9b881da47c92 | 45 | // </h> |
| mbed_official | 103:9b881da47c92 | 46 | #define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 47 | // |
| mbed_official | 103:9b881da47c92 | 48 | // <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL) |
| mbed_official | 103:9b881da47c92 | 49 | // <0=> IRC Oscillator |
| mbed_official | 103:9b881da47c92 | 50 | // <1=> Crystal Oscillator (SYSOSC) |
| mbed_official | 103:9b881da47c92 | 51 | #define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 52 | // |
| mbed_official | 103:9b881da47c92 | 53 | // <e> Clock Configuration (Manual) |
| mbed_official | 103:9b881da47c92 | 54 | #define CLOCK_SETUP_REG 1 |
| mbed_official | 103:9b881da47c92 | 55 | // |
| mbed_official | 103:9b881da47c92 | 56 | // <o.0..1> Main Clock Source Select A (MAINCLKSELA) |
| mbed_official | 103:9b881da47c92 | 57 | // <0=> IRC Oscillator |
| mbed_official | 103:9b881da47c92 | 58 | // <1=> System Oscillator |
| mbed_official | 103:9b881da47c92 | 59 | // <2=> WD Oscillator |
| mbed_official | 103:9b881da47c92 | 60 | #define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 61 | // |
| mbed_official | 103:9b881da47c92 | 62 | // <o.0..1> Main Clock Source Select B (MAINCLKSELB) |
| mbed_official | 103:9b881da47c92 | 63 | // <0=> MAINCLKSELA |
| mbed_official | 103:9b881da47c92 | 64 | // <1=> System PLL Input |
| mbed_official | 103:9b881da47c92 | 65 | // <2=> System PLL Output |
| mbed_official | 103:9b881da47c92 | 66 | // <3=> RTC Oscillator |
| mbed_official | 103:9b881da47c92 | 67 | #define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 68 | // |
| mbed_official | 103:9b881da47c92 | 69 | // <h> System PLL Setting (SYSPLLCTRL) |
| mbed_official | 103:9b881da47c92 | 70 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| mbed_official | 103:9b881da47c92 | 71 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| mbed_official | 103:9b881da47c92 | 72 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| mbed_official | 103:9b881da47c92 | 73 | // <o.0..5> MSEL: Feedback Divider Selection |
| mbed_official | 103:9b881da47c92 | 74 | // <i> M = MSEL + 1 |
| mbed_official | 103:9b881da47c92 | 75 | // <0-31> |
| mbed_official | 103:9b881da47c92 | 76 | // <o.5..7> PSEL: Post Divider Selection |
| mbed_official | 103:9b881da47c92 | 77 | // <i> Post divider ratio P. Division ratio is 2 * P |
| mbed_official | 103:9b881da47c92 | 78 | // <0=> P = 1 |
| mbed_official | 103:9b881da47c92 | 79 | // <1=> P = 2 |
| mbed_official | 103:9b881da47c92 | 80 | // <2=> P = 4 |
| mbed_official | 103:9b881da47c92 | 81 | // <3=> P = 8 |
| mbed_official | 103:9b881da47c92 | 82 | // </h> |
| mbed_official | 103:9b881da47c92 | 83 | #define SYSPLLCTRL_Val 0x00000005 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 84 | // |
| mbed_official | 103:9b881da47c92 | 85 | // <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV) |
| mbed_official | 103:9b881da47c92 | 86 | // <i> Divides main clock to provide system clock to core, memories, and peripherals. |
| mbed_official | 103:9b881da47c92 | 87 | // <i> 0 = is disabled |
| mbed_official | 103:9b881da47c92 | 88 | // <0-255> |
| mbed_official | 103:9b881da47c92 | 89 | #define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001 |
| mbed_official | 103:9b881da47c92 | 90 | // </e> |
| mbed_official | 103:9b881da47c92 | 91 | // |
| mbed_official | 103:9b881da47c92 | 92 | // <e> Clock Configuration (via ROM PLL API) |
| mbed_official | 103:9b881da47c92 | 93 | #define CLOCK_SETUP_API 0 |
| mbed_official | 103:9b881da47c92 | 94 | // |
| mbed_official | 103:9b881da47c92 | 95 | // <o> PLL API Mode Select |
| mbed_official | 103:9b881da47c92 | 96 | // <0=> Exact |
| mbed_official | 103:9b881da47c92 | 97 | // <1=> Less than or equal |
| mbed_official | 103:9b881da47c92 | 98 | // <2=> Greater than or equal |
| mbed_official | 103:9b881da47c92 | 99 | // <3=> As close as possible |
| mbed_official | 103:9b881da47c92 | 100 | #define PLL_API_MODE_Val 0 |
| mbed_official | 103:9b881da47c92 | 101 | // |
| mbed_official | 103:9b881da47c92 | 102 | // <o> CPU Frequency [Hz] <1000000-72000000:1000> |
| mbed_official | 103:9b881da47c92 | 103 | #define PLL_API_FREQ_Val 72000000 |
| mbed_official | 103:9b881da47c92 | 104 | // </e> |
| mbed_official | 103:9b881da47c92 | 105 | // |
| mbed_official | 103:9b881da47c92 | 106 | // <e> USB Clock Configuration |
| mbed_official | 103:9b881da47c92 | 107 | #define USB_CLOCK_SETUP 0 |
| mbed_official | 103:9b881da47c92 | 108 | // <h> USB PLL Control (USBPLLCTRL) |
| mbed_official | 103:9b881da47c92 | 109 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| mbed_official | 103:9b881da47c92 | 110 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| mbed_official | 103:9b881da47c92 | 111 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| mbed_official | 103:9b881da47c92 | 112 | // <o.0..5> MSEL: Feedback Divider Selection |
| mbed_official | 103:9b881da47c92 | 113 | // <i> M = MSEL + 1 |
| mbed_official | 103:9b881da47c92 | 114 | // <0-31> |
| mbed_official | 103:9b881da47c92 | 115 | // <o.7..6> PSEL: Post Divider Selection |
| mbed_official | 103:9b881da47c92 | 116 | // <i> Post divider ratio P. Division ratio is 2 * P |
| mbed_official | 103:9b881da47c92 | 117 | // <0=> P = 1 |
| mbed_official | 103:9b881da47c92 | 118 | // <1=> P = 2 |
| mbed_official | 103:9b881da47c92 | 119 | // <2=> P = 4 |
| mbed_official | 103:9b881da47c92 | 120 | // <3=> P = 8 |
| mbed_official | 103:9b881da47c92 | 121 | // </h> |
| mbed_official | 103:9b881da47c92 | 122 | #define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 123 | // |
| mbed_official | 103:9b881da47c92 | 124 | // <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL) |
| mbed_official | 103:9b881da47c92 | 125 | // <0=> IRC Oscillator |
| mbed_official | 103:9b881da47c92 | 126 | // <1=> System Oscillator |
| mbed_official | 103:9b881da47c92 | 127 | #define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 128 | // |
| mbed_official | 103:9b881da47c92 | 129 | // <o.0..1> USB Clock Source Select (USBCLKSEL.SEL) |
| mbed_official | 103:9b881da47c92 | 130 | // <0=> IRC Oscillator |
| mbed_official | 103:9b881da47c92 | 131 | // <1=> System Oscillator |
| mbed_official | 103:9b881da47c92 | 132 | // <2=> USB PLL out |
| mbed_official | 103:9b881da47c92 | 133 | // <3=> Main clock |
| mbed_official | 103:9b881da47c92 | 134 | #define USBCLKSEL_Val 0x00000002 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 135 | // |
| mbed_official | 103:9b881da47c92 | 136 | // <o.0..7> USB Clock Divider (USBCLKDIV.DIV) |
| mbed_official | 103:9b881da47c92 | 137 | // <i> Divides USB clock to 48 MHz. |
| mbed_official | 103:9b881da47c92 | 138 | // <i> 0 = is disabled |
| mbed_official | 103:9b881da47c92 | 139 | // <0-255> |
| mbed_official | 103:9b881da47c92 | 140 | #define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001 |
| mbed_official | 103:9b881da47c92 | 141 | // </e> |
| mbed_official | 103:9b881da47c92 | 142 | // |
| mbed_official | 103:9b881da47c92 | 143 | // <e> SCT Clock Configuration |
| mbed_official | 103:9b881da47c92 | 144 | #define SCT_CLOCK_SETUP 1 |
| mbed_official | 103:9b881da47c92 | 145 | // <h> SCT PLL Control (SCTPLLCTRL) |
| mbed_official | 103:9b881da47c92 | 146 | // <i> F_clkout = M * F_clkin = F_CCO / (2 * P) |
| mbed_official | 103:9b881da47c92 | 147 | // <i> F_clkin must be in the range of 10 MHz to 25 MHz |
| mbed_official | 103:9b881da47c92 | 148 | // <i> F_CCO must be in the range of 156 MHz to 320 MHz |
| mbed_official | 103:9b881da47c92 | 149 | // <o.0..5> MSEL: Feedback Divider Selection |
| mbed_official | 103:9b881da47c92 | 150 | // <i> M = MSEL + 1 |
| mbed_official | 103:9b881da47c92 | 151 | // <0-31> |
| mbed_official | 103:9b881da47c92 | 152 | // <o.7..6> PSEL: Post Divider Selection |
| mbed_official | 103:9b881da47c92 | 153 | // <i> Post divider ratio P. Division ratio is 2 * P |
| mbed_official | 103:9b881da47c92 | 154 | // <0=> P = 1 |
| mbed_official | 103:9b881da47c92 | 155 | // <1=> P = 2 |
| mbed_official | 103:9b881da47c92 | 156 | // <2=> P = 4 |
| mbed_official | 103:9b881da47c92 | 157 | // <3=> P = 8 |
| mbed_official | 103:9b881da47c92 | 158 | // </h> |
| mbed_official | 103:9b881da47c92 | 159 | #define SCTPLLCTRL_Val 0x00000005 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 160 | // |
| mbed_official | 103:9b881da47c92 | 161 | // <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL) |
| mbed_official | 103:9b881da47c92 | 162 | // <0=> IRC Oscillator |
| mbed_official | 103:9b881da47c92 | 163 | // <1=> System Oscillator |
| mbed_official | 103:9b881da47c92 | 164 | #define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000 |
| mbed_official | 103:9b881da47c92 | 165 | // </e> |
| mbed_official | 103:9b881da47c92 | 166 | // |
| mbed_official | 103:9b881da47c92 | 167 | // </e> |
| mbed_official | 103:9b881da47c92 | 168 | // |
| mbed_official | 103:9b881da47c92 | 169 | // <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000> |
| mbed_official | 103:9b881da47c92 | 170 | // <i> XTAL frequency must be in the range of 1 MHz to 25 MHz |
| mbed_official | 103:9b881da47c92 | 171 | // |
| mbed_official | 103:9b881da47c92 | 172 | #define XTAL_CLK_Val 12000000 |
| mbed_official | 103:9b881da47c92 | 173 | |
| mbed_official | 103:9b881da47c92 | 174 | /* |
| mbed_official | 103:9b881da47c92 | 175 | //-------- <<< end of configuration section >>> ------------------------------ |
| mbed_official | 103:9b881da47c92 | 176 | */ |
| mbed_official | 103:9b881da47c92 | 177 | |
| mbed_official | 103:9b881da47c92 | 178 | /*---------------------------------------------------------------------------- |
| mbed_official | 103:9b881da47c92 | 179 | Define clocks |
| mbed_official | 103:9b881da47c92 | 180 | *----------------------------------------------------------------------------*/ |
| mbed_official | 103:9b881da47c92 | 181 | #define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */ |
| mbed_official | 103:9b881da47c92 | 182 | #define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */ |
| mbed_official | 103:9b881da47c92 | 183 | #define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */ |
| mbed_official | 103:9b881da47c92 | 184 | #define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */ |
| mbed_official | 103:9b881da47c92 | 185 | #define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */ |
| mbed_official | 103:9b881da47c92 | 186 | |
| mbed_official | 103:9b881da47c92 | 187 | /*---------------------------------------------------------------------------- |
| mbed_official | 103:9b881da47c92 | 188 | Check the register settings |
| mbed_official | 103:9b881da47c92 | 189 | *----------------------------------------------------------------------------*/ |
| mbed_official | 103:9b881da47c92 | 190 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
| mbed_official | 103:9b881da47c92 | 191 | #define CHECK_RSVD(val, mask) (val & mask) |
| mbed_official | 103:9b881da47c92 | 192 | |
| mbed_official | 103:9b881da47c92 | 193 | #if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1)) |
| mbed_official | 103:9b881da47c92 | 194 | #error "SYSOSCCTRL: Invalid values of reserved bits!" |
| mbed_official | 103:9b881da47c92 | 195 | #endif |
| mbed_official | 103:9b881da47c92 | 196 | |
| mbed_official | 103:9b881da47c92 | 197 | #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) |
| mbed_official | 103:9b881da47c92 | 198 | #error "SYSPLLCLKSEL: Value out of range!" |
| mbed_official | 103:9b881da47c92 | 199 | #endif |
| mbed_official | 103:9b881da47c92 | 200 | |
| mbed_official | 103:9b881da47c92 | 201 | #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF)) |
| mbed_official | 103:9b881da47c92 | 202 | #error "SYSPLLCTRL: Invalid values of reserved bits!" |
| mbed_official | 103:9b881da47c92 | 203 | #endif |
| mbed_official | 103:9b881da47c92 | 204 | |
| mbed_official | 103:9b881da47c92 | 205 | #if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2)) |
| mbed_official | 103:9b881da47c92 | 206 | #error "MAINCLKSELA: Invalid values of reserved bits!" |
| mbed_official | 103:9b881da47c92 | 207 | #endif |
| mbed_official | 103:9b881da47c92 | 208 | |
| mbed_official | 103:9b881da47c92 | 209 | #if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003)) |
| mbed_official | 103:9b881da47c92 | 210 | #error "MAINCLKSELB: Invalid values of reserved bits!" |
| mbed_official | 103:9b881da47c92 | 211 | #endif |
| mbed_official | 103:9b881da47c92 | 212 | |
| mbed_official | 103:9b881da47c92 | 213 | #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) |
| mbed_official | 103:9b881da47c92 | 214 | #error "SYSAHBCLKDIV: Value out of range!" |
| mbed_official | 103:9b881da47c92 | 215 | #endif |
| mbed_official | 103:9b881da47c92 | 216 | |
| mbed_official | 103:9b881da47c92 | 217 | #if ( CLOCK_SETUP_REG == CLOCK_SETUP_API ) |
| mbed_official | 103:9b881da47c92 | 218 | #error "You must select either manual or API based Clock Configuration!" |
| mbed_official | 103:9b881da47c92 | 219 | #endif |
| mbed_official | 103:9b881da47c92 | 220 | |
| mbed_official | 103:9b881da47c92 | 221 | #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1)) |
| mbed_official | 103:9b881da47c92 | 222 | #error "USBPLLCLKSEL: Value out of range!" |
| mbed_official | 103:9b881da47c92 | 223 | #endif |
| mbed_official | 103:9b881da47c92 | 224 | |
| mbed_official | 103:9b881da47c92 | 225 | #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF)) |
| mbed_official | 103:9b881da47c92 | 226 | #error "USBPLLCTRL: Invalid values of reserved bits!" |
| mbed_official | 103:9b881da47c92 | 227 | #endif |
| mbed_official | 103:9b881da47c92 | 228 | |
| mbed_official | 103:9b881da47c92 | 229 | #if (CHECK_RANGE((USBCLKSEL_Val), 0, 3)) |
| mbed_official | 103:9b881da47c92 | 230 | #error "USBCLKSEL: Value out of range!" |
| mbed_official | 103:9b881da47c92 | 231 | #endif |
| mbed_official | 103:9b881da47c92 | 232 | |
| mbed_official | 103:9b881da47c92 | 233 | #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255)) |
| mbed_official | 103:9b881da47c92 | 234 | #error "USBCLKDIV: Value out of range!" |
| mbed_official | 103:9b881da47c92 | 235 | #endif |
| mbed_official | 103:9b881da47c92 | 236 | |
| mbed_official | 103:9b881da47c92 | 237 | #if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1)) |
| mbed_official | 103:9b881da47c92 | 238 | #error "SCTPLLCLKSEL: Value out of range!" |
| mbed_official | 103:9b881da47c92 | 239 | #endif |
| mbed_official | 103:9b881da47c92 | 240 | |
| mbed_official | 103:9b881da47c92 | 241 | #if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF)) |
| mbed_official | 103:9b881da47c92 | 242 | #error "SCTPLLCTRL: Invalid values of reserved bits!" |
| mbed_official | 103:9b881da47c92 | 243 | #endif |
| mbed_official | 103:9b881da47c92 | 244 | |
| mbed_official | 103:9b881da47c92 | 245 | #if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000)) |
| mbed_official | 103:9b881da47c92 | 246 | #error "XTAL frequency is out of bounds" |
| mbed_official | 103:9b881da47c92 | 247 | #endif |
| mbed_official | 103:9b881da47c92 | 248 | |
| mbed_official | 103:9b881da47c92 | 249 | #if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3)) |
| mbed_official | 103:9b881da47c92 | 250 | #error "PLL API Mode Select not valid" |
| mbed_official | 103:9b881da47c92 | 251 | #endif |
| mbed_official | 103:9b881da47c92 | 252 | |
| mbed_official | 103:9b881da47c92 | 253 | #if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000)) |
| mbed_official | 103:9b881da47c92 | 254 | #error "CPU Frequency (API mode) not valid" |
| mbed_official | 103:9b881da47c92 | 255 | #endif |
| mbed_official | 103:9b881da47c92 | 256 | |
| mbed_official | 103:9b881da47c92 | 257 | |
| mbed_official | 103:9b881da47c92 | 258 | |
| mbed_official | 103:9b881da47c92 | 259 | /*---------------------------------------------------------------------------- |
| mbed_official | 103:9b881da47c92 | 260 | Calculate system core clock |
| mbed_official | 103:9b881da47c92 | 261 | *----------------------------------------------------------------------------*/ |
| mbed_official | 103:9b881da47c92 | 262 | #if (CLOCK_SETUP) /* Clock Setup */ |
| mbed_official | 103:9b881da47c92 | 263 | |
| mbed_official | 103:9b881da47c92 | 264 | /* sys_pllclkin calculation */ |
| mbed_official | 103:9b881da47c92 | 265 | #if ((SYSPLLCLKSEL_Val & 0x03) == 0) |
| mbed_official | 103:9b881da47c92 | 266 | #define __SYS_PLLCLKIN (__IRC_OSC_CLK) |
| mbed_official | 103:9b881da47c92 | 267 | #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) |
| mbed_official | 103:9b881da47c92 | 268 | #define __SYS_PLLCLKIN (__SYS_OSC_CLK) |
| mbed_official | 103:9b881da47c92 | 269 | #else |
| mbed_official | 103:9b881da47c92 | 270 | #error "Oops" |
| mbed_official | 103:9b881da47c92 | 271 | #endif |
| mbed_official | 103:9b881da47c92 | 272 | |
| mbed_official | 103:9b881da47c92 | 273 | #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ |
| mbed_official | 103:9b881da47c92 | 274 | |
| mbed_official | 103:9b881da47c92 | 275 | #if ((MAINCLKSELA_Val & 0x03) == 0) |
| mbed_official | 103:9b881da47c92 | 276 | #define __MAINA_CLOCK (__IRC_OSC_CLK) |
| mbed_official | 103:9b881da47c92 | 277 | #elif ((MAINCLKSELA_Val & 0x03) == 1) |
| mbed_official | 103:9b881da47c92 | 278 | #define __MAINA_CLOCK (__SYS_OSC_CLK) |
| mbed_official | 103:9b881da47c92 | 279 | #elif ((MAINCLKSELA_Val & 0x03) == 2) |
| mbed_official | 103:9b881da47c92 | 280 | #define __MAINA_CLOCK (__WDT_OSC_CLK) |
| mbed_official | 103:9b881da47c92 | 281 | #else |
| mbed_official | 103:9b881da47c92 | 282 | #error "Oops" |
| mbed_official | 103:9b881da47c92 | 283 | #endif |
| mbed_official | 103:9b881da47c92 | 284 | |
| mbed_official | 103:9b881da47c92 | 285 | #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) |
| mbed_official | 103:9b881da47c92 | 286 | |
| mbed_official | 103:9b881da47c92 | 287 | /* main clock calculation */ |
| mbed_official | 103:9b881da47c92 | 288 | #if ((MAINCLKSELB_Val & 0x03) == 0) |
| mbed_official | 103:9b881da47c92 | 289 | #define __MAINB_CLOCK (__MAINA_CLOCK) |
| mbed_official | 103:9b881da47c92 | 290 | #elif ((MAINCLKSELB_Val & 0x03) == 1) |
| mbed_official | 103:9b881da47c92 | 291 | #define __MAINB_CLOCK (__SYS_PLLCLKIN) |
| mbed_official | 103:9b881da47c92 | 292 | #elif ((MAINCLKSELB_Val & 0x03) == 2) |
| mbed_official | 103:9b881da47c92 | 293 | #define __MAINB_CLOCK (__SYS_PLLCLKOUT) |
| mbed_official | 103:9b881da47c92 | 294 | #elif ((MAINCLKSELB_Val & 0x03) == 3) |
| mbed_official | 103:9b881da47c92 | 295 | #define __MAINB_CLOCK (__RTC_OSC_CLK) |
| mbed_official | 103:9b881da47c92 | 296 | #else |
| mbed_official | 103:9b881da47c92 | 297 | #error "Oops" |
| mbed_official | 103:9b881da47c92 | 298 | #endif |
| mbed_official | 103:9b881da47c92 | 299 | |
| mbed_official | 103:9b881da47c92 | 300 | #define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val) |
| mbed_official | 103:9b881da47c92 | 301 | #endif /* Clock Setup via Register */ |
| mbed_official | 103:9b881da47c92 | 302 | |
| mbed_official | 103:9b881da47c92 | 303 | #if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */ |
| mbed_official | 103:9b881da47c92 | 304 | #define __SYSTEM_CLOCK (PLL_API_FREQ_Val) |
| mbed_official | 103:9b881da47c92 | 305 | #endif /* Clock Setup via PLL API */ |
| mbed_official | 103:9b881da47c92 | 306 | |
| mbed_official | 103:9b881da47c92 | 307 | #else |
| mbed_official | 103:9b881da47c92 | 308 | #define __SYSTEM_CLOCK (__IRC_OSC_CLK) |
| mbed_official | 103:9b881da47c92 | 309 | #endif /* CLOCK_SETUP */ |
| mbed_official | 103:9b881da47c92 | 310 | |
| mbed_official | 103:9b881da47c92 | 311 | |
| mbed_official | 103:9b881da47c92 | 312 | |
| mbed_official | 103:9b881da47c92 | 313 | #if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */ |
| mbed_official | 103:9b881da47c92 | 314 | #include "power_api.h" |
| mbed_official | 103:9b881da47c92 | 315 | |
| mbed_official | 103:9b881da47c92 | 316 | typedef struct _ROM { |
| mbed_official | 103:9b881da47c92 | 317 | const unsigned p_dev0; |
| mbed_official | 103:9b881da47c92 | 318 | const unsigned p_dev1; |
| mbed_official | 103:9b881da47c92 | 319 | const unsigned p_dev2; |
| mbed_official | 103:9b881da47c92 | 320 | const PWRD * pPWRD; /* ROM Power Management API */ |
| mbed_official | 103:9b881da47c92 | 321 | const unsigned p_dev4; |
| mbed_official | 103:9b881da47c92 | 322 | const unsigned p_dev5; |
| mbed_official | 103:9b881da47c92 | 323 | const unsigned p_dev6; |
| mbed_official | 103:9b881da47c92 | 324 | const unsigned p_dev7; |
| mbed_official | 103:9b881da47c92 | 325 | } ROM; |
| mbed_official | 103:9b881da47c92 | 326 | |
| mbed_official | 103:9b881da47c92 | 327 | /*---------------------------------------------------------------------------- |
| mbed_official | 103:9b881da47c92 | 328 | PLL API Function |
| mbed_official | 103:9b881da47c92 | 329 | *----------------------------------------------------------------------------*/ |
| mbed_official | 103:9b881da47c92 | 330 | static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq) |
| mbed_official | 103:9b881da47c92 | 331 | { |
| mbed_official | 103:9b881da47c92 | 332 | uint32_t cmd[5], res[5]; |
| mbed_official | 103:9b881da47c92 | 333 | ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */ |
| mbed_official | 103:9b881da47c92 | 334 | |
| mbed_official | 103:9b881da47c92 | 335 | cmd[0] = pllInFreq; /* PLL's input freq in KHz */ |
| mbed_official | 103:9b881da47c92 | 336 | cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */ |
| mbed_official | 103:9b881da47c92 | 337 | cmd[2] = pllMode; |
| mbed_official | 103:9b881da47c92 | 338 | cmd[3] = 0; /* no timeout for PLL to lock */ |
| mbed_official | 103:9b881da47c92 | 339 | |
| mbed_official | 103:9b881da47c92 | 340 | /* Execute API call */ |
| mbed_official | 103:9b881da47c92 | 341 | (*rom)->pPWRD->set_pll(cmd, res); /* call API function */ |
| mbed_official | 103:9b881da47c92 | 342 | if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */ |
| mbed_official | 103:9b881da47c92 | 343 | while(1); /* ... stay here */ |
| mbed_official | 103:9b881da47c92 | 344 | } |
| mbed_official | 103:9b881da47c92 | 345 | } |
| mbed_official | 103:9b881da47c92 | 346 | #endif |
| mbed_official | 103:9b881da47c92 | 347 | |
| mbed_official | 103:9b881da47c92 | 348 | |
| mbed_official | 103:9b881da47c92 | 349 | |
| mbed_official | 103:9b881da47c92 | 350 | |
| mbed_official | 103:9b881da47c92 | 351 | /*---------------------------------------------------------------------------- |
| mbed_official | 103:9b881da47c92 | 352 | Clock Variable definitions |
| mbed_official | 103:9b881da47c92 | 353 | *----------------------------------------------------------------------------*/ |
| mbed_official | 103:9b881da47c92 | 354 | uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */ |
| mbed_official | 103:9b881da47c92 | 355 | |
| mbed_official | 103:9b881da47c92 | 356 | |
| mbed_official | 103:9b881da47c92 | 357 | /*---------------------------------------------------------------------------- |
| mbed_official | 103:9b881da47c92 | 358 | Clock functions |
| mbed_official | 103:9b881da47c92 | 359 | *----------------------------------------------------------------------------*/ |
| mbed_official | 103:9b881da47c92 | 360 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ |
| mbed_official | 103:9b881da47c92 | 361 | { |
| mbed_official | 103:9b881da47c92 | 362 | /* Determine clock frequency according to clock register values */ |
| mbed_official | 103:9b881da47c92 | 363 | switch (LPC_SYSCON->MAINCLKSELB & 0x03) { |
| mbed_official | 103:9b881da47c92 | 364 | case 0: /* MAINCLKSELA clock sel */ |
| mbed_official | 103:9b881da47c92 | 365 | switch (LPC_SYSCON->MAINCLKSELA & 0x03) { |
| mbed_official | 103:9b881da47c92 | 366 | case 0: /* Internal RC oscillator */ |
| mbed_official | 103:9b881da47c92 | 367 | SystemCoreClock = __IRC_OSC_CLK; |
| mbed_official | 103:9b881da47c92 | 368 | break; |
| mbed_official | 103:9b881da47c92 | 369 | case 1: /* System oscillator */ |
| mbed_official | 103:9b881da47c92 | 370 | SystemCoreClock = __SYS_OSC_CLK; |
| mbed_official | 103:9b881da47c92 | 371 | break; |
| mbed_official | 103:9b881da47c92 | 372 | case 2: /* Watchdog oscillator */ |
| mbed_official | 103:9b881da47c92 | 373 | SystemCoreClock = __WDT_OSC_CLK; |
| mbed_official | 103:9b881da47c92 | 374 | break; |
| mbed_official | 103:9b881da47c92 | 375 | case 3: /* Reserved */ |
| mbed_official | 103:9b881da47c92 | 376 | SystemCoreClock = 0; |
| mbed_official | 103:9b881da47c92 | 377 | break; |
| mbed_official | 103:9b881da47c92 | 378 | } |
| mbed_official | 103:9b881da47c92 | 379 | break; |
| mbed_official | 103:9b881da47c92 | 380 | case 1: /* Input Clock to System PLL */ |
| mbed_official | 103:9b881da47c92 | 381 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
| mbed_official | 103:9b881da47c92 | 382 | case 0: /* Internal RC oscillator */ |
| mbed_official | 103:9b881da47c92 | 383 | SystemCoreClock = __IRC_OSC_CLK; |
| mbed_official | 103:9b881da47c92 | 384 | break; |
| mbed_official | 103:9b881da47c92 | 385 | case 1: /* System oscillator */ |
| mbed_official | 103:9b881da47c92 | 386 | SystemCoreClock = __SYS_OSC_CLK; |
| mbed_official | 103:9b881da47c92 | 387 | break; |
| mbed_official | 103:9b881da47c92 | 388 | case 2: /* Reserved */ |
| mbed_official | 103:9b881da47c92 | 389 | case 3: /* Reserved */ |
| mbed_official | 103:9b881da47c92 | 390 | SystemCoreClock = 0; |
| mbed_official | 103:9b881da47c92 | 391 | break; |
| mbed_official | 103:9b881da47c92 | 392 | } |
| mbed_official | 103:9b881da47c92 | 393 | break; |
| mbed_official | 103:9b881da47c92 | 394 | case 2: /* System PLL Clock Out */ |
| mbed_official | 103:9b881da47c92 | 395 | switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { |
| mbed_official | 103:9b881da47c92 | 396 | case 0: /* Internal RC oscillator */ |
| mbed_official | 103:9b881da47c92 | 397 | SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
| mbed_official | 103:9b881da47c92 | 398 | break; |
| mbed_official | 103:9b881da47c92 | 399 | case 1: /* System oscillator */ |
| mbed_official | 103:9b881da47c92 | 400 | SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); |
| mbed_official | 103:9b881da47c92 | 401 | break; |
| mbed_official | 103:9b881da47c92 | 402 | case 2: /* Reserved */ |
| mbed_official | 103:9b881da47c92 | 403 | case 3: /* Reserved */ |
| mbed_official | 103:9b881da47c92 | 404 | SystemCoreClock = 0; |
| mbed_official | 103:9b881da47c92 | 405 | break; |
| mbed_official | 103:9b881da47c92 | 406 | } |
| mbed_official | 103:9b881da47c92 | 407 | break; |
| mbed_official | 103:9b881da47c92 | 408 | case 3: /* WDT Oscillator */ |
| mbed_official | 103:9b881da47c92 | 409 | SystemCoreClock = __WDT_OSC_CLK; |
| mbed_official | 103:9b881da47c92 | 410 | break; |
| mbed_official | 103:9b881da47c92 | 411 | } |
| mbed_official | 103:9b881da47c92 | 412 | |
| mbed_official | 103:9b881da47c92 | 413 | SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; |
| mbed_official | 103:9b881da47c92 | 414 | |
| mbed_official | 103:9b881da47c92 | 415 | } |
| mbed_official | 103:9b881da47c92 | 416 | |
| mbed_official | 103:9b881da47c92 | 417 | /** |
| mbed_official | 103:9b881da47c92 | 418 | * Initialize the system |
| mbed_official | 103:9b881da47c92 | 419 | * |
| mbed_official | 103:9b881da47c92 | 420 | * @param none |
| mbed_official | 103:9b881da47c92 | 421 | * @return none |
| mbed_official | 103:9b881da47c92 | 422 | * |
| mbed_official | 103:9b881da47c92 | 423 | * @brief Setup the microcontroller system. |
| mbed_official | 103:9b881da47c92 | 424 | */ |
| mbed_official | 103:9b881da47c92 | 425 | void SystemInit (void) { |
| mbed_official | 103:9b881da47c92 | 426 | #if (CLOCK_SETUP) |
| mbed_official | 103:9b881da47c92 | 427 | volatile uint32_t i; |
| mbed_official | 103:9b881da47c92 | 428 | #endif |
| mbed_official | 103:9b881da47c92 | 429 | |
| mbed_official | 103:9b881da47c92 | 430 | #if (CLOCK_SETUP) /* Clock Setup */ |
| mbed_official | 103:9b881da47c92 | 431 | |
| mbed_official | 103:9b881da47c92 | 432 | #if ((SYSPLLCLKSEL_Val & 0x03) == 1) |
| mbed_official | 103:9b881da47c92 | 433 | LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; |
| mbed_official | 103:9b881da47c92 | 434 | LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */ |
| mbed_official | 103:9b881da47c92 | 435 | for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ |
| mbed_official | 103:9b881da47c92 | 436 | #endif |
| mbed_official | 103:9b881da47c92 | 437 | |
| mbed_official | 103:9b881da47c92 | 438 | LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ |
| mbed_official | 103:9b881da47c92 | 439 | |
| mbed_official | 103:9b881da47c92 | 440 | #if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */ |
| mbed_official | 103:9b881da47c92 | 441 | |
| mbed_official | 103:9b881da47c92 | 442 | #if (((MAINCLKSELA_Val & 0x03) == 1) ) |
| mbed_official | 103:9b881da47c92 | 443 | LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; |
| mbed_official | 103:9b881da47c92 | 444 | LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */ |
| mbed_official | 103:9b881da47c92 | 445 | for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ |
| mbed_official | 103:9b881da47c92 | 446 | #endif |
| mbed_official | 103:9b881da47c92 | 447 | |
| mbed_official | 103:9b881da47c92 | 448 | #if (((MAINCLKSELA_Val & 0x03) == 2) ) |
| mbed_official | 103:9b881da47c92 | 449 | LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */ |
| mbed_official | 103:9b881da47c92 | 450 | for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ |
| mbed_official | 103:9b881da47c92 | 451 | #endif |
| mbed_official | 103:9b881da47c92 | 452 | |
| mbed_official | 103:9b881da47c92 | 453 | #if ((MAINCLKSELB_Val & 0x03) == 3) |
| mbed_official | 103:9b881da47c92 | 454 | LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */ |
| mbed_official | 103:9b881da47c92 | 455 | for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */ |
| mbed_official | 103:9b881da47c92 | 456 | #endif |
| mbed_official | 103:9b881da47c92 | 457 | |
| mbed_official | 103:9b881da47c92 | 458 | LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */ |
| mbed_official | 103:9b881da47c92 | 459 | |
| mbed_official | 103:9b881da47c92 | 460 | #if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */ |
| mbed_official | 103:9b881da47c92 | 461 | LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; |
| mbed_official | 103:9b881da47c92 | 462 | LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */ |
| mbed_official | 103:9b881da47c92 | 463 | while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
| mbed_official | 103:9b881da47c92 | 464 | #endif |
| mbed_official | 103:9b881da47c92 | 465 | |
| mbed_official | 103:9b881da47c92 | 466 | LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */ |
| mbed_official | 103:9b881da47c92 | 467 | |
| mbed_official | 103:9b881da47c92 | 468 | LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; |
| mbed_official | 103:9b881da47c92 | 469 | #endif /* Clock Setup via Register */ |
| mbed_official | 103:9b881da47c92 | 470 | |
| mbed_official | 103:9b881da47c92 | 471 | #if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */ |
| mbed_official | 103:9b881da47c92 | 472 | // LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */ |
| mbed_official | 103:9b881da47c92 | 473 | |
| mbed_official | 103:9b881da47c92 | 474 | LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */ |
| mbed_official | 103:9b881da47c92 | 475 | |
| mbed_official | 103:9b881da47c92 | 476 | LPC_SYSCON->SYSAHBCLKDIV = 1; |
| mbed_official | 103:9b881da47c92 | 477 | |
| mbed_official | 103:9b881da47c92 | 478 | setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000); |
| mbed_official | 103:9b881da47c92 | 479 | #endif /* Clock Setup via PLL API */ |
| mbed_official | 103:9b881da47c92 | 480 | |
| mbed_official | 103:9b881da47c92 | 481 | #if (USB_CLOCK_SETUP == 1) /* USB clock is used */ |
| mbed_official | 103:9b881da47c92 | 482 | LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */ |
| mbed_official | 103:9b881da47c92 | 483 | |
| mbed_official | 103:9b881da47c92 | 484 | #if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */ |
| mbed_official | 103:9b881da47c92 | 485 | LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */ |
| mbed_official | 103:9b881da47c92 | 486 | LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */ |
| mbed_official | 103:9b881da47c92 | 487 | |
| mbed_official | 103:9b881da47c92 | 488 | LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val; |
| mbed_official | 103:9b881da47c92 | 489 | while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
| mbed_official | 103:9b881da47c92 | 490 | |
| mbed_official | 103:9b881da47c92 | 491 | LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */ |
| mbed_official | 103:9b881da47c92 | 492 | #endif |
| mbed_official | 103:9b881da47c92 | 493 | |
| mbed_official | 103:9b881da47c92 | 494 | LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */ |
| mbed_official | 103:9b881da47c92 | 495 | LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */ |
| mbed_official | 103:9b881da47c92 | 496 | |
| mbed_official | 103:9b881da47c92 | 497 | #else /* USB clock is not used */ |
| mbed_official | 103:9b881da47c92 | 498 | LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */ |
| mbed_official | 103:9b881da47c92 | 499 | LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */ |
| mbed_official | 103:9b881da47c92 | 500 | #endif |
| mbed_official | 103:9b881da47c92 | 501 | |
| mbed_official | 103:9b881da47c92 | 502 | #if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */ |
| mbed_official | 103:9b881da47c92 | 503 | LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */ |
| mbed_official | 103:9b881da47c92 | 504 | LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */ |
| mbed_official | 103:9b881da47c92 | 505 | |
| mbed_official | 103:9b881da47c92 | 506 | LPC_SYSCON->SCTPLLCTRL = SCTPLLCTRL_Val; |
| mbed_official | 103:9b881da47c92 | 507 | while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */ |
| mbed_official | 103:9b881da47c92 | 508 | #else /* SCT clock is not used */ |
| mbed_official | 103:9b881da47c92 | 509 | LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */ |
| mbed_official | 103:9b881da47c92 | 510 | #endif |
| mbed_official | 103:9b881da47c92 | 511 | |
| mbed_official | 103:9b881da47c92 | 512 | #endif /* Clock Setup */ |
| mbed_official | 103:9b881da47c92 | 513 | |
| mbed_official | 103:9b881da47c92 | 514 | |
| mbed_official | 103:9b881da47c92 | 515 | LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << 12); /* enable clock for SWM */ |
| mbed_official | 103:9b881da47c92 | 516 | |
| mbed_official | 103:9b881da47c92 | 517 | } |