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mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/cmsis_nvic.c@30:91c1d09ada54, 2013-09-25 (annotated)

Committer:
mbed_official
Date:
Wed Sep 25 10:30:04 2013 +0100
Revision:
30:91c1d09ada54
Child:
358:9d7ef901f004
Synchronized with git revision 8f57c1e84759991fa81ede0da2b4aabe8530fa09

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 30:91c1d09ada54 1 /* mbed Microcontroller Library - cmsis_nvic for LPC11U24
mbed_official 30:91c1d09ada54 2 * Copyright (c) 2011 ARM Limited. All rights reserved.
mbed_official 30:91c1d09ada54 3 *
mbed_official 30:91c1d09ada54 4 * CMSIS-style functionality to support dynamic vectors
mbed_official 30:91c1d09ada54 5 */
mbed_official 30:91c1d09ada54 6
mbed_official 30:91c1d09ada54 7 #include "cmsis_nvic.h"
mbed_official 30:91c1d09ada54 8
mbed_official 30:91c1d09ada54 9 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
mbed_official 30:91c1d09ada54 10 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
mbed_official 30:91c1d09ada54 11 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
mbed_official 30:91c1d09ada54 12 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
mbed_official 30:91c1d09ada54 13 *
mbed_official 30:91c1d09ada54 14 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
mbed_official 30:91c1d09ada54 15 * above the vector table before 0x200 will actually go to RAM. So we need to provide
mbed_official 30:91c1d09ada54 16 * a solution where the compiler gets the right results based on the memory map
mbed_official 30:91c1d09ada54 17 *
mbed_official 30:91c1d09ada54 18 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
mbed_official 30:91c1d09ada54 19 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
mbed_official 30:91c1d09ada54 20 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
mbed_official 30:91c1d09ada54 21 *
mbed_official 30:91c1d09ada54 22 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
mbed_official 30:91c1d09ada54 23 * - No flash accesses will go to ram, as there will be nothing there
mbed_official 30:91c1d09ada54 24 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
mbed_official 30:91c1d09ada54 25 * - RAM overhead: 0, FLASH overhead: 320 bytes
mbed_official 30:91c1d09ada54 26 *
mbed_official 30:91c1d09ada54 27 * Option 2 is the one to go for, as RAM is the most valuable resource
mbed_official 30:91c1d09ada54 28 */
mbed_official 30:91c1d09ada54 29
mbed_official 30:91c1d09ada54 30 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
mbed_official 30:91c1d09ada54 31
mbed_official 30:91c1d09ada54 32 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
mbed_official 30:91c1d09ada54 33 int i;
mbed_official 30:91c1d09ada54 34 // Space for dynamic vectors, initialised to allocate in R/W
mbed_official 30:91c1d09ada54 35 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
mbed_official 30:91c1d09ada54 36
mbed_official 30:91c1d09ada54 37 // Copy and switch to dynamic vectors if first time called
mbed_official 30:91c1d09ada54 38 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
mbed_official 30:91c1d09ada54 39 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
mbed_official 30:91c1d09ada54 40 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
mbed_official 30:91c1d09ada54 41 vectors[i] = old_vectors[i];
mbed_official 30:91c1d09ada54 42 }
mbed_official 30:91c1d09ada54 43 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
mbed_official 30:91c1d09ada54 44 }
mbed_official 30:91c1d09ada54 45
mbed_official 30:91c1d09ada54 46 // Set the vector
mbed_official 30:91c1d09ada54 47 vectors[IRQn + 16] = vector;
mbed_official 30:91c1d09ada54 48 }
mbed_official 30:91c1d09ada54 49
mbed_official 30:91c1d09ada54 50 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
mbed_official 30:91c1d09ada54 51 // We can always read vectors at 0x0, as the addresses are remapped
mbed_official 30:91c1d09ada54 52 uint32_t *vectors = (uint32_t*)0;
mbed_official 30:91c1d09ada54 53
mbed_official 30:91c1d09ada54 54 // Return the vector
mbed_official 30:91c1d09ada54 55 return vectors[IRQn + 16];
mbed_official 30:91c1d09ada54 56 }
mbed_official 30:91c1d09ada54 57