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mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c@294:78f9587bb26d, 2014-08-21 (annotated)

Committer:
mbed_official
Date:
Thu Aug 21 11:00:08 2014 +0100
Revision:
294:78f9587bb26d
Parent:
256:76fd9a263045
Child:
446:b421ac8a7b41
Synchronized with git revision 5ba8d2a310393df9f8bc08d16bbaec433cdeeba0



Full URL: https://github.com/mbedmicro/mbed/commit/5ba8d2a310393df9f8bc08d16bbaec433cdeeba0/



LPC4330_M4 port_api, us_ticker update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /*
bogdanm 20:4263a77256ae 2 * @brief LPC43xx System Initialization
bogdanm 20:4263a77256ae 3 *
bogdanm 20:4263a77256ae 4 * @note
bogdanm 20:4263a77256ae 5 * Copyright(C) NXP Semiconductors, 2012
bogdanm 20:4263a77256ae 6 * All rights reserved.
bogdanm 20:4263a77256ae 7 *
bogdanm 20:4263a77256ae 8 * @par
bogdanm 20:4263a77256ae 9 * Software that is described herein is for illustrative purposes only
bogdanm 20:4263a77256ae 10 * which provides customers with programming information regarding the
bogdanm 20:4263a77256ae 11 * LPC products. This software is supplied "AS IS" without any warranties of
bogdanm 20:4263a77256ae 12 * any kind, and NXP Semiconductors and its licensor disclaim any and
bogdanm 20:4263a77256ae 13 * all warranties, express or implied, including all implied warranties of
bogdanm 20:4263a77256ae 14 * merchantability, fitness for a particular purpose and non-infringement of
bogdanm 20:4263a77256ae 15 * intellectual property rights. NXP Semiconductors assumes no responsibility
bogdanm 20:4263a77256ae 16 * or liability for the use of the software, conveys no license or rights under any
bogdanm 20:4263a77256ae 17 * patent, copyright, mask work right, or any other intellectual property rights in
bogdanm 20:4263a77256ae 18 * or to any products. NXP Semiconductors reserves the right to make changes
bogdanm 20:4263a77256ae 19 * in the software without notification. NXP Semiconductors also makes no
bogdanm 20:4263a77256ae 20 * representation or warranty that such application will be suitable for the
bogdanm 20:4263a77256ae 21 * specified use without further testing or modification.
bogdanm 20:4263a77256ae 22 *
bogdanm 20:4263a77256ae 23 * @par
bogdanm 20:4263a77256ae 24 * Permission to use, copy, modify, and distribute this software and its
bogdanm 20:4263a77256ae 25 * documentation is hereby granted, under NXP Semiconductors' and its
bogdanm 20:4263a77256ae 26 * licensor's relevant copyrights in the software, without fee, provided that it
bogdanm 20:4263a77256ae 27 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 20:4263a77256ae 28 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 20:4263a77256ae 29 * this code.
bogdanm 20:4263a77256ae 30 *
bogdanm 20:4263a77256ae 31 * Modified by Micromint USA <support@micromint.com>
bogdanm 20:4263a77256ae 32 */
bogdanm 20:4263a77256ae 33 #include "LPC43xx.h"
bogdanm 20:4263a77256ae 34
bogdanm 20:4263a77256ae 35 #define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
bogdanm 20:4263a77256ae 36
bogdanm 20:4263a77256ae 37 /* Clock variables */
mbed_official 256:76fd9a263045 38 #if (CLOCK_SETUP)
mbed_official 256:76fd9a263045 39 uint32_t SystemCoreClock = MAX_CLOCK_FREQ;
mbed_official 256:76fd9a263045 40 #else
mbed_official 256:76fd9a263045 41 uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN;
mbed_official 256:76fd9a263045 42 #endif
bogdanm 20:4263a77256ae 43
bogdanm 20:4263a77256ae 44 #if !defined(CORE_M0)
bogdanm 20:4263a77256ae 45 /* SCU pin definitions for pin muxing */
bogdanm 20:4263a77256ae 46 typedef struct {
bogdanm 20:4263a77256ae 47 __IO uint32_t *reg; /* SCU register address */
bogdanm 20:4263a77256ae 48 uint16_t mode; /* SCU pin mode and function */
bogdanm 20:4263a77256ae 49 } PINMUX_GRP_T;
bogdanm 20:4263a77256ae 50
mbed_official 256:76fd9a263045 51 /* Pins to initialize before clocks are configured */
mbed_official 256:76fd9a263045 52 static const PINMUX_GRP_T pre_clock_mux[] = {
mbed_official 256:76fd9a263045 53 /* SPIFI pins */
mbed_official 256:76fd9a263045 54 {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
mbed_official 256:76fd9a263045 55 {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
mbed_official 256:76fd9a263045 56 {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
mbed_official 256:76fd9a263045 57 {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
mbed_official 256:76fd9a263045 58 {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
mbed_official 256:76fd9a263045 59 {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
mbed_official 256:76fd9a263045 60 };
mbed_official 256:76fd9a263045 61
mbed_official 256:76fd9a263045 62 /* Pins to initialize after clocks are configured */
mbed_official 256:76fd9a263045 63 static const PINMUX_GRP_T post_clock_mux[] = {
mbed_official 256:76fd9a263045 64 /* Boot pins */
mbed_official 256:76fd9a263045 65 {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
mbed_official 256:76fd9a263045 66 {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
mbed_official 256:76fd9a263045 67 {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
mbed_official 256:76fd9a263045 68 {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
mbed_official 256:76fd9a263045 69 /* Micromint Bambino 200/210 */
mbed_official 256:76fd9a263045 70 {SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
mbed_official 256:76fd9a263045 71 {SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
mbed_official 256:76fd9a263045 72 {SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
mbed_official 256:76fd9a263045 73 /* Micromint Bambino 210 */
mbed_official 256:76fd9a263045 74 {SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
mbed_official 256:76fd9a263045 75 {SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
mbed_official 256:76fd9a263045 76 };
mbed_official 256:76fd9a263045 77
mbed_official 256:76fd9a263045 78 #if (CLOCK_SETUP)
mbed_official 256:76fd9a263045 79 /* Structure for initial base clock states */
mbed_official 256:76fd9a263045 80 struct CLK_BASE_STATES {
mbed_official 256:76fd9a263045 81 CGU_BASE_CLK_T clk; /* Base clock */
mbed_official 256:76fd9a263045 82 CGU_CLKIN_T clkin; /* Base clock source */
mbed_official 256:76fd9a263045 83 uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
mbed_official 256:76fd9a263045 84 };
mbed_official 256:76fd9a263045 85
mbed_official 256:76fd9a263045 86 /* Initial base clock states are mostly on */
mbed_official 256:76fd9a263045 87 static const struct CLK_BASE_STATES clock_states[] = {
mbed_official 256:76fd9a263045 88 {CLK_BASE_SAFE, CLKIN_IRC, 0},
mbed_official 256:76fd9a263045 89 {CLK_BASE_APB1, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 90 {CLK_BASE_APB3, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 91 {CLK_BASE_USB0, CLKIN_USBPLL, 1},
mbed_official 256:76fd9a263045 92 {CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 93 {CLK_BASE_SPI, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 94 {CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
mbed_official 256:76fd9a263045 95 #if defined(USE_RMII)
mbed_official 256:76fd9a263045 96 {CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
mbed_official 256:76fd9a263045 97 #else
mbed_official 256:76fd9a263045 98 {CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
mbed_official 256:76fd9a263045 99 #endif
mbed_official 256:76fd9a263045 100 {CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
mbed_official 294:78f9587bb26d 101 {CLK_BASE_SSP0, CLKIN_IDIVC, 0},
mbed_official 294:78f9587bb26d 102 {CLK_BASE_SSP1, CLKIN_IDIVC, 0},
mbed_official 256:76fd9a263045 103 {CLK_BASE_UART0, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 104 {CLK_BASE_UART1, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 105 {CLK_BASE_UART2, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 106 {CLK_BASE_UART3, CLKIN_MAINPLL, 0},
mbed_official 256:76fd9a263045 107 {CLK_BASE_OUT, CLKINPUT_PD, 0},
mbed_official 256:76fd9a263045 108 {CLK_BASE_APLL, CLKINPUT_PD, 0},
mbed_official 256:76fd9a263045 109 {CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
mbed_official 256:76fd9a263045 110 {CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
mbed_official 256:76fd9a263045 111
mbed_official 256:76fd9a263045 112 /* Clocks derived from dividers */
mbed_official 256:76fd9a263045 113 {CLK_BASE_LCD, CLKIN_IDIVC, 0},
mbed_official 256:76fd9a263045 114 {CLK_BASE_USB1, CLKIN_IDIVD, 1}
mbed_official 256:76fd9a263045 115 };
mbed_official 256:76fd9a263045 116 #endif /* defined(CLOCK_SETUP) */
mbed_official 256:76fd9a263045 117
bogdanm 20:4263a77256ae 118 /* Local functions */
mbed_official 256:76fd9a263045 119 static uint32_t SystemGetMainPLLHz(void);
bogdanm 20:4263a77256ae 120 static void SystemSetupClock(void);
bogdanm 20:4263a77256ae 121 static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
bogdanm 20:4263a77256ae 122 static void SystemSetupMemory(void);
bogdanm 20:4263a77256ae 123 static void WaitUs(uint32_t us);
bogdanm 20:4263a77256ae 124
bogdanm 20:4263a77256ae 125 #endif /* !defined(CORE_M0) */
bogdanm 20:4263a77256ae 126
bogdanm 20:4263a77256ae 127 /*
bogdanm 20:4263a77256ae 128 * SystemInit() - Initialize the system
bogdanm 20:4263a77256ae 129 */
bogdanm 20:4263a77256ae 130 void SystemInit(void)
bogdanm 20:4263a77256ae 131 {
bogdanm 20:4263a77256ae 132 #if !defined(CORE_M0)
bogdanm 20:4263a77256ae 133
mbed_official 256:76fd9a263045 134 /* Initialize vector table in flash */
bogdanm 20:4263a77256ae 135 #if defined(__ARMCC_VERSION)
bogdanm 20:4263a77256ae 136 extern void *__Vectors;
bogdanm 20:4263a77256ae 137
mbed_official 256:76fd9a263045 138 SCB->VTOR = (unsigned int) &__Vectors;
bogdanm 20:4263a77256ae 139 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 20:4263a77256ae 140 extern void *__vector_table;
bogdanm 20:4263a77256ae 141
mbed_official 256:76fd9a263045 142 SCB->VTOR = (unsigned int) &__vector_table;
mbed_official 47:02833c62d054 143 #elif defined(TOOLCHAIN_GCC_ARM)
mbed_official 47:02833c62d054 144 extern void *__isr_vector;
mbed_official 47:02833c62d054 145
mbed_official 256:76fd9a263045 146 SCB->VTOR = (unsigned int) &__isr_vector;
bogdanm 20:4263a77256ae 147 #else /* defined(__GNUC__) and others */
bogdanm 20:4263a77256ae 148 extern void *g_pfnVectors;
bogdanm 20:4263a77256ae 149
mbed_official 256:76fd9a263045 150 SCB->VTOR = (unsigned int) &g_pfnVectors;
bogdanm 20:4263a77256ae 151 #endif
bogdanm 20:4263a77256ae 152
mbed_official 256:76fd9a263045 153 #if !defined(TOOLCHAIN_GCC)
bogdanm 20:4263a77256ae 154 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
bogdanm 20:4263a77256ae 155 /* Initialize floating point */
bogdanm 20:4263a77256ae 156 fpuInit();
bogdanm 20:4263a77256ae 157 #endif
mbed_official 256:76fd9a263045 158 #endif
bogdanm 20:4263a77256ae 159
bogdanm 20:4263a77256ae 160 SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
bogdanm 20:4263a77256ae 161 SystemSetupClock(); /* Configure processor and peripheral clocks */
bogdanm 20:4263a77256ae 162 SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
bogdanm 20:4263a77256ae 163 SystemSetupMemory(); /* Configure external memory */
bogdanm 20:4263a77256ae 164 #endif /* !defined(CORE_M0) */
bogdanm 20:4263a77256ae 165
bogdanm 20:4263a77256ae 166 SystemCoreClockUpdate(); /* Update SystemCoreClock variable */
bogdanm 20:4263a77256ae 167 }
bogdanm 20:4263a77256ae 168
bogdanm 20:4263a77256ae 169 /*
bogdanm 20:4263a77256ae 170 * SystemCoreClockUpdate() - Update SystemCoreClock variable
bogdanm 20:4263a77256ae 171 */
bogdanm 20:4263a77256ae 172 void SystemCoreClockUpdate(void)
bogdanm 20:4263a77256ae 173 {
mbed_official 256:76fd9a263045 174 uint32_t reg, div, rate;
mbed_official 256:76fd9a263045 175
mbed_official 256:76fd9a263045 176 /* Get main PLL rate */
mbed_official 256:76fd9a263045 177 rate = SystemGetMainPLLHz();
mbed_official 256:76fd9a263045 178
mbed_official 256:76fd9a263045 179 /* Get clock divider */
mbed_official 256:76fd9a263045 180 reg = LPC_CCU1->CLKCCU[CLK_MX_MXCORE].CFG;
mbed_official 256:76fd9a263045 181 if (((reg >> 5) & 0x7) == 0) {
mbed_official 256:76fd9a263045 182 div = 1;
mbed_official 256:76fd9a263045 183 }
mbed_official 256:76fd9a263045 184 else {
mbed_official 256:76fd9a263045 185 div = 2;
mbed_official 256:76fd9a263045 186 }
mbed_official 256:76fd9a263045 187 rate = rate / div;
mbed_official 256:76fd9a263045 188
mbed_official 256:76fd9a263045 189 SystemCoreClock = rate;
mbed_official 256:76fd9a263045 190 }
mbed_official 256:76fd9a263045 191
mbed_official 256:76fd9a263045 192 /* Returns the frequency of the main PLL */
mbed_official 256:76fd9a263045 193 uint32_t SystemGetMainPLLHz(void)
mbed_official 256:76fd9a263045 194 {
mbed_official 256:76fd9a263045 195 uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
mbed_official 256:76fd9a263045 196 uint32_t freq = CRYSTAL_MAIN_FREQ_IN;
mbed_official 256:76fd9a263045 197 uint32_t msel, nsel, psel, direct, fbsel;
mbed_official 256:76fd9a263045 198 uint32_t m, n, p;
mbed_official 256:76fd9a263045 199 const uint8_t ptab[] = {1, 2, 4, 8};
mbed_official 256:76fd9a263045 200
mbed_official 256:76fd9a263045 201 msel = (PLLReg >> 16) & 0xFF;
mbed_official 256:76fd9a263045 202 nsel = (PLLReg >> 12) & 0x3;
mbed_official 256:76fd9a263045 203 psel = (PLLReg >> 8) & 0x3;
mbed_official 256:76fd9a263045 204 direct = (PLLReg >> 7) & 0x1;
mbed_official 256:76fd9a263045 205 fbsel = (PLLReg >> 6) & 0x1;
mbed_official 256:76fd9a263045 206
mbed_official 256:76fd9a263045 207 m = msel + 1;
mbed_official 256:76fd9a263045 208 n = nsel + 1;
mbed_official 256:76fd9a263045 209 p = ptab[psel];
mbed_official 256:76fd9a263045 210
mbed_official 256:76fd9a263045 211 if (direct || fbsel) {
mbed_official 256:76fd9a263045 212 return m * (freq / n);
mbed_official 256:76fd9a263045 213 }
mbed_official 256:76fd9a263045 214
mbed_official 256:76fd9a263045 215 return (m / (2 * p)) * (freq / n);
bogdanm 20:4263a77256ae 216 }
bogdanm 20:4263a77256ae 217
bogdanm 20:4263a77256ae 218 #if !defined(CORE_M0)
bogdanm 20:4263a77256ae 219 /*
bogdanm 20:4263a77256ae 220 * SystemSetupClock() - Set processor and peripheral clocks
mbed_official 256:76fd9a263045 221 *
mbed_official 256:76fd9a263045 222 * Clock Frequency Source
mbed_official 256:76fd9a263045 223 * CLK_BASE_MX 204 MHz CLKIN_MAINPLL (CLKIN_PLL1)
mbed_official 256:76fd9a263045 224 * CLK_BASE_SPIFI 102 MHz CLKIN_IDIVE
mbed_official 256:76fd9a263045 225 * CLK_BASE_USB0 480 MHz CLKIN_USBPLL (Disabled) (CLKIN_PLL0USB)
mbed_official 256:76fd9a263045 226 * CLK_BASE_USB1 60 MHz CLKIN_IDIVE (Disabled)
mbed_official 256:76fd9a263045 227 * 120 MHz CLKIN_IDIVD (Disabled)
mbed_official 256:76fd9a263045 228 *
mbed_official 256:76fd9a263045 229 * 12 MHz CLKIN_IDIVB
mbed_official 256:76fd9a263045 230 * 12 MHz CLKIN_IDIVC
mbed_official 256:76fd9a263045 231 *
bogdanm 20:4263a77256ae 232 */
bogdanm 20:4263a77256ae 233 void SystemSetupClock(void)
bogdanm 20:4263a77256ae 234 {
bogdanm 20:4263a77256ae 235 #if (CLOCK_SETUP)
mbed_official 256:76fd9a263045 236 uint32_t i;
mbed_official 256:76fd9a263045 237
mbed_official 256:76fd9a263045 238 /* Switch main clock to Internal RC (IRC) while setting up PLL1 */
mbed_official 256:76fd9a263045 239 LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
mbed_official 294:78f9587bb26d 240 /* Set prescaler/divider on SSP1 assuming 204 MHz clock */
mbed_official 294:78f9587bb26d 241 LPC_SSP1->CR1 &= ~(1 << 1);
mbed_official 294:78f9587bb26d 242 LPC_SSP1->CPSR = 0x0002;
mbed_official 294:78f9587bb26d 243 LPC_SSP1->CR0 = 0x00006507;
mbed_official 294:78f9587bb26d 244 LPC_SSP1->CR1 |= (1 << 1);
bogdanm 20:4263a77256ae 245
bogdanm 20:4263a77256ae 246 /* Enable the oscillator and wait 100 us */
bogdanm 20:4263a77256ae 247 LPC_CGU->XTAL_OSC_CTRL = 0;
bogdanm 20:4263a77256ae 248 WaitUs(100);
bogdanm 20:4263a77256ae 249
bogdanm 20:4263a77256ae 250 #if (SPIFI_INIT)
mbed_official 256:76fd9a263045 251 /* Setup SPIFI control register and no-opcode mode */
mbed_official 256:76fd9a263045 252 LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
mbed_official 256:76fd9a263045 253 LPC_SPIFI->IDATA = 0xA5;
mbed_official 256:76fd9a263045 254 /* Switch IDIVE clock to IRC and connect to SPIFI clock */
mbed_official 256:76fd9a263045 255 LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
mbed_official 256:76fd9a263045 256 LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
bogdanm 20:4263a77256ae 257 #endif /* SPIFI_INIT */
bogdanm 20:4263a77256ae 258
mbed_official 256:76fd9a263045 259 /* Configure PLL1 (MAINPLL) for main clock */
mbed_official 256:76fd9a263045 260 LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
bogdanm 20:4263a77256ae 261
bogdanm 20:4263a77256ae 262 /* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
mbed_official 256:76fd9a263045 263 LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
mbed_official 256:76fd9a263045 264 | (CLKIN_MAINPLL << 24);
bogdanm 20:4263a77256ae 265 while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
bogdanm 20:4263a77256ae 266 WaitUs(100);
bogdanm 20:4263a77256ae 267
bogdanm 20:4263a77256ae 268 /* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
mbed_official 256:76fd9a263045 269 LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
mbed_official 256:76fd9a263045 270 | (CLKIN_MAINPLL << 24);
bogdanm 20:4263a77256ae 271 while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
bogdanm 20:4263a77256ae 272
mbed_official 256:76fd9a263045 273 /* Connect main clock to PLL1 */
mbed_official 256:76fd9a263045 274 LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
mbed_official 256:76fd9a263045 275
mbed_official 256:76fd9a263045 276 /* Set USB PLL dividers for 480 MHz (for USB0) */
mbed_official 256:76fd9a263045 277 LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
mbed_official 256:76fd9a263045 278 LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
mbed_official 256:76fd9a263045 279 LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL = 0x0000081D | (CLKIN_CRYSTAL << 24);
mbed_official 256:76fd9a263045 280
mbed_official 256:76fd9a263045 281 /* Set IDIVE clock to PLL1/2 = 102 MHz */
mbed_official 256:76fd9a263045 282 LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
mbed_official 256:76fd9a263045 283
mbed_official 256:76fd9a263045 284 /* Set IDIVD clock to ((USBPLL/4) / 2) = 60 MHz (for USB1) */
mbed_official 256:76fd9a263045 285 LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = (3 << 2) | (1 << 11) | (CLKIN_USBPLL << 24); /* USBPLL/4 */
mbed_official 256:76fd9a263045 286 LPC_CGU->IDIV_CTRL[CLK_IDIV_D] = (1 << 2) | (1 << 11) | (CLKIN_IDIVA << 24); /* IDIVA/2 */
mbed_official 256:76fd9a263045 287
mbed_official 256:76fd9a263045 288 /* Configure remaining integer dividers */
mbed_official 256:76fd9a263045 289 LPC_CGU->IDIV_CTRL[CLK_IDIV_B] = (0 << 2) | (1 << 11) | (CLKIN_IRC << 24); /* IRC */
mbed_official 256:76fd9a263045 290 LPC_CGU->IDIV_CTRL[CLK_IDIV_C] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
mbed_official 256:76fd9a263045 291
mbed_official 256:76fd9a263045 292 /* Connect base clocks */
mbed_official 256:76fd9a263045 293 for (i = 0; i < COUNT_OF(clock_states); i++) {
mbed_official 256:76fd9a263045 294 LPC_CGU->BASE_CLK[clock_states[i].clk] =
mbed_official 256:76fd9a263045 295 ( clock_states[i].powerdn << 0)
mbed_official 256:76fd9a263045 296 | (1 << 11) | (clock_states[i].clkin << 24);
mbed_official 256:76fd9a263045 297 }
bogdanm 20:4263a77256ae 298 #endif /* CLOCK_SETUP */
mbed_official 294:78f9587bb26d 299 /* Reset peripherals */
mbed_official 294:78f9587bb26d 300 LPC_RGU->RESET_CTRL0 = 0x105F0000;
mbed_official 294:78f9587bb26d 301 LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
bogdanm 20:4263a77256ae 302 }
bogdanm 20:4263a77256ae 303
bogdanm 20:4263a77256ae 304 /*
bogdanm 20:4263a77256ae 305 * SystemSetupPins() - Configure MCU pins
bogdanm 20:4263a77256ae 306 */
bogdanm 20:4263a77256ae 307 void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
bogdanm 20:4263a77256ae 308 {
mbed_official 256:76fd9a263045 309 uint32_t i;
bogdanm 20:4263a77256ae 310
bogdanm 20:4263a77256ae 311 for (i = 0; i < n; i++) {
bogdanm 20:4263a77256ae 312 *(mux[i].reg) = mux[i].mode;
bogdanm 20:4263a77256ae 313 }
bogdanm 20:4263a77256ae 314 }
bogdanm 20:4263a77256ae 315
bogdanm 20:4263a77256ae 316 /*
bogdanm 20:4263a77256ae 317 * SystemSetupMemory() - Configure external memory
bogdanm 20:4263a77256ae 318 */
bogdanm 20:4263a77256ae 319 void SystemSetupMemory(void)
bogdanm 20:4263a77256ae 320 {
bogdanm 20:4263a77256ae 321 #if (MEMORY_SETUP)
bogdanm 20:4263a77256ae 322 /* None required for boards without external memory */
bogdanm 20:4263a77256ae 323 #endif /* MEMORY_SETUP */
bogdanm 20:4263a77256ae 324 }
bogdanm 20:4263a77256ae 325
bogdanm 20:4263a77256ae 326 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
bogdanm 20:4263a77256ae 327 /*
bogdanm 20:4263a77256ae 328 * fpuInit() - Early initialization of the FPU
bogdanm 20:4263a77256ae 329 */
bogdanm 20:4263a77256ae 330 void fpuInit(void)
bogdanm 20:4263a77256ae 331 {
mbed_official 256:76fd9a263045 332 /*
mbed_official 256:76fd9a263045 333 * from ARM TRM manual:
mbed_official 256:76fd9a263045 334 * ; CPACR is located at address 0xE000ED88
mbed_official 256:76fd9a263045 335 * LDR.W R0, =0xE000ED88
mbed_official 256:76fd9a263045 336 * ; Read CPACR
mbed_official 256:76fd9a263045 337 * LDR R1, [R0]
mbed_official 256:76fd9a263045 338 * ; Set bits 20-23 to enable CP10 and CP11 coprocessors
mbed_official 256:76fd9a263045 339 * ORR R1, R1, #(0xF << 20)
mbed_official 256:76fd9a263045 340 * ; Write back the modified value to the CPACR
mbed_official 256:76fd9a263045 341 * STR R1, [R0]
mbed_official 256:76fd9a263045 342 */
bogdanm 20:4263a77256ae 343
mbed_official 256:76fd9a263045 344 volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
mbed_official 256:76fd9a263045 345 volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
mbed_official 256:76fd9a263045 346 volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
mbed_official 256:76fd9a263045 347 volatile uint32_t Cpacr;
mbed_official 256:76fd9a263045 348 volatile uint32_t Mvfr0;
mbed_official 256:76fd9a263045 349 volatile uint32_t Mvfr1;
mbed_official 256:76fd9a263045 350 char vfpPresent = 0;
bogdanm 20:4263a77256ae 351
mbed_official 256:76fd9a263045 352 Mvfr0 = *regMvfr0;
mbed_official 256:76fd9a263045 353 Mvfr1 = *regMvfr1;
bogdanm 20:4263a77256ae 354
mbed_official 256:76fd9a263045 355 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
bogdanm 20:4263a77256ae 356
mbed_official 256:76fd9a263045 357 if (vfpPresent) {
mbed_official 256:76fd9a263045 358 Cpacr = *regCpacr;
mbed_official 256:76fd9a263045 359 Cpacr |= (0xF << 20);
mbed_official 256:76fd9a263045 360 *regCpacr = Cpacr; /* enable CP10 and CP11 for full access */
mbed_official 256:76fd9a263045 361 }
bogdanm 20:4263a77256ae 362 }
bogdanm 20:4263a77256ae 363 #endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */
bogdanm 20:4263a77256ae 364
bogdanm 20:4263a77256ae 365 /* Approximate delay function */
bogdanm 20:4263a77256ae 366 #define CPU_NANOSEC(x) (((uint64_t) (x) * SystemCoreClock) / 1000000000)
bogdanm 20:4263a77256ae 367
bogdanm 20:4263a77256ae 368 static void WaitUs(uint32_t us)
bogdanm 20:4263a77256ae 369 {
bogdanm 20:4263a77256ae 370 uint32_t cyc = us * CPU_NANOSEC(1000) / 4;
bogdanm 20:4263a77256ae 371 while (cyc--)
bogdanm 20:4263a77256ae 372 ;
bogdanm 20:4263a77256ae 373 }
bogdanm 20:4263a77256ae 374
bogdanm 20:4263a77256ae 375 #endif /* !defined(CORE_M0) */