mbed library sources

Fork of mbed-src by mbed official

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Child:
17:151ab7482c89
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 13:0645d8841f51 1 /******************************************************************************
bogdanm 13:0645d8841f51 2 * @file system_LPC13Uxx.c
bogdanm 13:0645d8841f51 3 * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
bogdanm 13:0645d8841f51 4 * for the NXP LPC13xx Device Series
bogdanm 13:0645d8841f51 5 * @version V1.10
bogdanm 13:0645d8841f51 6 * @date 24. November 2010
bogdanm 13:0645d8841f51 7 *
bogdanm 13:0645d8841f51 8 * @note
bogdanm 13:0645d8841f51 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
bogdanm 13:0645d8841f51 10 *
bogdanm 13:0645d8841f51 11 * @par
bogdanm 13:0645d8841f51 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 13:0645d8841f51 13 * processor based microcontrollers. This file can be freely distributed
bogdanm 13:0645d8841f51 14 * within development tools that are supporting such ARM based processors.
bogdanm 13:0645d8841f51 15 *
bogdanm 13:0645d8841f51 16 * @par
bogdanm 13:0645d8841f51 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 13:0645d8841f51 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 13:0645d8841f51 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 13:0645d8841f51 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 13:0645d8841f51 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 13:0645d8841f51 22 *
bogdanm 13:0645d8841f51 23 ******************************************************************************/
bogdanm 13:0645d8841f51 24
bogdanm 13:0645d8841f51 25
bogdanm 13:0645d8841f51 26 #include <stdint.h>
bogdanm 13:0645d8841f51 27 #include "LPC13Uxx.h"
bogdanm 13:0645d8841f51 28
bogdanm 13:0645d8841f51 29 /*
bogdanm 13:0645d8841f51 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
bogdanm 13:0645d8841f51 31 */
bogdanm 13:0645d8841f51 32
bogdanm 13:0645d8841f51 33 /*--------------------- Clock Configuration ----------------------------------
bogdanm 13:0645d8841f51 34 //
bogdanm 13:0645d8841f51 35 // <e> Clock Configuration
bogdanm 13:0645d8841f51 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
bogdanm 13:0645d8841f51 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
bogdanm 13:0645d8841f51 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
bogdanm 13:0645d8841f51 39 // <i> directly from XTALIN and XTALOUT pins.
bogdanm 13:0645d8841f51 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
bogdanm 13:0645d8841f51 41 // <i> Determines frequency range for Low-power oscillator.
bogdanm 13:0645d8841f51 42 // <0=> 1 - 20 MHz
bogdanm 13:0645d8841f51 43 // <1=> 15 - 25 MHz
bogdanm 13:0645d8841f51 44 // </h>
bogdanm 13:0645d8841f51 45 //
bogdanm 13:0645d8841f51 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
bogdanm 13:0645d8841f51 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
bogdanm 13:0645d8841f51 48 // <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
bogdanm 13:0645d8841f51 49 // <0-31>
bogdanm 13:0645d8841f51 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
bogdanm 13:0645d8841f51 51 // <0=> Undefined
bogdanm 13:0645d8841f51 52 // <1=> 0.5 MHz
bogdanm 13:0645d8841f51 53 // <2=> 0.8 MHz
bogdanm 13:0645d8841f51 54 // <3=> 1.1 MHz
bogdanm 13:0645d8841f51 55 // <4=> 1.4 MHz
bogdanm 13:0645d8841f51 56 // <5=> 1.6 MHz
bogdanm 13:0645d8841f51 57 // <6=> 1.8 MHz
bogdanm 13:0645d8841f51 58 // <7=> 2.0 MHz
bogdanm 13:0645d8841f51 59 // <8=> 2.2 MHz
bogdanm 13:0645d8841f51 60 // <9=> 2.4 MHz
bogdanm 13:0645d8841f51 61 // <10=> 2.6 MHz
bogdanm 13:0645d8841f51 62 // <11=> 2.7 MHz
bogdanm 13:0645d8841f51 63 // <12=> 2.9 MHz
bogdanm 13:0645d8841f51 64 // <13=> 3.1 MHz
bogdanm 13:0645d8841f51 65 // <14=> 3.2 MHz
bogdanm 13:0645d8841f51 66 // <15=> 3.4 MHz
bogdanm 13:0645d8841f51 67 // </h>
bogdanm 13:0645d8841f51 68 //
bogdanm 13:0645d8841f51 69 // <h> System PLL Control Register (SYSPLLCTRL)
bogdanm 13:0645d8841f51 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 13:0645d8841f51 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 13:0645d8841f51 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 13:0645d8841f51 73 // <o3.0..4> MSEL: Feedback Divider Selection
bogdanm 13:0645d8841f51 74 // <i> M = MSEL + 1
bogdanm 13:0645d8841f51 75 // <0-31>
bogdanm 13:0645d8841f51 76 // <o3.5..6> PSEL: Post Divider Selection
bogdanm 13:0645d8841f51 77 // <0=> P = 1
bogdanm 13:0645d8841f51 78 // <1=> P = 2
bogdanm 13:0645d8841f51 79 // <2=> P = 4
bogdanm 13:0645d8841f51 80 // <3=> P = 8
bogdanm 13:0645d8841f51 81 // </h>
bogdanm 13:0645d8841f51 82 //
bogdanm 13:0645d8841f51 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
bogdanm 13:0645d8841f51 84 // <o4.0..1> SEL: System PLL Clock Source
bogdanm 13:0645d8841f51 85 // <0=> IRC Oscillator
bogdanm 13:0645d8841f51 86 // <1=> System Oscillator
bogdanm 13:0645d8841f51 87 // <2=> Reserved
bogdanm 13:0645d8841f51 88 // <3=> Reserved
bogdanm 13:0645d8841f51 89 // </h>
bogdanm 13:0645d8841f51 90 //
bogdanm 13:0645d8841f51 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
bogdanm 13:0645d8841f51 92 // <o5.0..1> SEL: Clock Source for Main Clock
bogdanm 13:0645d8841f51 93 // <0=> IRC Oscillator
bogdanm 13:0645d8841f51 94 // <1=> Input Clock to System PLL
bogdanm 13:0645d8841f51 95 // <2=> WDT Oscillator
bogdanm 13:0645d8841f51 96 // <3=> System PLL Clock Out
bogdanm 13:0645d8841f51 97 // </h>
bogdanm 13:0645d8841f51 98 //
bogdanm 13:0645d8841f51 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
bogdanm 13:0645d8841f51 100 // <o6.0..7> DIV: System AHB Clock Divider
bogdanm 13:0645d8841f51 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
bogdanm 13:0645d8841f51 102 // <i> 0 = is disabled
bogdanm 13:0645d8841f51 103 // <0-255>
bogdanm 13:0645d8841f51 104 // </h>
bogdanm 13:0645d8841f51 105 //
bogdanm 13:0645d8841f51 106 // <h> USB PLL Control Register (USBPLLCTRL)
bogdanm 13:0645d8841f51 107 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
bogdanm 13:0645d8841f51 108 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
bogdanm 13:0645d8841f51 109 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
bogdanm 13:0645d8841f51 110 // <o7.0..4> MSEL: Feedback Divider Selection
bogdanm 13:0645d8841f51 111 // <i> M = MSEL + 1
bogdanm 13:0645d8841f51 112 // <0-31>
bogdanm 13:0645d8841f51 113 // <o7.5..6> PSEL: Post Divider Selection
bogdanm 13:0645d8841f51 114 // <0=> P = 1
bogdanm 13:0645d8841f51 115 // <1=> P = 2
bogdanm 13:0645d8841f51 116 // <2=> P = 4
bogdanm 13:0645d8841f51 117 // <3=> P = 8
bogdanm 13:0645d8841f51 118 // </h>
bogdanm 13:0645d8841f51 119 //
bogdanm 13:0645d8841f51 120 // <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
bogdanm 13:0645d8841f51 121 // <o8.0..1> SEL: USB PLL Clock Source
bogdanm 13:0645d8841f51 122 // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
bogdanm 13:0645d8841f51 123 // <0=> IRC Oscillator
bogdanm 13:0645d8841f51 124 // <1=> System Oscillator
bogdanm 13:0645d8841f51 125 // <2=> Reserved
bogdanm 13:0645d8841f51 126 // <3=> Reserved
bogdanm 13:0645d8841f51 127 // </h>
bogdanm 13:0645d8841f51 128 //
bogdanm 13:0645d8841f51 129 // <h> USB Clock Source Select Register (USBCLKSEL)
bogdanm 13:0645d8841f51 130 // <o9.0..1> SEL: System PLL Clock Source
bogdanm 13:0645d8841f51 131 // <0=> USB PLL out
bogdanm 13:0645d8841f51 132 // <1=> Main clock
bogdanm 13:0645d8841f51 133 // <2=> Reserved
bogdanm 13:0645d8841f51 134 // <3=> Reserved
bogdanm 13:0645d8841f51 135 // </h>
bogdanm 13:0645d8841f51 136 //
bogdanm 13:0645d8841f51 137 // <h> USB Clock Divider Register (USBCLKDIV)
bogdanm 13:0645d8841f51 138 // <o10.0..7> DIV: USB Clock Divider
bogdanm 13:0645d8841f51 139 // <i> Divides USB clock to 48 MHz.
bogdanm 13:0645d8841f51 140 // <i> 0 = is disabled
bogdanm 13:0645d8841f51 141 // <0-255>
bogdanm 13:0645d8841f51 142 // </h>
bogdanm 13:0645d8841f51 143 // </e>
bogdanm 13:0645d8841f51 144 */
bogdanm 13:0645d8841f51 145 #define CLOCK_SETUP 1
bogdanm 13:0645d8841f51 146 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 13:0645d8841f51 147 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
bogdanm 13:0645d8841f51 148 #define SYSPLLCTRL_Val 0x00000025 // Reset: 0x000
bogdanm 13:0645d8841f51 149 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 13:0645d8841f51 150 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
bogdanm 13:0645d8841f51 151 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 13:0645d8841f51 152 #define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
bogdanm 13:0645d8841f51 153 #define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
bogdanm 13:0645d8841f51 154 #define USBCLKSEL_Val 0x00000000 // Reset: 0x000
bogdanm 13:0645d8841f51 155 #define USBCLKDIV_Val 0x00000001 // Reset: 0x001
bogdanm 13:0645d8841f51 156
bogdanm 13:0645d8841f51 157 /*
bogdanm 13:0645d8841f51 158 //-------- <<< end of configuration section >>> ------------------------------
bogdanm 13:0645d8841f51 159 */
bogdanm 13:0645d8841f51 160
bogdanm 13:0645d8841f51 161 /*----------------------------------------------------------------------------
bogdanm 13:0645d8841f51 162 Check the register settings
bogdanm 13:0645d8841f51 163 *----------------------------------------------------------------------------*/
bogdanm 13:0645d8841f51 164 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
bogdanm 13:0645d8841f51 165 #define CHECK_RSVD(val, mask) (val & mask)
bogdanm 13:0645d8841f51 166
bogdanm 13:0645d8841f51 167 /* Clock Configuration -------------------------------------------------------*/
bogdanm 13:0645d8841f51 168 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
bogdanm 13:0645d8841f51 169 #error "SYSOSCCTRL: Invalid values of reserved bits!"
bogdanm 13:0645d8841f51 170 #endif
bogdanm 13:0645d8841f51 171
bogdanm 13:0645d8841f51 172 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
bogdanm 13:0645d8841f51 173 #error "WDTOSCCTRL: Invalid values of reserved bits!"
bogdanm 13:0645d8841f51 174 #endif
bogdanm 13:0645d8841f51 175
bogdanm 13:0645d8841f51 176 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
bogdanm 13:0645d8841f51 177 #error "SYSPLLCLKSEL: Value out of range!"
bogdanm 13:0645d8841f51 178 #endif
bogdanm 13:0645d8841f51 179
bogdanm 13:0645d8841f51 180 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
bogdanm 13:0645d8841f51 181 #error "SYSPLLCTRL: Invalid values of reserved bits!"
bogdanm 13:0645d8841f51 182 #endif
bogdanm 13:0645d8841f51 183
bogdanm 13:0645d8841f51 184 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
bogdanm 13:0645d8841f51 185 #error "MAINCLKSEL: Invalid values of reserved bits!"
bogdanm 13:0645d8841f51 186 #endif
bogdanm 13:0645d8841f51 187
bogdanm 13:0645d8841f51 188 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
bogdanm 13:0645d8841f51 189 #error "SYSAHBCLKDIV: Value out of range!"
bogdanm 13:0645d8841f51 190 #endif
bogdanm 13:0645d8841f51 191
bogdanm 13:0645d8841f51 192 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
bogdanm 13:0645d8841f51 193 #error "USBPLLCLKSEL: Value out of range!"
bogdanm 13:0645d8841f51 194 #endif
bogdanm 13:0645d8841f51 195
bogdanm 13:0645d8841f51 196 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
bogdanm 13:0645d8841f51 197 #error "USBPLLCTRL: Invalid values of reserved bits!"
bogdanm 13:0645d8841f51 198 #endif
bogdanm 13:0645d8841f51 199
bogdanm 13:0645d8841f51 200 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
bogdanm 13:0645d8841f51 201 #error "USBCLKSEL: Value out of range!"
bogdanm 13:0645d8841f51 202 #endif
bogdanm 13:0645d8841f51 203
bogdanm 13:0645d8841f51 204 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
bogdanm 13:0645d8841f51 205 #error "USBCLKDIV: Value out of range!"
bogdanm 13:0645d8841f51 206 #endif
bogdanm 13:0645d8841f51 207
bogdanm 13:0645d8841f51 208
bogdanm 13:0645d8841f51 209 /*----------------------------------------------------------------------------
bogdanm 13:0645d8841f51 210 DEFINES
bogdanm 13:0645d8841f51 211 *----------------------------------------------------------------------------*/
bogdanm 13:0645d8841f51 212
bogdanm 13:0645d8841f51 213 /*----------------------------------------------------------------------------
bogdanm 13:0645d8841f51 214 Define clocks
bogdanm 13:0645d8841f51 215 *----------------------------------------------------------------------------*/
bogdanm 13:0645d8841f51 216 #define __XTAL (12000000UL) /* Oscillator frequency */
bogdanm 13:0645d8841f51 217 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
bogdanm 13:0645d8841f51 218 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
bogdanm 13:0645d8841f51 219
bogdanm 13:0645d8841f51 220
bogdanm 13:0645d8841f51 221 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
bogdanm 13:0645d8841f51 222 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
bogdanm 13:0645d8841f51 223
bogdanm 13:0645d8841f51 224 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 13:0645d8841f51 225 #if (__FREQSEL == 0)
bogdanm 13:0645d8841f51 226 #define __WDT_OSC_CLK ( 0) /* undefined */
bogdanm 13:0645d8841f51 227 #elif (__FREQSEL == 1)
bogdanm 13:0645d8841f51 228 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
bogdanm 13:0645d8841f51 229 #elif (__FREQSEL == 2)
bogdanm 13:0645d8841f51 230 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
bogdanm 13:0645d8841f51 231 #elif (__FREQSEL == 3)
bogdanm 13:0645d8841f51 232 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
bogdanm 13:0645d8841f51 233 #elif (__FREQSEL == 4)
bogdanm 13:0645d8841f51 234 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
bogdanm 13:0645d8841f51 235 #elif (__FREQSEL == 5)
bogdanm 13:0645d8841f51 236 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
bogdanm 13:0645d8841f51 237 #elif (__FREQSEL == 6)
bogdanm 13:0645d8841f51 238 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
bogdanm 13:0645d8841f51 239 #elif (__FREQSEL == 7)
bogdanm 13:0645d8841f51 240 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
bogdanm 13:0645d8841f51 241 #elif (__FREQSEL == 8)
bogdanm 13:0645d8841f51 242 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
bogdanm 13:0645d8841f51 243 #elif (__FREQSEL == 9)
bogdanm 13:0645d8841f51 244 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
bogdanm 13:0645d8841f51 245 #elif (__FREQSEL == 10)
bogdanm 13:0645d8841f51 246 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
bogdanm 13:0645d8841f51 247 #elif (__FREQSEL == 11)
bogdanm 13:0645d8841f51 248 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
bogdanm 13:0645d8841f51 249 #elif (__FREQSEL == 12)
bogdanm 13:0645d8841f51 250 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
bogdanm 13:0645d8841f51 251 #elif (__FREQSEL == 13)
bogdanm 13:0645d8841f51 252 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
bogdanm 13:0645d8841f51 253 #elif (__FREQSEL == 14)
bogdanm 13:0645d8841f51 254 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
bogdanm 13:0645d8841f51 255 #else
bogdanm 13:0645d8841f51 256 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
bogdanm 13:0645d8841f51 257 #endif
bogdanm 13:0645d8841f51 258
bogdanm 13:0645d8841f51 259 /* sys_pllclkin calculation */
bogdanm 13:0645d8841f51 260 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
bogdanm 13:0645d8841f51 261 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
bogdanm 13:0645d8841f51 262 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 13:0645d8841f51 263 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
bogdanm 13:0645d8841f51 264 #else
bogdanm 13:0645d8841f51 265 #define __SYS_PLLCLKIN (0)
bogdanm 13:0645d8841f51 266 #endif
bogdanm 13:0645d8841f51 267
bogdanm 13:0645d8841f51 268 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
bogdanm 13:0645d8841f51 269
bogdanm 13:0645d8841f51 270 /* main clock calculation */
bogdanm 13:0645d8841f51 271 #if ((MAINCLKSEL_Val & 0x03) == 0)
bogdanm 13:0645d8841f51 272 #define __MAIN_CLOCK (__IRC_OSC_CLK)
bogdanm 13:0645d8841f51 273 #elif ((MAINCLKSEL_Val & 0x03) == 1)
bogdanm 13:0645d8841f51 274 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
bogdanm 13:0645d8841f51 275 #elif ((MAINCLKSEL_Val & 0x03) == 2)
bogdanm 13:0645d8841f51 276 #if (__FREQSEL == 0)
bogdanm 13:0645d8841f51 277 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
bogdanm 13:0645d8841f51 278 #else
bogdanm 13:0645d8841f51 279 #define __MAIN_CLOCK (__WDT_OSC_CLK)
bogdanm 13:0645d8841f51 280 #endif
bogdanm 13:0645d8841f51 281 #elif ((MAINCLKSEL_Val & 0x03) == 3)
bogdanm 13:0645d8841f51 282 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
bogdanm 13:0645d8841f51 283 #else
bogdanm 13:0645d8841f51 284 #define __MAIN_CLOCK (0)
bogdanm 13:0645d8841f51 285 #endif
bogdanm 13:0645d8841f51 286
bogdanm 13:0645d8841f51 287 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
bogdanm 13:0645d8841f51 288
bogdanm 13:0645d8841f51 289 #else
bogdanm 13:0645d8841f51 290 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
bogdanm 13:0645d8841f51 291 #endif // CLOCK_SETUP
bogdanm 13:0645d8841f51 292
bogdanm 13:0645d8841f51 293
bogdanm 13:0645d8841f51 294 /*----------------------------------------------------------------------------
bogdanm 13:0645d8841f51 295 Clock Variable definitions
bogdanm 13:0645d8841f51 296 *----------------------------------------------------------------------------*/
bogdanm 13:0645d8841f51 297 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
bogdanm 13:0645d8841f51 298
bogdanm 13:0645d8841f51 299
bogdanm 13:0645d8841f51 300 /*----------------------------------------------------------------------------
bogdanm 13:0645d8841f51 301 Clock functions
bogdanm 13:0645d8841f51 302 *----------------------------------------------------------------------------*/
bogdanm 13:0645d8841f51 303 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
bogdanm 13:0645d8841f51 304 {
bogdanm 13:0645d8841f51 305 uint32_t wdt_osc = 0;
bogdanm 13:0645d8841f51 306
bogdanm 13:0645d8841f51 307 /* Determine clock frequency according to clock register values */
bogdanm 13:0645d8841f51 308 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
bogdanm 13:0645d8841f51 309 case 0: wdt_osc = 0; break;
bogdanm 13:0645d8841f51 310 case 1: wdt_osc = 500000; break;
bogdanm 13:0645d8841f51 311 case 2: wdt_osc = 800000; break;
bogdanm 13:0645d8841f51 312 case 3: wdt_osc = 1100000; break;
bogdanm 13:0645d8841f51 313 case 4: wdt_osc = 1400000; break;
bogdanm 13:0645d8841f51 314 case 5: wdt_osc = 1600000; break;
bogdanm 13:0645d8841f51 315 case 6: wdt_osc = 1800000; break;
bogdanm 13:0645d8841f51 316 case 7: wdt_osc = 2000000; break;
bogdanm 13:0645d8841f51 317 case 8: wdt_osc = 2200000; break;
bogdanm 13:0645d8841f51 318 case 9: wdt_osc = 2400000; break;
bogdanm 13:0645d8841f51 319 case 10: wdt_osc = 2600000; break;
bogdanm 13:0645d8841f51 320 case 11: wdt_osc = 2700000; break;
bogdanm 13:0645d8841f51 321 case 12: wdt_osc = 2900000; break;
bogdanm 13:0645d8841f51 322 case 13: wdt_osc = 3100000; break;
bogdanm 13:0645d8841f51 323 case 14: wdt_osc = 3200000; break;
bogdanm 13:0645d8841f51 324 case 15: wdt_osc = 3400000; break;
bogdanm 13:0645d8841f51 325 }
bogdanm 13:0645d8841f51 326 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
bogdanm 13:0645d8841f51 327
bogdanm 13:0645d8841f51 328 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
bogdanm 13:0645d8841f51 329 case 0: /* Internal RC oscillator */
bogdanm 13:0645d8841f51 330 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 13:0645d8841f51 331 break;
bogdanm 13:0645d8841f51 332 case 1: /* Input Clock to System PLL */
bogdanm 13:0645d8841f51 333 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 13:0645d8841f51 334 case 0: /* Internal RC oscillator */
bogdanm 13:0645d8841f51 335 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 13:0645d8841f51 336 break;
bogdanm 13:0645d8841f51 337 case 1: /* System oscillator */
bogdanm 13:0645d8841f51 338 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 13:0645d8841f51 339 break;
bogdanm 13:0645d8841f51 340 case 2: /* Reserved */
bogdanm 13:0645d8841f51 341 case 3: /* Reserved */
bogdanm 13:0645d8841f51 342 SystemCoreClock = 0;
bogdanm 13:0645d8841f51 343 break;
bogdanm 13:0645d8841f51 344 }
bogdanm 13:0645d8841f51 345 break;
bogdanm 13:0645d8841f51 346 case 2: /* WDT Oscillator */
bogdanm 13:0645d8841f51 347 SystemCoreClock = wdt_osc;
bogdanm 13:0645d8841f51 348 break;
bogdanm 13:0645d8841f51 349 case 3: /* System PLL Clock Out */
bogdanm 13:0645d8841f51 350 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
bogdanm 13:0645d8841f51 351 case 0: /* Internal RC oscillator */
bogdanm 13:0645d8841f51 352 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 13:0645d8841f51 353 SystemCoreClock = __IRC_OSC_CLK;
bogdanm 13:0645d8841f51 354 } else {
bogdanm 13:0645d8841f51 355 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 13:0645d8841f51 356 }
bogdanm 13:0645d8841f51 357 break;
bogdanm 13:0645d8841f51 358 case 1: /* System oscillator */
bogdanm 13:0645d8841f51 359 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
bogdanm 13:0645d8841f51 360 SystemCoreClock = __SYS_OSC_CLK;
bogdanm 13:0645d8841f51 361 } else {
bogdanm 13:0645d8841f51 362 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
bogdanm 13:0645d8841f51 363 }
bogdanm 13:0645d8841f51 364 break;
bogdanm 13:0645d8841f51 365 case 2: /* Reserved */
bogdanm 13:0645d8841f51 366 case 3: /* Reserved */
bogdanm 13:0645d8841f51 367 SystemCoreClock = 0;
bogdanm 13:0645d8841f51 368 break;
bogdanm 13:0645d8841f51 369 }
bogdanm 13:0645d8841f51 370 break;
bogdanm 13:0645d8841f51 371 }
bogdanm 13:0645d8841f51 372
bogdanm 13:0645d8841f51 373 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
bogdanm 13:0645d8841f51 374
bogdanm 13:0645d8841f51 375 }
bogdanm 13:0645d8841f51 376
bogdanm 13:0645d8841f51 377 /**
bogdanm 13:0645d8841f51 378 * Initialize the system
bogdanm 13:0645d8841f51 379 *
bogdanm 13:0645d8841f51 380 * @param none
bogdanm 13:0645d8841f51 381 * @return none
bogdanm 13:0645d8841f51 382 *
bogdanm 13:0645d8841f51 383 * @brief Setup the microcontroller system.
bogdanm 13:0645d8841f51 384 * Initialize the System.
bogdanm 13:0645d8841f51 385 */
bogdanm 13:0645d8841f51 386 void SystemInit (void) {
bogdanm 13:0645d8841f51 387 volatile uint32_t i;
bogdanm 13:0645d8841f51 388
bogdanm 13:0645d8841f51 389 #if (CLOCK_SETUP) /* Clock Setup */
bogdanm 13:0645d8841f51 390
bogdanm 13:0645d8841f51 391 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
bogdanm 13:0645d8841f51 392 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
bogdanm 13:0645d8841f51 393 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
bogdanm 13:0645d8841f51 394 for (i = 0; i < 200; i++) __NOP();
bogdanm 13:0645d8841f51 395 #endif
bogdanm 13:0645d8841f51 396
bogdanm 13:0645d8841f51 397 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 13:0645d8841f51 398 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
bogdanm 13:0645d8841f51 399 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
bogdanm 13:0645d8841f51 400 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
bogdanm 13:0645d8841f51 401 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 13:0645d8841f51 402 #endif
bogdanm 13:0645d8841f51 403
bogdanm 13:0645d8841f51 404 #if (((MAINCLKSEL_Val & 0x03) == 2) )
bogdanm 13:0645d8841f51 405 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
bogdanm 13:0645d8841f51 406 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
bogdanm 13:0645d8841f51 407 for (i = 0; i < 200; i++) __NOP();
bogdanm 13:0645d8841f51 408 #endif
bogdanm 13:0645d8841f51 409
bogdanm 13:0645d8841f51 410 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
bogdanm 13:0645d8841f51 411
bogdanm 13:0645d8841f51 412 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
bogdanm 13:0645d8841f51 413
bogdanm 13:0645d8841f51 414 #if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
bogdanm 13:0645d8841f51 415 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
bogdanm 13:0645d8841f51 416
bogdanm 13:0645d8841f51 417 /* Regardless USB PLL is used as USB clock or not, USB PLL needs to be configured. */
bogdanm 13:0645d8841f51 418 LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
bogdanm 13:0645d8841f51 419 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
bogdanm 13:0645d8841f51 420 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
bogdanm 13:0645d8841f51 421 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
bogdanm 13:0645d8841f51 422
bogdanm 13:0645d8841f51 423 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
bogdanm 13:0645d8841f51 424 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
bogdanm 13:0645d8841f51 425
bogdanm 13:0645d8841f51 426 #else /* USB clock is not used */
bogdanm 13:0645d8841f51 427 LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
bogdanm 13:0645d8841f51 428 LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
bogdanm 13:0645d8841f51 429 #endif
bogdanm 13:0645d8841f51 430
bogdanm 13:0645d8841f51 431 #endif
bogdanm 13:0645d8841f51 432
bogdanm 13:0645d8841f51 433 /* System clock to the IOCON needs to be enabled or
bogdanm 13:0645d8841f51 434 most of the I/O related peripherals won't work. */
bogdanm 13:0645d8841f51 435 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
bogdanm 13:0645d8841f51 436
bogdanm 13:0645d8841f51 437 }